| T670 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.1161756584 |
|
|
Jul 17 08:38:17 PM PDT 24 |
Jul 17 08:48:03 PM PDT 24 |
3562993702 ps |
| T817 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.3648029959 |
|
|
Jul 17 09:00:09 PM PDT 24 |
Jul 17 09:09:47 PM PDT 24 |
5584953096 ps |
| T1154 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.3444099198 |
|
|
Jul 17 08:49:20 PM PDT 24 |
Jul 17 09:01:42 PM PDT 24 |
3683175282 ps |
| T1155 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.1545694421 |
|
|
Jul 17 08:48:58 PM PDT 24 |
Jul 17 08:54:09 PM PDT 24 |
2545082338 ps |
| T1156 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1993868908 |
|
|
Jul 17 08:29:03 PM PDT 24 |
Jul 17 08:35:43 PM PDT 24 |
5745927556 ps |
| T1157 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.3771406659 |
|
|
Jul 17 08:27:42 PM PDT 24 |
Jul 17 11:38:34 PM PDT 24 |
65823566484 ps |
| T1158 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3061661740 |
|
|
Jul 17 08:41:40 PM PDT 24 |
Jul 17 09:04:02 PM PDT 24 |
8433474900 ps |
| T340 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1910820304 |
|
|
Jul 17 08:45:08 PM PDT 24 |
Jul 17 09:12:36 PM PDT 24 |
12437639456 ps |
| T1159 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1226048264 |
|
|
Jul 17 08:45:26 PM PDT 24 |
Jul 17 08:56:12 PM PDT 24 |
8178805864 ps |
| T1160 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3910245384 |
|
|
Jul 17 08:29:18 PM PDT 24 |
Jul 17 08:32:35 PM PDT 24 |
2848370240 ps |
| T1161 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1216208220 |
|
|
Jul 17 08:37:12 PM PDT 24 |
Jul 17 09:05:37 PM PDT 24 |
11893665998 ps |
| T1162 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.4151663979 |
|
|
Jul 17 08:44:50 PM PDT 24 |
Jul 17 09:00:16 PM PDT 24 |
6440826225 ps |
| T1163 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.27607189 |
|
|
Jul 17 08:57:19 PM PDT 24 |
Jul 17 09:01:46 PM PDT 24 |
2947372880 ps |
| T1164 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2255193092 |
|
|
Jul 17 08:38:51 PM PDT 24 |
Jul 17 09:08:56 PM PDT 24 |
8513567028 ps |
| T131 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1436952327 |
|
|
Jul 17 08:52:45 PM PDT 24 |
Jul 17 09:02:50 PM PDT 24 |
7071004520 ps |
| T1165 |
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.4162343902 |
|
|
Jul 17 08:55:13 PM PDT 24 |
Jul 17 09:46:46 PM PDT 24 |
15494080426 ps |
| T391 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1999774966 |
|
|
Jul 17 08:34:35 PM PDT 24 |
Jul 17 08:46:01 PM PDT 24 |
4441285072 ps |
| T1166 |
/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.731450004 |
|
|
Jul 17 08:48:43 PM PDT 24 |
Jul 17 08:52:50 PM PDT 24 |
2344023084 ps |
| T784 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.1464137631 |
|
|
Jul 17 09:02:13 PM PDT 24 |
Jul 17 09:13:28 PM PDT 24 |
6035227960 ps |
| T472 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.2256773395 |
|
|
Jul 17 08:57:47 PM PDT 24 |
Jul 17 09:08:19 PM PDT 24 |
5873154492 ps |
| T1167 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3153818439 |
|
|
Jul 17 08:53:44 PM PDT 24 |
Jul 17 09:18:23 PM PDT 24 |
8806323416 ps |
| T1168 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3125095038 |
|
|
Jul 17 08:28:08 PM PDT 24 |
Jul 17 08:49:13 PM PDT 24 |
6792962440 ps |
| T1169 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3716539067 |
|
|
Jul 17 08:29:33 PM PDT 24 |
Jul 17 10:24:57 PM PDT 24 |
49532796230 ps |
| T1170 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.640428222 |
|
|
Jul 17 08:33:31 PM PDT 24 |
Jul 17 08:37:33 PM PDT 24 |
2974423560 ps |
| T1171 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2697445563 |
|
|
Jul 17 08:56:20 PM PDT 24 |
Jul 17 09:05:47 PM PDT 24 |
7015929412 ps |
| T750 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.3106248216 |
|
|
Jul 17 08:59:52 PM PDT 24 |
Jul 17 09:08:45 PM PDT 24 |
5527141912 ps |
| T1172 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1905755413 |
|
|
Jul 17 08:40:57 PM PDT 24 |
Jul 17 08:45:53 PM PDT 24 |
3104094324 ps |
| T1173 |
/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1945179534 |
|
|
Jul 17 08:42:44 PM PDT 24 |
Jul 17 08:56:17 PM PDT 24 |
6641988012 ps |
| T1174 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.3356673099 |
|
|
Jul 17 08:34:42 PM PDT 24 |
Jul 17 08:53:30 PM PDT 24 |
6197510422 ps |
| T1175 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3367210310 |
|
|
Jul 17 08:49:31 PM PDT 24 |
Jul 17 08:55:51 PM PDT 24 |
2854831638 ps |
| T1176 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.104163454 |
|
|
Jul 17 08:33:00 PM PDT 24 |
Jul 17 09:08:27 PM PDT 24 |
8585278326 ps |
| T1177 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.370939819 |
|
|
Jul 17 08:34:24 PM PDT 24 |
Jul 17 08:56:28 PM PDT 24 |
7057806868 ps |
| T1178 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.196050709 |
|
|
Jul 17 08:36:17 PM PDT 24 |
Jul 17 09:08:20 PM PDT 24 |
10688015767 ps |
| T387 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4042659710 |
|
|
Jul 17 08:39:35 PM PDT 24 |
Jul 17 08:45:03 PM PDT 24 |
5716757178 ps |
| T1179 |
/workspace/coverage/default/1.chip_sw_aes_idle.321314304 |
|
|
Jul 17 08:36:47 PM PDT 24 |
Jul 17 08:40:29 PM PDT 24 |
3277928356 ps |
| T1180 |
/workspace/coverage/default/2.chip_sw_example_flash.2972066054 |
|
|
Jul 17 08:44:29 PM PDT 24 |
Jul 17 08:47:48 PM PDT 24 |
2858634152 ps |
| T1181 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3286067666 |
|
|
Jul 17 08:45:10 PM PDT 24 |
Jul 17 09:08:39 PM PDT 24 |
14207506628 ps |
| T1182 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.4118159634 |
|
|
Jul 17 08:29:22 PM PDT 24 |
Jul 17 09:40:01 PM PDT 24 |
18447522544 ps |
| T1183 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.546807694 |
|
|
Jul 17 08:35:13 PM PDT 24 |
Jul 17 09:11:11 PM PDT 24 |
7843255480 ps |
| T760 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.4186197155 |
|
|
Jul 17 09:01:55 PM PDT 24 |
Jul 17 09:08:14 PM PDT 24 |
2962003140 ps |
| T1184 |
/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3342432664 |
|
|
Jul 17 08:31:09 PM PDT 24 |
Jul 17 08:36:21 PM PDT 24 |
3463135802 ps |
| T417 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.799579083 |
|
|
Jul 17 08:39:39 PM PDT 24 |
Jul 17 08:48:27 PM PDT 24 |
9352304779 ps |
| T821 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.3760440837 |
|
|
Jul 17 08:58:56 PM PDT 24 |
Jul 17 09:09:22 PM PDT 24 |
4980357488 ps |
| T1185 |
/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.1408333088 |
|
|
Jul 17 08:52:40 PM PDT 24 |
Jul 17 10:04:56 PM PDT 24 |
19870660080 ps |
| T1186 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.536358790 |
|
|
Jul 17 08:47:42 PM PDT 24 |
Jul 17 08:55:00 PM PDT 24 |
6217218148 ps |
| T1187 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1048289506 |
|
|
Jul 17 08:53:34 PM PDT 24 |
Jul 17 09:13:00 PM PDT 24 |
13698169825 ps |
| T1188 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3329711279 |
|
|
Jul 17 08:34:13 PM PDT 24 |
Jul 17 08:43:41 PM PDT 24 |
5104576458 ps |
| T1189 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.2603201011 |
|
|
Jul 17 08:34:07 PM PDT 24 |
Jul 17 08:38:08 PM PDT 24 |
2773519392 ps |
| T1190 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.203380158 |
|
|
Jul 17 08:36:56 PM PDT 24 |
Jul 17 08:59:33 PM PDT 24 |
13319566629 ps |
| T685 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3590469343 |
|
|
Jul 17 08:30:00 PM PDT 24 |
Jul 17 08:38:08 PM PDT 24 |
4559620695 ps |
| T365 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3144897835 |
|
|
Jul 17 08:27:55 PM PDT 24 |
Jul 17 08:41:01 PM PDT 24 |
5369964808 ps |
| T161 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.454894842 |
|
|
Jul 17 08:45:16 PM PDT 24 |
Jul 17 08:50:07 PM PDT 24 |
2850652392 ps |
| T1191 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1591050446 |
|
|
Jul 17 08:32:59 PM PDT 24 |
Jul 17 08:42:35 PM PDT 24 |
4450069216 ps |
| T1192 |
/workspace/coverage/default/2.chip_sw_aes_entropy.4073909315 |
|
|
Jul 17 08:46:43 PM PDT 24 |
Jul 17 08:51:58 PM PDT 24 |
3137516608 ps |
| T1193 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.1146729700 |
|
|
Jul 17 08:54:59 PM PDT 24 |
Jul 17 09:58:06 PM PDT 24 |
15341978242 ps |
| T186 |
/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1819317707 |
|
|
Jul 17 08:37:27 PM PDT 24 |
Jul 17 08:45:35 PM PDT 24 |
5062042240 ps |
| T1194 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.175214592 |
|
|
Jul 17 08:34:20 PM PDT 24 |
Jul 17 08:39:20 PM PDT 24 |
2302344857 ps |
| T378 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1674740646 |
|
|
Jul 17 08:51:53 PM PDT 24 |
Jul 17 08:59:01 PM PDT 24 |
3911308690 ps |
| T1195 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2949205204 |
|
|
Jul 17 08:50:56 PM PDT 24 |
Jul 17 08:56:57 PM PDT 24 |
3869449167 ps |
| T262 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1056085661 |
|
|
Jul 17 08:33:30 PM PDT 24 |
Jul 17 08:47:54 PM PDT 24 |
6284569768 ps |
| T1196 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.1169466936 |
|
|
Jul 17 08:42:46 PM PDT 24 |
Jul 17 08:45:58 PM PDT 24 |
1976628808 ps |
| T1197 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.3038567860 |
|
|
Jul 17 08:51:51 PM PDT 24 |
Jul 17 09:02:30 PM PDT 24 |
3275936586 ps |
| T1198 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.144484189 |
|
|
Jul 17 08:28:54 PM PDT 24 |
Jul 17 08:33:30 PM PDT 24 |
3179733938 ps |
| T1199 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.1942546937 |
|
|
Jul 17 09:02:17 PM PDT 24 |
Jul 17 09:12:05 PM PDT 24 |
6002756732 ps |
| T1200 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.161940723 |
|
|
Jul 17 08:41:26 PM PDT 24 |
Jul 17 08:44:45 PM PDT 24 |
2805290054 ps |
| T1201 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3552506604 |
|
|
Jul 17 08:58:19 PM PDT 24 |
Jul 17 09:03:53 PM PDT 24 |
3359163240 ps |
| T729 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.3136812054 |
|
|
Jul 17 09:01:10 PM PDT 24 |
Jul 17 09:08:57 PM PDT 24 |
5382073520 ps |
| T1202 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3119596229 |
|
|
Jul 17 08:34:36 PM PDT 24 |
Jul 17 08:51:12 PM PDT 24 |
12974442191 ps |
| T1203 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.887216048 |
|
|
Jul 17 08:38:08 PM PDT 24 |
Jul 17 08:48:19 PM PDT 24 |
4644842104 ps |
| T240 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.4149696925 |
|
|
Jul 17 08:36:50 PM PDT 24 |
Jul 17 10:07:37 PM PDT 24 |
47225120525 ps |
| T1204 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.3324579980 |
|
|
Jul 17 08:30:22 PM PDT 24 |
Jul 17 08:39:10 PM PDT 24 |
4309527656 ps |
| T1205 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2530376650 |
|
|
Jul 17 09:01:56 PM PDT 24 |
Jul 17 09:10:48 PM PDT 24 |
5753690624 ps |
| T1206 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.1266008716 |
|
|
Jul 17 08:30:59 PM PDT 24 |
Jul 17 08:36:43 PM PDT 24 |
2501989096 ps |
| T1207 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2248889004 |
|
|
Jul 17 08:39:39 PM PDT 24 |
Jul 17 09:43:43 PM PDT 24 |
15824044400 ps |
| T799 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.4085505696 |
|
|
Jul 17 08:57:43 PM PDT 24 |
Jul 17 09:06:31 PM PDT 24 |
4195196456 ps |
| T1208 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter.4206348302 |
|
|
Jul 17 08:39:02 PM PDT 24 |
Jul 17 08:44:00 PM PDT 24 |
2932153883 ps |
| T1209 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1727521911 |
|
|
Jul 17 08:30:46 PM PDT 24 |
Jul 17 08:42:56 PM PDT 24 |
10098490454 ps |
| T819 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2266143615 |
|
|
Jul 17 08:58:16 PM PDT 24 |
Jul 17 09:07:37 PM PDT 24 |
3216485768 ps |
| T1210 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.3266207551 |
|
|
Jul 17 08:29:46 PM PDT 24 |
Jul 17 08:41:34 PM PDT 24 |
3557412220 ps |
| T1211 |
/workspace/coverage/default/0.chip_tap_straps_dev.546490377 |
|
|
Jul 17 08:30:55 PM PDT 24 |
Jul 17 08:35:18 PM PDT 24 |
3944442015 ps |
| T1212 |
/workspace/coverage/default/0.chip_sw_hmac_enc.2836880607 |
|
|
Jul 17 08:30:51 PM PDT 24 |
Jul 17 08:35:26 PM PDT 24 |
3613690712 ps |
| T1213 |
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1233003477 |
|
|
Jul 17 09:01:14 PM PDT 24 |
Jul 17 09:08:34 PM PDT 24 |
4029862310 ps |
| T1214 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_dev.772195055 |
|
|
Jul 17 08:33:11 PM PDT 24 |
Jul 17 09:25:39 PM PDT 24 |
26146386650 ps |
| T1215 |
/workspace/coverage/default/0.chip_tap_straps_testunlock0.4061446095 |
|
|
Jul 17 08:38:08 PM PDT 24 |
Jul 17 08:44:29 PM PDT 24 |
4675340620 ps |
| T1216 |
/workspace/coverage/default/2.chip_sw_kmac_app_rom.4055235553 |
|
|
Jul 17 08:47:35 PM PDT 24 |
Jul 17 08:51:10 PM PDT 24 |
2150519822 ps |
| T1217 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.955480735 |
|
|
Jul 17 08:42:18 PM PDT 24 |
Jul 17 08:47:31 PM PDT 24 |
3346508850 ps |
| T1218 |
/workspace/coverage/default/2.chip_sw_hmac_enc.4228638735 |
|
|
Jul 17 08:47:39 PM PDT 24 |
Jul 17 08:51:37 PM PDT 24 |
2757891536 ps |
| T1219 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3139664226 |
|
|
Jul 17 08:37:57 PM PDT 24 |
Jul 17 08:43:50 PM PDT 24 |
2844332897 ps |
| T1220 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1200865813 |
|
|
Jul 17 08:28:38 PM PDT 24 |
Jul 17 08:37:17 PM PDT 24 |
5142671076 ps |
| T1221 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3754727224 |
|
|
Jul 17 08:34:24 PM PDT 24 |
Jul 17 09:36:02 PM PDT 24 |
14581823733 ps |
| T1222 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2009770419 |
|
|
Jul 17 08:37:05 PM PDT 24 |
Jul 17 08:47:05 PM PDT 24 |
4021019424 ps |
| T1223 |
/workspace/coverage/default/1.rom_e2e_self_hash.738373698 |
|
|
Jul 17 08:44:21 PM PDT 24 |
Jul 17 10:16:26 PM PDT 24 |
25835734572 ps |
| T1224 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.461335574 |
|
|
Jul 17 08:58:36 PM PDT 24 |
Jul 17 09:06:52 PM PDT 24 |
5164008670 ps |
| T181 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3671921926 |
|
|
Jul 17 08:43:58 PM PDT 24 |
Jul 17 10:14:20 PM PDT 24 |
44888094150 ps |
| T1225 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.261910669 |
|
|
Jul 17 08:48:15 PM PDT 24 |
Jul 17 09:23:27 PM PDT 24 |
10296381818 ps |
| T1226 |
/workspace/coverage/default/2.chip_sival_flash_info_access.2376561455 |
|
|
Jul 17 08:43:46 PM PDT 24 |
Jul 17 08:49:03 PM PDT 24 |
2621730200 ps |
| T228 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2713274269 |
|
|
Jul 17 08:48:35 PM PDT 24 |
Jul 17 09:14:27 PM PDT 24 |
8315284200 ps |
| T1227 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1241855893 |
|
|
Jul 17 08:29:34 PM PDT 24 |
Jul 17 08:55:27 PM PDT 24 |
9335979960 ps |
| T782 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3781913454 |
|
|
Jul 17 08:58:48 PM PDT 24 |
Jul 17 09:04:25 PM PDT 24 |
4136816404 ps |
| T1228 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.3710487199 |
|
|
Jul 17 08:54:03 PM PDT 24 |
Jul 17 08:59:00 PM PDT 24 |
3406554980 ps |
| T1229 |
/workspace/coverage/default/1.chip_sw_flash_init.4237196443 |
|
|
Jul 17 08:33:33 PM PDT 24 |
Jul 17 09:02:41 PM PDT 24 |
23111937045 ps |
| T395 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2318497950 |
|
|
Jul 17 08:50:31 PM PDT 24 |
Jul 17 08:54:06 PM PDT 24 |
2849153674 ps |
| T1230 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.1143153405 |
|
|
Jul 17 08:35:51 PM PDT 24 |
Jul 17 08:40:43 PM PDT 24 |
3133530968 ps |
| T1231 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.679555988 |
|
|
Jul 17 08:38:12 PM PDT 24 |
Jul 17 09:39:12 PM PDT 24 |
14656921833 ps |
| T798 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.2602082183 |
|
|
Jul 17 09:04:10 PM PDT 24 |
Jul 17 09:14:44 PM PDT 24 |
4585918112 ps |
| T1232 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2709782817 |
|
|
Jul 17 08:51:58 PM PDT 24 |
Jul 17 09:09:18 PM PDT 24 |
5560363256 ps |
| T135 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3087519928 |
|
|
Jul 17 08:48:10 PM PDT 24 |
Jul 17 08:56:26 PM PDT 24 |
4922890184 ps |
| T42 |
/workspace/coverage/default/2.chip_sw_gpio.370235338 |
|
|
Jul 17 08:50:24 PM PDT 24 |
Jul 17 08:59:56 PM PDT 24 |
4577821484 ps |
| T1233 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.735980221 |
|
|
Jul 17 08:28:34 PM PDT 24 |
Jul 17 08:36:39 PM PDT 24 |
3467515928 ps |
| T1234 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1161384609 |
|
|
Jul 17 08:49:11 PM PDT 24 |
Jul 17 09:52:30 PM PDT 24 |
18283449024 ps |
| T1235 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.103330788 |
|
|
Jul 17 08:58:34 PM PDT 24 |
Jul 17 09:17:14 PM PDT 24 |
13961171703 ps |
| T1236 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3404990929 |
|
|
Jul 17 08:36:34 PM PDT 24 |
Jul 17 09:28:40 PM PDT 24 |
11145820047 ps |
| T747 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.914306872 |
|
|
Jul 17 08:54:07 PM PDT 24 |
Jul 17 09:02:28 PM PDT 24 |
4679458856 ps |
| T1237 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1346937426 |
|
|
Jul 17 08:33:49 PM PDT 24 |
Jul 17 08:44:01 PM PDT 24 |
5183809743 ps |
| T771 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.2302531754 |
|
|
Jul 17 08:59:37 PM PDT 24 |
Jul 17 09:10:12 PM PDT 24 |
5770131432 ps |
| T718 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.1614823503 |
|
|
Jul 17 08:32:57 PM PDT 24 |
Jul 17 09:05:50 PM PDT 24 |
11606933992 ps |
| T1238 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4240079280 |
|
|
Jul 17 08:33:42 PM PDT 24 |
Jul 17 08:46:54 PM PDT 24 |
4651903120 ps |
| T1239 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.551824000 |
|
|
Jul 17 08:54:20 PM PDT 24 |
Jul 17 09:06:22 PM PDT 24 |
3935990712 ps |
| T751 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.2010105218 |
|
|
Jul 17 09:02:13 PM PDT 24 |
Jul 17 09:14:11 PM PDT 24 |
6140804504 ps |
| T1240 |
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2096155386 |
|
|
Jul 17 09:01:59 PM PDT 24 |
Jul 17 09:08:10 PM PDT 24 |
4007861872 ps |
| T301 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.988081522 |
|
|
Jul 17 09:01:17 PM PDT 24 |
Jul 17 09:06:25 PM PDT 24 |
3260967000 ps |
| T1241 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3290296381 |
|
|
Jul 17 08:28:23 PM PDT 24 |
Jul 17 08:37:33 PM PDT 24 |
4596564216 ps |
| T1242 |
/workspace/coverage/default/1.chip_sw_hmac_smoketest.1747501329 |
|
|
Jul 17 08:42:01 PM PDT 24 |
Jul 17 08:49:07 PM PDT 24 |
3548326082 ps |
| T1243 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.3949350445 |
|
|
Jul 17 08:57:55 PM PDT 24 |
Jul 17 09:05:17 PM PDT 24 |
4684234640 ps |
| T1244 |
/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1212079388 |
|
|
Jul 17 08:57:22 PM PDT 24 |
Jul 17 09:06:24 PM PDT 24 |
4637513464 ps |
| T792 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.568276722 |
|
|
Jul 17 08:58:37 PM PDT 24 |
Jul 17 09:03:26 PM PDT 24 |
3806253160 ps |
| T809 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1915872707 |
|
|
Jul 17 08:54:58 PM PDT 24 |
Jul 17 09:00:47 PM PDT 24 |
3583118800 ps |
| T755 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.3614388700 |
|
|
Jul 17 08:58:33 PM PDT 24 |
Jul 17 09:07:09 PM PDT 24 |
4478512986 ps |
| T1245 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3811281490 |
|
|
Jul 17 08:38:24 PM PDT 24 |
Jul 17 09:28:57 PM PDT 24 |
12123774024 ps |
| T1246 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.4049704318 |
|
|
Jul 17 08:31:31 PM PDT 24 |
Jul 17 08:35:07 PM PDT 24 |
3434152470 ps |
| T140 |
/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1526630606 |
|
|
Jul 17 08:41:59 PM PDT 24 |
Jul 17 09:31:09 PM PDT 24 |
22212227801 ps |
| T1247 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.3422656998 |
|
|
Jul 17 08:57:29 PM PDT 24 |
Jul 17 09:08:53 PM PDT 24 |
8105872140 ps |
| T374 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.201987177 |
|
|
Jul 17 08:33:15 PM PDT 24 |
Jul 17 08:41:43 PM PDT 24 |
4595670826 ps |
| T785 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3786402783 |
|
|
Jul 17 08:58:29 PM PDT 24 |
Jul 17 09:05:47 PM PDT 24 |
3473718372 ps |
| T155 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.2531688189 |
|
|
Jul 17 08:39:40 PM PDT 24 |
Jul 17 08:50:34 PM PDT 24 |
3547244684 ps |
| T1248 |
/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.4064340177 |
|
|
Jul 17 08:58:19 PM PDT 24 |
Jul 17 09:08:03 PM PDT 24 |
4125428842 ps |
| T1249 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3561788380 |
|
|
Jul 17 08:50:49 PM PDT 24 |
Jul 17 09:03:49 PM PDT 24 |
4500323712 ps |
| T1250 |
/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1812027932 |
|
|
Jul 17 08:28:12 PM PDT 24 |
Jul 17 08:41:01 PM PDT 24 |
6297860392 ps |
| T1251 |
/workspace/coverage/default/1.chip_tap_straps_dev.845039189 |
|
|
Jul 17 08:39:12 PM PDT 24 |
Jul 17 09:06:59 PM PDT 24 |
14640146291 ps |
| T1252 |
/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3558610311 |
|
|
Jul 17 08:42:03 PM PDT 24 |
Jul 17 08:51:53 PM PDT 24 |
3775685840 ps |
| T1253 |
/workspace/coverage/default/2.rom_e2e_self_hash.3691494887 |
|
|
Jul 17 08:55:36 PM PDT 24 |
Jul 17 10:27:25 PM PDT 24 |
26337607880 ps |
| T726 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3683691786 |
|
|
Jul 17 08:56:05 PM PDT 24 |
Jul 17 09:01:09 PM PDT 24 |
3792069504 ps |
| T1254 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3725066949 |
|
|
Jul 17 08:31:16 PM PDT 24 |
Jul 17 08:51:58 PM PDT 24 |
5889178728 ps |
| T1255 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.2125196316 |
|
|
Jul 17 08:57:07 PM PDT 24 |
Jul 17 09:05:18 PM PDT 24 |
4803522210 ps |
| T820 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1149814082 |
|
|
Jul 17 09:01:14 PM PDT 24 |
Jul 17 09:09:47 PM PDT 24 |
4612135168 ps |
| T9 |
/workspace/coverage/default/1.chip_jtag_csr_rw.469539723 |
|
|
Jul 17 08:31:38 PM PDT 24 |
Jul 17 08:55:04 PM PDT 24 |
12481121852 ps |
| T434 |
/workspace/coverage/default/2.chip_sw_hmac_oneshot.1212952060 |
|
|
Jul 17 08:48:30 PM PDT 24 |
Jul 17 08:53:30 PM PDT 24 |
3052101400 ps |
| T204 |
/workspace/coverage/default/1.chip_jtag_mem_access.311253278 |
|
|
Jul 17 08:31:37 PM PDT 24 |
Jul 17 08:56:43 PM PDT 24 |
13988921536 ps |
| T435 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3608875113 |
|
|
Jul 17 08:30:46 PM PDT 24 |
Jul 17 08:39:26 PM PDT 24 |
6583523448 ps |
| T436 |
/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3240398922 |
|
|
Jul 17 08:29:46 PM PDT 24 |
Jul 17 08:38:56 PM PDT 24 |
4197402120 ps |
| T437 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3545577412 |
|
|
Jul 17 08:45:36 PM PDT 24 |
Jul 17 09:04:11 PM PDT 24 |
5618155319 ps |
| T438 |
/workspace/coverage/default/0.chip_sw_example_flash.2278277263 |
|
|
Jul 17 08:28:24 PM PDT 24 |
Jul 17 08:31:31 PM PDT 24 |
1925024732 ps |
| T439 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2935182664 |
|
|
Jul 17 08:30:07 PM PDT 24 |
Jul 17 08:41:57 PM PDT 24 |
4534579432 ps |
| T440 |
/workspace/coverage/default/0.rom_volatile_raw_unlock.4169223168 |
|
|
Jul 17 08:34:21 PM PDT 24 |
Jul 17 08:36:10 PM PDT 24 |
3055980048 ps |
| T441 |
/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.4213604914 |
|
|
Jul 17 08:30:55 PM PDT 24 |
Jul 17 08:35:09 PM PDT 24 |
3118450986 ps |
| T1256 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.119030948 |
|
|
Jul 17 08:29:59 PM PDT 24 |
Jul 17 08:42:19 PM PDT 24 |
7753730090 ps |
| T1257 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2747409547 |
|
|
Jul 17 08:36:36 PM PDT 24 |
Jul 17 09:49:30 PM PDT 24 |
15185740462 ps |
| T1258 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2802109632 |
|
|
Jul 17 08:46:45 PM PDT 24 |
Jul 17 09:45:38 PM PDT 24 |
19484812572 ps |
| T1259 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.123297209 |
|
|
Jul 17 08:35:15 PM PDT 24 |
Jul 17 09:03:04 PM PDT 24 |
23989014884 ps |
| T1260 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.922289258 |
|
|
Jul 17 08:58:41 PM PDT 24 |
Jul 17 09:08:20 PM PDT 24 |
4245314790 ps |
| T388 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.548085040 |
|
|
Jul 17 09:04:20 PM PDT 24 |
Jul 17 09:11:02 PM PDT 24 |
3827598060 ps |
| T1261 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2311511907 |
|
|
Jul 17 08:29:34 PM PDT 24 |
Jul 17 08:31:31 PM PDT 24 |
2551314500 ps |
| T1262 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4256645251 |
|
|
Jul 17 08:36:03 PM PDT 24 |
Jul 17 08:45:02 PM PDT 24 |
19192525550 ps |
| T802 |
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1304201674 |
|
|
Jul 17 09:03:45 PM PDT 24 |
Jul 17 09:11:06 PM PDT 24 |
3749944140 ps |
| T1263 |
/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3365209453 |
|
|
Jul 17 08:49:42 PM PDT 24 |
Jul 17 09:19:54 PM PDT 24 |
22040881305 ps |
| T1264 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1675966081 |
|
|
Jul 17 08:50:15 PM PDT 24 |
Jul 17 09:03:11 PM PDT 24 |
7961625460 ps |
| T1265 |
/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2138064995 |
|
|
Jul 17 08:47:33 PM PDT 24 |
Jul 17 08:52:11 PM PDT 24 |
2712554868 ps |
| T1266 |
/workspace/coverage/default/2.chip_sw_flash_init.343189427 |
|
|
Jul 17 08:44:32 PM PDT 24 |
Jul 17 09:23:38 PM PDT 24 |
22014880057 ps |
| T1267 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.4089665710 |
|
|
Jul 17 08:29:55 PM PDT 24 |
Jul 17 08:32:58 PM PDT 24 |
3570891863 ps |
| T1268 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2528784750 |
|
|
Jul 17 08:36:05 PM PDT 24 |
Jul 17 08:38:44 PM PDT 24 |
2377794693 ps |
| T1269 |
/workspace/coverage/default/1.chip_sw_otbn_randomness.1590346789 |
|
|
Jul 17 08:36:31 PM PDT 24 |
Jul 17 08:49:53 PM PDT 24 |
5744902448 ps |
| T1270 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.36288728 |
|
|
Jul 17 08:53:37 PM PDT 24 |
Jul 17 08:59:14 PM PDT 24 |
3338195208 ps |
| T748 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.3757278969 |
|
|
Jul 17 08:54:21 PM PDT 24 |
Jul 17 09:02:29 PM PDT 24 |
5103196700 ps |
| T1271 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.3869664250 |
|
|
Jul 17 08:52:09 PM PDT 24 |
Jul 17 08:56:51 PM PDT 24 |
2832858600 ps |
| T1272 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1826418424 |
|
|
Jul 17 08:33:18 PM PDT 24 |
Jul 17 08:42:07 PM PDT 24 |
10028682316 ps |
| T1273 |
/workspace/coverage/default/1.chip_sw_aes_entropy.2454815234 |
|
|
Jul 17 08:39:14 PM PDT 24 |
Jul 17 08:43:29 PM PDT 24 |
3194609498 ps |
| T1274 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1239703591 |
|
|
Jul 17 08:30:14 PM PDT 24 |
Jul 17 08:35:30 PM PDT 24 |
4196216000 ps |
| T776 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.1967645411 |
|
|
Jul 17 08:58:19 PM PDT 24 |
Jul 17 09:06:10 PM PDT 24 |
4684747464 ps |
| T15 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.4170965641 |
|
|
Jul 17 08:32:34 PM PDT 24 |
Jul 17 08:55:20 PM PDT 24 |
22737443832 ps |
| T1275 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2058843237 |
|
|
Jul 17 08:54:49 PM PDT 24 |
Jul 17 09:12:38 PM PDT 24 |
8202010876 ps |
| T1276 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2210070341 |
|
|
Jul 17 08:48:53 PM PDT 24 |
Jul 17 09:42:27 PM PDT 24 |
20260866386 ps |
| T1277 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2450129837 |
|
|
Jul 17 08:38:39 PM PDT 24 |
Jul 17 08:42:43 PM PDT 24 |
3170466824 ps |
| T1278 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.156325688 |
|
|
Jul 17 08:38:52 PM PDT 24 |
Jul 17 08:44:15 PM PDT 24 |
3899625982 ps |
| T1279 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3303183114 |
|
|
Jul 17 08:46:23 PM PDT 24 |
Jul 17 08:51:23 PM PDT 24 |
4196381194 ps |
| T1280 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2370061903 |
|
|
Jul 17 08:53:39 PM PDT 24 |
Jul 17 09:11:12 PM PDT 24 |
11216079538 ps |
| T1281 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.3921703152 |
|
|
Jul 17 08:38:04 PM PDT 24 |
Jul 17 09:43:48 PM PDT 24 |
14001697272 ps |
| T1282 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.3339669537 |
|
|
Jul 17 08:41:22 PM PDT 24 |
Jul 17 08:49:18 PM PDT 24 |
3435504468 ps |
| T1283 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4257854677 |
|
|
Jul 17 08:35:20 PM PDT 24 |
Jul 17 08:37:08 PM PDT 24 |
2822914159 ps |
| T1284 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.995033070 |
|
|
Jul 17 08:57:45 PM PDT 24 |
Jul 17 09:07:01 PM PDT 24 |
5564931900 ps |
| T1285 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.438931812 |
|
|
Jul 17 08:30:07 PM PDT 24 |
Jul 17 08:45:02 PM PDT 24 |
6885821380 ps |
| T1286 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.111799037 |
|
|
Jul 17 09:01:23 PM PDT 24 |
Jul 17 09:11:53 PM PDT 24 |
6206766700 ps |
| T1287 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.7784769 |
|
|
Jul 17 08:48:32 PM PDT 24 |
Jul 17 09:25:00 PM PDT 24 |
11249329440 ps |
| T1288 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.1104359664 |
|
|
Jul 17 08:47:08 PM PDT 24 |
Jul 17 09:54:16 PM PDT 24 |
14454607162 ps |
| T1289 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.4174853999 |
|
|
Jul 17 09:04:10 PM PDT 24 |
Jul 17 09:13:55 PM PDT 24 |
4391526452 ps |
| T310 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.3494507081 |
|
|
Jul 17 08:39:27 PM PDT 24 |
Jul 17 08:43:58 PM PDT 24 |
2386737412 ps |
| T1290 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.249196046 |
|
|
Jul 17 08:38:22 PM PDT 24 |
Jul 17 08:48:07 PM PDT 24 |
3706341384 ps |
| T1291 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.990577670 |
|
|
Jul 17 08:51:45 PM PDT 24 |
Jul 17 09:05:02 PM PDT 24 |
4165280144 ps |
| T1292 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.4105652624 |
|
|
Jul 17 08:49:46 PM PDT 24 |
Jul 17 09:08:58 PM PDT 24 |
6465045358 ps |
| T1293 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.4173984739 |
|
|
Jul 17 08:59:53 PM PDT 24 |
Jul 17 09:07:11 PM PDT 24 |
4720541096 ps |
| T1294 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.720473333 |
|
|
Jul 17 08:49:58 PM PDT 24 |
Jul 17 08:58:01 PM PDT 24 |
3919530835 ps |
| T25 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3341094998 |
|
|
Jul 17 08:28:07 PM PDT 24 |
Jul 17 08:34:01 PM PDT 24 |
3741842764 ps |
| T756 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.305154561 |
|
|
Jul 17 09:01:50 PM PDT 24 |
Jul 17 09:11:28 PM PDT 24 |
5876310142 ps |
| T1295 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1935373025 |
|
|
Jul 17 09:00:34 PM PDT 24 |
Jul 17 09:06:28 PM PDT 24 |
3339200078 ps |
| T1296 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3797137573 |
|
|
Jul 17 08:39:35 PM PDT 24 |
Jul 17 09:44:10 PM PDT 24 |
25257153972 ps |
| T164 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.2156816425 |
|
|
Jul 17 08:52:19 PM PDT 24 |
Jul 17 09:01:32 PM PDT 24 |
5159413304 ps |
| T717 |
/workspace/coverage/default/0.rom_raw_unlock.844177673 |
|
|
Jul 17 08:31:39 PM PDT 24 |
Jul 17 08:35:55 PM PDT 24 |
7064122270 ps |
| T1297 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.147776914 |
|
|
Jul 17 09:00:42 PM PDT 24 |
Jul 17 09:12:18 PM PDT 24 |
5289058410 ps |
| T1298 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.1264794474 |
|
|
Jul 17 08:53:03 PM PDT 24 |
Jul 17 09:11:12 PM PDT 24 |
6464644092 ps |
| T319 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2444923167 |
|
|
Jul 17 08:50:08 PM PDT 24 |
Jul 17 09:00:52 PM PDT 24 |
7763590681 ps |
| T1299 |
/workspace/coverage/default/2.chip_tap_straps_rma.1856356288 |
|
|
Jul 17 08:50:02 PM PDT 24 |
Jul 17 08:56:04 PM PDT 24 |
4639649446 ps |
| T137 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.4016862393 |
|
|
Jul 17 08:38:53 PM PDT 24 |
Jul 17 08:55:38 PM PDT 24 |
8457549720 ps |
| T786 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.2062262627 |
|
|
Jul 17 09:06:03 PM PDT 24 |
Jul 17 09:16:56 PM PDT 24 |
6258710312 ps |
| T1300 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3739881254 |
|
|
Jul 17 08:30:50 PM PDT 24 |
Jul 17 08:47:47 PM PDT 24 |
5078503590 ps |
| T1301 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.2367360305 |
|
|
Jul 17 08:45:38 PM PDT 24 |
Jul 17 08:59:29 PM PDT 24 |
7643248231 ps |
| T749 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.4145013361 |
|
|
Jul 17 08:58:56 PM PDT 24 |
Jul 17 09:09:27 PM PDT 24 |
4915033446 ps |
| T66 |
/workspace/coverage/default/1.chip_sw_alert_test.509678314 |
|
|
Jul 17 08:41:43 PM PDT 24 |
Jul 17 08:46:10 PM PDT 24 |
2398749872 ps |
| T1302 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.891685840 |
|
|
Jul 17 08:32:48 PM PDT 24 |
Jul 17 08:41:56 PM PDT 24 |
4535141984 ps |
| T263 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.2973209001 |
|
|
Jul 17 08:56:36 PM PDT 24 |
Jul 17 09:05:25 PM PDT 24 |
5910580776 ps |
| T1303 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3452818053 |
|
|
Jul 17 08:52:27 PM PDT 24 |
Jul 17 09:03:22 PM PDT 24 |
3813456000 ps |
| T1304 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2029229453 |
|
|
Jul 17 08:46:45 PM PDT 24 |
Jul 17 09:10:38 PM PDT 24 |
8144168190 ps |
| T1305 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.732252719 |
|
|
Jul 17 08:38:18 PM PDT 24 |
Jul 17 08:48:21 PM PDT 24 |
4001823900 ps |
| T822 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2765283278 |
|
|
Jul 17 09:00:24 PM PDT 24 |
Jul 17 09:07:06 PM PDT 24 |
3847757794 ps |
| T1306 |
/workspace/coverage/default/0.chip_sw_example_concurrency.366441308 |
|
|
Jul 17 08:30:42 PM PDT 24 |
Jul 17 08:35:42 PM PDT 24 |
2797272808 ps |
| T1307 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.442714941 |
|
|
Jul 17 08:54:07 PM PDT 24 |
Jul 17 09:04:09 PM PDT 24 |
3972692120 ps |
| T813 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.2783075996 |
|
|
Jul 17 08:54:27 PM PDT 24 |
Jul 17 09:03:18 PM PDT 24 |
5858689808 ps |
| T1308 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2940201560 |
|
|
Jul 17 08:39:00 PM PDT 24 |
Jul 17 09:04:03 PM PDT 24 |
6484715120 ps |
| T1309 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3796193535 |
|
|
Jul 17 09:02:14 PM PDT 24 |
Jul 17 09:09:26 PM PDT 24 |
4280423638 ps |
| T1310 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.244732314 |
|
|
Jul 17 08:36:02 PM PDT 24 |
Jul 17 09:50:56 PM PDT 24 |
17777038452 ps |
| T1311 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.3930898820 |
|
|
Jul 17 08:43:41 PM PDT 24 |
Jul 17 08:54:56 PM PDT 24 |
5163422218 ps |
| T1312 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3903914622 |
|
|
Jul 17 08:43:21 PM PDT 24 |
Jul 17 09:07:02 PM PDT 24 |
12408951504 ps |
| T1313 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3909425344 |
|
|
Jul 17 08:28:34 PM PDT 24 |
Jul 17 08:40:42 PM PDT 24 |
4444511258 ps |
| T1314 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2808976235 |
|
|
Jul 17 08:49:08 PM PDT 24 |
Jul 17 09:00:55 PM PDT 24 |
4226006292 ps |
| T1315 |
/workspace/coverage/default/0.chip_sw_hmac_oneshot.4074686600 |
|
|
Jul 17 08:30:33 PM PDT 24 |
Jul 17 08:35:12 PM PDT 24 |
3282372904 ps |
| T1316 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.189817229 |
|
|
Jul 17 08:32:32 PM PDT 24 |
Jul 17 08:37:32 PM PDT 24 |
3390517123 ps |
| T1317 |
/workspace/coverage/default/0.chip_sw_aes_entropy.929562371 |
|
|
Jul 17 08:30:53 PM PDT 24 |
Jul 17 08:35:41 PM PDT 24 |
2791916772 ps |
| T1318 |
/workspace/coverage/default/1.chip_sw_power_idle_load.3731817451 |
|
|
Jul 17 08:43:09 PM PDT 24 |
Jul 17 08:55:53 PM PDT 24 |
4814581080 ps |
| T1319 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.4198471893 |
|
|
Jul 17 08:28:27 PM PDT 24 |
Jul 17 08:37:20 PM PDT 24 |
3741951250 ps |
| T1320 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2645188677 |
|
|
Jul 17 08:57:33 PM PDT 24 |
Jul 17 09:05:43 PM PDT 24 |
3534598888 ps |
| T1321 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod.4174173279 |
|
|
Jul 17 08:38:24 PM PDT 24 |
Jul 17 09:37:04 PM PDT 24 |
15805399234 ps |
| T1322 |
/workspace/coverage/default/1.chip_sw_example_rom.3617296676 |
|
|
Jul 17 08:31:57 PM PDT 24 |
Jul 17 08:34:08 PM PDT 24 |
2362395610 ps |
| T1323 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3059620405 |
|
|
Jul 17 08:37:41 PM PDT 24 |
Jul 17 08:47:32 PM PDT 24 |
4461118970 ps |
| T1324 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.396416776 |
|
|
Jul 17 08:46:25 PM PDT 24 |
Jul 17 09:35:43 PM PDT 24 |
14968318700 ps |
| T1325 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3119608541 |
|
|
Jul 17 08:58:45 PM PDT 24 |
Jul 17 09:04:48 PM PDT 24 |
3464820528 ps |
| T1326 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3783266105 |
|
|
Jul 17 08:32:38 PM PDT 24 |
Jul 17 08:37:04 PM PDT 24 |
2848512608 ps |
| T337 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.2475925217 |
|
|
Jul 17 08:48:54 PM PDT 24 |
Jul 17 09:05:06 PM PDT 24 |
5237736196 ps |
| T804 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.892765476 |
|
|
Jul 17 08:59:42 PM PDT 24 |
Jul 17 09:08:09 PM PDT 24 |
4347365296 ps |
| T1327 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.85073400 |
|
|
Jul 17 08:34:24 PM PDT 24 |
Jul 17 09:29:03 PM PDT 24 |
15611145744 ps |
| T1328 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2486473844 |
|
|
Jul 17 08:36:44 PM PDT 24 |
Jul 17 09:56:31 PM PDT 24 |
17918627452 ps |
| T320 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2647657074 |
|
|
Jul 17 08:38:16 PM PDT 24 |
Jul 17 08:52:15 PM PDT 24 |
8476778687 ps |
| T1329 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2476934720 |
|
|
Jul 17 08:29:30 PM PDT 24 |
Jul 17 08:31:36 PM PDT 24 |
2933014918 ps |