Module Definition
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Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rsp_intg_gen

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp.u_intg_gen

Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2511100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
47 1 1
48 1 1
49 1 1
53 1 1


Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 )
Line Coverage for Module self-instances :
SCORELINE
83.33 66.67
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_rsp_intg_gen

SCORELINE
83.33 66.67
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_rsp_intg_gen

SCORELINE
83.33 66.67
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_rsp_intg_gen

SCORELINE
83.33 66.67
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_rsp_intg_gen

Line No.TotalCoveredPercent
TOTAL6466.67
CONT_ASSIGN32100.00
CONT_ASSIGN43100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 0 1
43 0 1
47 1 1
48 1 1
49 1 1
53 1 1


Assert Coverage for Module : tlul_rsp_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 20658 20658 0 0
PayLoadWidthCheck 20658 20658 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 20658 20658 0 0
T4 9 9 0 0
T5 9 9 0 0
T6 9 9 0 0
T15 9 9 0 0
T16 9 9 0 0
T41 9 9 0 0
T64 9 9 0 0
T65 9 9 0 0
T96 9 9 0 0
T97 9 9 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 20658 20658 0 0
T4 9 9 0 0
T5 9 9 0 0
T6 9 9 0 0
T15 9 9 0 0
T16 9 9 0 0
T41 9 9 0 0
T64 9 9 0 0
T65 9 9 0 0
T96 9 9 0 0
T97 9 9 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%