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Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.25 99.72 97.27 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_data_intg.u_tlul_data_integ_enc 100.00 100.00
gen_rsp_intg.u_rsp_gen 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_rsp_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 66.67 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 66.67 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.98 100.00 95.92 100.00 100.00 u_reg_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.41 100.00 69.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_data_intg.u_tlul_data_integ_enc 100.00 100.00
gen_rsp_intg.u_rsp_gen 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_rsp_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 66.67 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 66.67 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.91 97.37 78.26 100.00 100.00 u_reg_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.98 100.00 99.90 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_data_intg.u_tlul_data_integ_enc 100.00 100.00
gen_rsp_intg.u_rsp_gen 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_rsp_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 66.67 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 66.67 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.46 100.00 97.83 100.00 100.00 u_reg_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

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Module Instances:
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_rsp_intg_gen
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_rsp_intg_gen
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_rsp_intg_gen
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2511100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
47 1 1
48 1 1
49 1 1
53 1 1


Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 2932 2932 0 0
PayLoadWidthCheck 2932 2932 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2932 2932 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T41 1 1 0 0
T64 1 1 0 0
T65 1 1 0 0
T96 1 1 0 0
T97 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 2932 2932 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T41 1 1 0 0
T64 1 1 0 0
T65 1 1 0 0
T96 1 1 0 0
T97 1 1 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_rsp_intg_gen
Line No.TotalCoveredPercent
TOTAL6466.67
CONT_ASSIGN32100.00
CONT_ASSIGN43100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 0 1
43 0 1
47 1 1
48 1 1
49 1 1
53 1 1


Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_rsp_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 2932 2932 0 0
PayLoadWidthCheck 2932 2932 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2932 2932 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T41 1 1 0 0
T64 1 1 0 0
T65 1 1 0 0
T96 1 1 0 0
T97 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 2932 2932 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T41 1 1 0 0
T64 1 1 0 0
T65 1 1 0 0
T96 1 1 0 0
T97 1 1 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2511100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
47 1 1
48 1 1
49 1 1
53 1 1


Assert Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 1022 1022 0 0
PayLoadWidthCheck 1022 1022 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1022 1022 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T41 1 1 0 0
T64 1 1 0 0
T65 1 1 0 0
T96 1 1 0 0
T97 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 1022 1022 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T41 1 1 0 0
T64 1 1 0 0
T65 1 1 0 0
T96 1 1 0 0
T97 1 1 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_rsp_intg_gen
Line No.TotalCoveredPercent
TOTAL6466.67
CONT_ASSIGN32100.00
CONT_ASSIGN43100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 0 1
43 0 1
47 1 1
48 1 1
49 1 1
53 1 1


Assert Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_rsp_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 1022 1022 0 0
PayLoadWidthCheck 1022 1022 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1022 1022 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T41 1 1 0 0
T64 1 1 0 0
T65 1 1 0 0
T96 1 1 0 0
T97 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 1022 1022 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T41 1 1 0 0
T64 1 1 0 0
T65 1 1 0 0
T96 1 1 0 0
T97 1 1 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2511100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
47 1 1
48 1 1
49 1 1
53 1 1


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 2932 2932 0 0
PayLoadWidthCheck 2932 2932 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2932 2932 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T41 1 1 0 0
T64 1 1 0 0
T65 1 1 0 0
T96 1 1 0 0
T97 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 2932 2932 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T41 1 1 0 0
T64 1 1 0 0
T65 1 1 0 0
T96 1 1 0 0
T97 1 1 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_rsp_intg_gen
Line No.TotalCoveredPercent
TOTAL6466.67
CONT_ASSIGN32100.00
CONT_ASSIGN43100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 0 1
43 0 1
47 1 1
48 1 1
49 1 1
53 1 1


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_rsp_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 2932 2932 0 0
PayLoadWidthCheck 2932 2932 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2932 2932 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T41 1 1 0 0
T64 1 1 0 0
T65 1 1 0 0
T96 1 1 0 0
T97 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 2932 2932 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T41 1 1 0 0
T64 1 1 0 0
T65 1 1 0 0
T96 1 1 0 0
T97 1 1 0 0

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