Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : pinmux_strap_sampling
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.83 99.34 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling 99.83 99.34 100.00 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.83 99.34 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.82 99.62 95.65 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
88.98 98.83 80.56 98.84 74.68 92.00 u_pinmux_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_pinmux_jtag_buf_dft 100.00 100.00
u_pinmux_jtag_buf_lc 100.00 100.00
u_pinmux_jtag_buf_rv 100.00 100.00
u_por_scanmode_sync 100.00 100.00
u_prim_lc_or_hardened 100.00 100.00 100.00 100.00
u_prim_lc_sender_pinmux_hw_debug_en 100.00 100.00 100.00
u_prim_lc_sync_lc_check_byp_en 100.00 100.00 100.00 100.00
u_prim_lc_sync_lc_dft_en 100.00 100.00 100.00 100.00
u_prim_lc_sync_lc_escalate_en 100.00 100.00 100.00 100.00
u_prim_lc_sync_lc_hw_debug_en 100.00 100.00 100.00 100.00
u_prim_lc_sync_pinmux_hw_debug_en 100.00 100.00 100.00
u_rst_por_aon_n_mux 85.19 100.00 55.56 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : pinmux_strap_sampling
Line No.TotalCoveredPercent
TOTAL30330199.34
CONT_ASSIGN13211100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN15311100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN23011100.00
CONT_ASSIGN23211100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN24011100.00
CONT_ASSIGN24111100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN25911100.00
ALWAYS26299100.00
ALWAYS28399100.00
CONT_ASSIGN30811100.00
ALWAYS3121717100.00
CONT_ASSIGN37111100.00
CONT_ASSIGN37211100.00
CONT_ASSIGN37311100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN40011100.00
CONT_ASSIGN40111100.00
CONT_ASSIGN40411100.00
CONT_ASSIGN40411100.00
CONT_ASSIGN40411100.00
CONT_ASSIGN40411100.00
CONT_ASSIGN40511100.00
CONT_ASSIGN40511100.00
CONT_ASSIGN40511100.00
CONT_ASSIGN40511100.00
CONT_ASSIGN41211100.00
CONT_ASSIGN41211100.00
CONT_ASSIGN41411100.00
CONT_ASSIGN41411100.00
CONT_ASSIGN41411100.00
CONT_ASSIGN41711100.00
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CONT_ASSIGN42011100.00
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CONT_ASSIGN42011100.00
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CONT_ASSIGN42011100.00
CONT_ASSIGN42011100.00
CONT_ASSIGN42011100.00
CONT_ASSIGN42011100.00
CONT_ASSIGN42011100.00
CONT_ASSIGN42011100.00
CONT_ASSIGN42011100.00
CONT_ASSIGN42011100.00
CONT_ASSIGN42011100.00
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CONT_ASSIGN42011100.00
CONT_ASSIGN42011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
132 1 1
133 1 1
153 1 1
157 1 1
187 1 1
230 1 1
232 1 1
236 1 1
240 1 1
241 1 1
242 1 1
259 1 1
262 1 1
263 1 1
264 1 1
268 1 1
269 1 1
MISSING_ELSE
274 1 1
275 1 1
276 1 1
277 1 1
MISSING_ELSE
MISSING_ELSE
283 1 1
284 1 1
285 1 1
286 1 1
287 1 1
289 1 1
290 1 1
291 1 1
292 1 1
308 1 1
312 1 1
315 1 1
316 1 1
317 1 1
319 1 1
321 1 1
323 1 1
324 1 1
325 1 1
328 1 1
329 1 1
330 1 1
331 1 1
MISSING_ELSE
335 1 1
336 1 1
337 1 1
338 1 1
MISSING_ELSE
371 1 1
372 1 1
373 1 1
396 5 5
400 1 1
401 1 1
404 4 4
405 4 4
412 2 2
414 3 3
417 58 58
418 58 58
419 56 58
420 58 58


Cond Coverage for Module : pinmux_strap_sampling
TotalCoveredPercent
Conditions5555100.00
Logical5555100.00
Non-Logical00
Event00

 LINE       230
 EXPRESSION (lc_strap_sample_en ? in_padring_i[30] : tap_strap_q[0])
             ---------1--------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       232
 EXPRESSION (rv_strap_sample_en ? in_padring_i[27] : tap_strap_q[1])
             ---------1--------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       236
 EXPRESSION (dft_strap_sample_en ? ({in_padring_i[42], in_padring_i[40]}) : dft_strap_q)
             ---------1---------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       240
 EXPRESSION (dft_strap_sample_en | dft_strap_valid_q)
             ---------1---------   --------2--------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT4,T5,T6

 LINE       268
 EXPRESSION (strap_en_q && tap_sampling_en)
             -----1----    -------2-------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT58,T59,T132
11CoveredT4,T5,T6

 LINE       274
 EXPRESSION (strap_en_q || tap_sampling_en)
             -----1----    -------2-------
-1--2-StatusTests
00CoveredT5,T16,T64
01CoveredT4,T5,T6
10CoveredT58,T59,T132

 LINE       396
 EXPRESSION (jtag_en ? 1'b0 : in_padring_i[35])
             ---1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT57,T58,T59

 LINE       396
 EXPRESSION (jtag_en ? 1'b0 : in_padring_i[36])
             ---1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT57,T58,T59

 LINE       396
 EXPRESSION (jtag_en ? 1'b0 : in_padring_i[37])
             ---1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT57,T58,T59

 LINE       396
 EXPRESSION (jtag_en ? 1'b0 : in_padring_i[38])
             ---1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT57,T58,T59

 LINE       396
 EXPRESSION (jtag_en ? 1'b0 : in_padring_i[39])
             ---1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT57,T58,T59

 LINE       400
 EXPRESSION (jtag_en ? jtag_rsp.tdo : out_core_i[36])
             ---1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT57,T58,T59

 LINE       401
 EXPRESSION (jtag_en ? jtag_rsp.tdo_oe : oe_core_i[36])
             ---1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT57,T58,T59

 LINE       404
 EXPRESSION (jtag_en ? 1'b0 : out_core_i[35])
             ---1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT57,T58,T59

 LINE       404
 EXPRESSION (jtag_en ? 1'b0 : out_core_i[37])
             ---1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT57,T58,T59

 LINE       404
 EXPRESSION (jtag_en ? 1'b0 : out_core_i[38])
             ---1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT57,T58,T59

 LINE       404
 EXPRESSION (jtag_en ? 1'b0 : out_core_i[39])
             ---1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT57,T58,T59

 LINE       405
 EXPRESSION (jtag_en ? 1'b0 : oe_core_i[35])
             ---1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT57,T58,T59

 LINE       405
 EXPRESSION (jtag_en ? 1'b0 : oe_core_i[37])
             ---1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT57,T58,T59

 LINE       405
 EXPRESSION (jtag_en ? 1'b0 : oe_core_i[38])
             ---1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT57,T58,T59

 LINE       405
 EXPRESSION (jtag_en ? 1'b0 : oe_core_i[39])
             ---1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT57,T58,T59

 LINE       412
 EXPRESSION 
 Number  Term
      1  jtag_en ? ('{schmitt_en:1'b1, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0}) : attr_core_i[38])
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT57,T58,T59

 LINE       412
 EXPRESSION 
 Number  Term
      1  jtag_en ? ('{schmitt_en:1'b1, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0}) : attr_core_i[39])
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT57,T58,T59

 LINE       414
 EXPRESSION (jtag_en ? '0 : attr_core_i[35])
             ---1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT57,T58,T59

 LINE       414
 EXPRESSION (jtag_en ? '0 : attr_core_i[36])
             ---1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT57,T58,T59

 LINE       414
 EXPRESSION (jtag_en ? '0 : attr_core_i[37])
             ---1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT57,T58,T59

Branch Coverage for Module : pinmux_strap_sampling
Line No.TotalCoveredPercent
Branches 59 59 100.00
TERNARY 230 2 2 100.00
TERNARY 232 2 2 100.00
TERNARY 236 2 2 100.00
TERNARY 396 2 2 100.00
TERNARY 404 2 2 100.00
TERNARY 405 2 2 100.00
TERNARY 414 2 2 100.00
TERNARY 396 2 2 100.00
TERNARY 400 2 2 100.00
TERNARY 401 2 2 100.00
TERNARY 414 2 2 100.00
TERNARY 396 2 2 100.00
TERNARY 404 2 2 100.00
TERNARY 405 2 2 100.00
TERNARY 414 2 2 100.00
TERNARY 396 2 2 100.00
TERNARY 404 2 2 100.00
TERNARY 405 2 2 100.00
TERNARY 412 2 2 100.00
TERNARY 396 2 2 100.00
TERNARY 404 2 2 100.00
TERNARY 405 2 2 100.00
TERNARY 412 2 2 100.00
IF 268 2 2 100.00
IF 274 3 3 100.00
IF 283 2 2 100.00
CASE 321 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 230 (lc_strap_sample_en) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 232 (rv_strap_sample_en) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 236 (dft_strap_sample_en) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 396 (jtag_en) ?

Branches:
-1-StatusTests
1 Covered T57,T58,T59
0 Covered T4,T5,T6


LineNo. Expression -1-: 404 (jtag_en) ?

Branches:
-1-StatusTests
1 Covered T57,T58,T59
0 Covered T4,T5,T6


LineNo. Expression -1-: 405 (jtag_en) ?

Branches:
-1-StatusTests
1 Covered T57,T58,T59
0 Covered T4,T5,T6


LineNo. Expression -1-: 414 (jtag_en) ?

Branches:
-1-StatusTests
1 Covered T57,T58,T59
0 Covered T4,T5,T6


LineNo. Expression -1-: 396 (jtag_en) ?

Branches:
-1-StatusTests
1 Covered T57,T58,T59
0 Covered T4,T5,T6


LineNo. Expression -1-: 400 (jtag_en) ?

Branches:
-1-StatusTests
1 Covered T57,T58,T59
0 Covered T4,T5,T6


LineNo. Expression -1-: 401 (jtag_en) ?

Branches:
-1-StatusTests
1 Covered T57,T58,T59
0 Covered T4,T5,T6


LineNo. Expression -1-: 414 (jtag_en) ?

Branches:
-1-StatusTests
1 Covered T57,T58,T59
0 Covered T4,T5,T6


LineNo. Expression -1-: 396 (jtag_en) ?

Branches:
-1-StatusTests
1 Covered T57,T58,T59
0 Covered T4,T5,T6


LineNo. Expression -1-: 404 (jtag_en) ?

Branches:
-1-StatusTests
1 Covered T57,T58,T59
0 Covered T4,T5,T6


LineNo. Expression -1-: 405 (jtag_en) ?

Branches:
-1-StatusTests
1 Covered T57,T58,T59
0 Covered T4,T5,T6


LineNo. Expression -1-: 414 (jtag_en) ?

Branches:
-1-StatusTests
1 Covered T57,T58,T59
0 Covered T4,T5,T6


LineNo. Expression -1-: 396 (jtag_en) ?

Branches:
-1-StatusTests
1 Covered T57,T58,T59
0 Covered T4,T5,T6


LineNo. Expression -1-: 404 (jtag_en) ?

Branches:
-1-StatusTests
1 Covered T57,T58,T59
0 Covered T4,T5,T6


LineNo. Expression -1-: 405 (jtag_en) ?

Branches:
-1-StatusTests
1 Covered T57,T58,T59
0 Covered T4,T5,T6


LineNo. Expression -1-: 412 (jtag_en) ?

Branches:
-1-StatusTests
1 Covered T57,T58,T59
0 Covered T4,T5,T6


LineNo. Expression -1-: 396 (jtag_en) ?

Branches:
-1-StatusTests
1 Covered T57,T58,T59
0 Covered T4,T5,T6


LineNo. Expression -1-: 404 (jtag_en) ?

Branches:
-1-StatusTests
1 Covered T57,T58,T59
0 Covered T4,T5,T6


LineNo. Expression -1-: 405 (jtag_en) ?

Branches:
-1-StatusTests
1 Covered T57,T58,T59
0 Covered T4,T5,T6


LineNo. Expression -1-: 412 (jtag_en) ?

Branches:
-1-StatusTests
1 Covered T57,T58,T59
0 Covered T4,T5,T6


LineNo. Expression -1-: 268 if ((strap_en_q && tap_sampling_en))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 274 if ((strap_en_q || tap_sampling_en)) -2-: 276 if (lc_ctrl_pkg::lc_tx_test_true_strict(pinmux_hw_debug_en[HwDebugEnSample]))

Branches:
-1--2-StatusTests
1 1 Covered T4,T5,T6
1 0 Covered T4,T5,T6
0 - Covered T5,T16,T64


LineNo. Expression -1-: 283 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 321 case (tap_strap) -2-: 328 if (lc_ctrl_pkg::lc_tx_test_true_strict(pinmux_hw_debug_en[HwDebugEnTapSel])) -3-: 335 if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_dft_en[DftEnTapSel]))

Branches:
-1--2--3-StatusTests
LcTapSel - - Covered T57,T58,T59
RvTapSel 1 - Covered T72,T73,T8
RvTapSel 0 - Covered T73,T736,T737
DftTapSel - 1 Covered T74,T71,T76
DftTapSel - 0 Covered T738
default - - Covered T4,T5,T6


Assert Coverage for Module : pinmux_strap_sampling
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 17 17 100.00 17 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 17 17 100.00 17 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DftTapOff0_A 130890987 40524088 0 290
LcHwDebugEnClear_A 130890987 11931473 0 15
LcHwDebugEnSetRev0_A 130890987 1472 0 104
LcHwDebugEnSetRev1_A 130890987 1472 0 104
LcHwDebugEnSet_A 130890987 1472 0 0
RvTapOff0_A 130890987 258 0 208
RvTapOff1_A 130890987 37535139 0 0
TapStrapKnown_A 130890987 130207015 0 0
dft_strap0_idxRange_A 1022 1022 0 0
dft_strap1_idxRange_A 1022 1022 0 0
tap_strap0_idxRange_A 1022 1022 0 0
tap_strap1_idxRange_A 1022 1022 0 0
tck_idxRange_A 1022 1022 0 0
tdi_idxRange_A 1022 1022 0 0
tdo_idxRange_A 1022 1022 0 0
tms_idxRange_A 1022 1022 0 0
trst_idxRange_A 1022 1022 0 0


DftTapOff0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 130890987 40524088 0 290
T2 0 0 0 2
T4 212528 2483 0 0
T5 63982 19515 0 0
T6 65553 2481 0 0
T15 84724 2482 0 0
T16 286572 2481 0 0
T17 0 0 0 2
T41 65692 10067 0 0
T52 0 0 0 2
T58 0 0 0 2
T59 0 0 0 2
T64 41448 5840 0 0
T65 40256 2484 0 0
T72 0 0 0 2
T96 23962 2481 0 0
T97 52474 2481 0 0
T112 0 0 0 2
T132 0 0 0 2
T169 0 0 0 2
T280 0 0 0 2

LcHwDebugEnClear_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 130890987 11931473 0 15
T5 63982 14550 0 0
T6 65553 0 0 0
T15 84724 0 0 0
T16 286572 0 0 0
T41 65692 5102 0 0
T54 0 10203 0 0
T55 0 905842 0 0
T56 0 905578 0 0
T64 41448 0 0 0
T65 40256 0 0 0
T67 0 0 0 1
T68 0 12213 0 0
T91 0 5104 0 0
T96 23962 0 0 0
T97 52474 0 0 0
T173 0 0 0 1
T174 0 0 0 1
T175 0 0 0 1
T200 0 5103 0 0
T201 19421 0 0 0
T228 0 5103 0 0
T359 0 5072 0 0
T739 0 0 0 1
T740 0 0 0 1
T741 0 0 0 1
T742 0 0 0 1
T743 0 0 0 1
T744 0 0 0 1

LcHwDebugEnSetRev0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 130890987 1472 0 104
T2 0 0 0 1
T4 212528 1 0 0
T5 63982 2 0 0
T6 65553 1 0 0
T15 84724 1 0 0
T16 286572 1 0 0
T17 0 0 0 1
T41 65692 2 0 0
T52 0 0 0 1
T58 0 0 0 1
T59 0 0 0 1
T64 41448 1 0 0
T65 40256 1 0 0
T67 0 0 0 1
T96 23962 1 0 0
T97 52474 1 0 0
T112 0 0 0 1
T132 0 0 0 1
T169 0 0 0 1
T280 0 0 0 1

LcHwDebugEnSetRev1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 130890987 1472 0 104
T2 0 0 0 1
T4 212528 1 0 0
T5 63982 2 0 0
T6 65553 1 0 0
T15 84724 1 0 0
T16 286572 1 0 0
T17 0 0 0 1
T41 65692 2 0 0
T52 0 0 0 1
T58 0 0 0 1
T59 0 0 0 1
T64 41448 1 0 0
T65 40256 1 0 0
T67 0 0 0 1
T96 23962 1 0 0
T97 52474 1 0 0
T112 0 0 0 1
T132 0 0 0 1
T169 0 0 0 1
T280 0 0 0 1

LcHwDebugEnSet_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 130890987 1472 0 0
T4 212528 1 0 0
T5 63982 2 0 0
T6 65553 1 0 0
T15 84724 1 0 0
T16 286572 1 0 0
T41 65692 2 0 0
T64 41448 1 0 0
T65 40256 1 0 0
T96 23962 1 0 0
T97 52474 1 0 0

RvTapOff0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 130890987 258 0 208
T2 0 1 0 2
T17 483950 0 0 2
T18 0 1 0 0
T52 0 1 0 2
T53 306322 0 0 0
T55 0 1 0 0
T56 0 3 0 0
T58 13863 1 0 2
T59 9241 1 0 2
T67 0 0 0 2
T68 157546 0 0 0
T112 0 0 0 2
T132 0 2 0 2
T160 600687 0 0 0
T169 0 1 0 2
T225 269353 0 0 0
T262 102342 0 0 0
T263 32219 0 0 0
T280 0 1 0 2
T339 34603 0 0 0

RvTapOff1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 130890987 37535139 0 0
T4 212528 3144 0 0
T5 63982 19828 0 0
T6 65553 2939 0 0
T15 84724 2882 0 0
T16 286572 2683 0 0
T41 65692 10504 0 0
T64 41448 2950 0 0
T65 40256 2875 0 0
T96 23962 2766 0 0
T97 52474 2835 0 0

TapStrapKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 130890987 130207015 0 0
T4 212528 211800 0 0
T5 63982 63599 0 0
T6 65553 64814 0 0
T15 84724 84015 0 0
T16 286572 286252 0 0
T41 65692 65093 0 0
T64 41448 40668 0 0
T65 40256 39842 0 0
T96 23962 23522 0 0
T97 52474 51855 0 0

dft_strap0_idxRange_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1022 1022 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T41 1 1 0 0
T64 1 1 0 0
T65 1 1 0 0
T96 1 1 0 0
T97 1 1 0 0

dft_strap1_idxRange_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1022 1022 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T41 1 1 0 0
T64 1 1 0 0
T65 1 1 0 0
T96 1 1 0 0
T97 1 1 0 0

tap_strap0_idxRange_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1022 1022 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T41 1 1 0 0
T64 1 1 0 0
T65 1 1 0 0
T96 1 1 0 0
T97 1 1 0 0

tap_strap1_idxRange_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1022 1022 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T41 1 1 0 0
T64 1 1 0 0
T65 1 1 0 0
T96 1 1 0 0
T97 1 1 0 0

tck_idxRange_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1022 1022 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T41 1 1 0 0
T64 1 1 0 0
T65 1 1 0 0
T96 1 1 0 0
T97 1 1 0 0

tdi_idxRange_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1022 1022 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T41 1 1 0 0
T64 1 1 0 0
T65 1 1 0 0
T96 1 1 0 0
T97 1 1 0 0

tdo_idxRange_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1022 1022 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T41 1 1 0 0
T64 1 1 0 0
T65 1 1 0 0
T96 1 1 0 0
T97 1 1 0 0

tms_idxRange_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1022 1022 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T41 1 1 0 0
T64 1 1 0 0
T65 1 1 0 0
T96 1 1 0 0
T97 1 1 0 0

trst_idxRange_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1022 1022 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T41 1 1 0 0
T64 1 1 0 0
T65 1 1 0 0
T96 1 1 0 0
T97 1 1 0 0

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