Module Definition
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Module : prim_mubi4_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.83 99.34 100.00 100.00 100.00 u_pinmux_strap_sampling


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Assert Coverage for Module : prim_mubi4_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1022 1022 0 0
OutputsKnown_A 130890987 130207015 0 0
gen_no_flops.OutputDelay_A 130890987 130207015 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1022 1022 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T41 1 1 0 0
T64 1 1 0 0
T65 1 1 0 0
T96 1 1 0 0
T97 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 130890987 130207015 0 0
T4 212528 211800 0 0
T5 63982 63599 0 0
T6 65553 64814 0 0
T15 84724 84015 0 0
T16 286572 286252 0 0
T41 65692 65093 0 0
T64 41448 40668 0 0
T65 40256 39842 0 0
T96 23962 23522 0 0
T97 52474 51855 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 130890987 130207015 0 0
T4 212528 211800 0 0
T5 63982 63599 0 0
T6 65553 64814 0 0
T15 84724 84015 0 0
T16 286572 286252 0 0
T41 65692 65093 0 0
T64 41448 40668 0 0
T65 40256 39842 0 0
T96 23962 23522 0 0
T97 52474 51855 0 0

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1022 1022 0 0
OutputsKnown_A 130890987 130207015 0 0
gen_no_flops.OutputDelay_A 130890987 130207015 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1022 1022 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T41 1 1 0 0
T64 1 1 0 0
T65 1 1 0 0
T96 1 1 0 0
T97 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 130890987 130207015 0 0
T4 212528 211800 0 0
T5 63982 63599 0 0
T6 65553 64814 0 0
T15 84724 84015 0 0
T16 286572 286252 0 0
T41 65692 65093 0 0
T64 41448 40668 0 0
T65 40256 39842 0 0
T96 23962 23522 0 0
T97 52474 51855 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 130890987 130207015 0 0
T4 212528 211800 0 0
T5 63982 63599 0 0
T6 65553 64814 0 0
T15 84724 84015 0 0
T16 286572 286252 0 0
T41 65692 65093 0 0
T64 41448 40668 0 0
T65 40256 39842 0 0
T96 23962 23522 0 0
T97 52474 51855 0 0

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