Unified Coverage Report :: Module :: sensor_ctrl_reg_top

Module : sensor_ctrl_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	100.00	69.65			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg	92.41	100.00	69.65			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	100.00	69.65			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.72	90.70	82.88			93.29	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.38	93.69	89.00	79.23		100.00	100.00	u_sensor_ctrl_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_en_0	100.00	100.00	100.00			100.00
u_alert_en_1	100.00	100.00	100.00			100.00
u_alert_en_10	100.00	100.00	100.00			100.00
u_alert_en_2	100.00	100.00	100.00			100.00
u_alert_en_3	100.00	100.00	100.00			100.00
u_alert_en_4	100.00	100.00	100.00			100.00
u_alert_en_5	100.00	100.00	100.00			100.00
u_alert_en_6	100.00	100.00	100.00			100.00
u_alert_en_7	100.00	100.00	100.00			100.00
u_alert_en_8	100.00	100.00	100.00			100.00
u_alert_en_9	100.00	100.00	100.00			100.00
u_alert_test_fatal_alert	100.00	100.00
u_alert_test_recov_alert	100.00	100.00
u_alert_trig_val_0	100.00	100.00	100.00			100.00
u_alert_trig_val_1	100.00	100.00	100.00			100.00
u_alert_trig_val_10	100.00	100.00	100.00			100.00
u_alert_trig_val_2	100.00	100.00	100.00			100.00
u_alert_trig_val_3	100.00	100.00	100.00			100.00
u_alert_trig_val_4	100.00	100.00	100.00			100.00
u_alert_trig_val_5	100.00	100.00	100.00			100.00
u_alert_trig_val_6	100.00	100.00	100.00			100.00
u_alert_trig_val_7	100.00	100.00	100.00			100.00
u_alert_trig_val_8	100.00	100.00	100.00			100.00
u_alert_trig_val_9	100.00	100.00	100.00			100.00
u_cfg_regwen	51.48	44.44	50.00			60.00
u_chk	100.00	100.00					100.00
u_fatal_alert_en_val_0	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_1	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_10	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_2	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_3	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_4	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_5	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_6	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_7	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_8	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_9	96.30	88.89	100.00			100.00
u_fatal_alert_val_0	96.30	88.89	100.00			100.00
u_fatal_alert_val_1	47.78	33.33	50.00			60.00
u_fatal_alert_val_10	47.78	33.33	50.00			60.00
u_fatal_alert_val_11	96.30	88.89	100.00			100.00
u_fatal_alert_val_2	96.30	88.89	100.00			100.00
u_fatal_alert_val_3	47.78	33.33	50.00			60.00
u_fatal_alert_val_4	96.30	88.89	100.00			100.00
u_fatal_alert_val_5	47.78	33.33	50.00			60.00
u_fatal_alert_val_6	96.30	88.89	100.00			100.00
u_fatal_alert_val_7	47.78	33.33	50.00			60.00
u_fatal_alert_val_8	47.78	33.33	50.00			60.00
u_fatal_alert_val_9	47.78	33.33	50.00			60.00
u_intr_enable_init_status_change	100.00	100.00	100.00			100.00
u_intr_enable_io_status_change	100.00	100.00	100.00			100.00
u_intr_state_init_status_change	100.00	100.00	100.00			100.00
u_intr_state_io_status_change	100.00	100.00	100.00			100.00
u_intr_test_init_status_change	100.00	100.00
u_intr_test_io_status_change	100.00	100.00
u_manual_pad_attr_0_input_disable_0	80.00	80.00
u_manual_pad_attr_0_pull_en_0	80.00	80.00
u_manual_pad_attr_0_pull_select_0	80.00	80.00
u_manual_pad_attr_1_input_disable_1	80.00	80.00
u_manual_pad_attr_1_pull_en_1	80.00	80.00
u_manual_pad_attr_1_pull_select_1	80.00	80.00
u_manual_pad_attr_2_input_disable_2	80.00	80.00
u_manual_pad_attr_2_pull_en_2	80.00	80.00
u_manual_pad_attr_2_pull_select_2	80.00	80.00
u_manual_pad_attr_3_input_disable_3	80.00	80.00
u_manual_pad_attr_3_pull_en_3	80.00	80.00
u_manual_pad_attr_3_pull_select_3	80.00	80.00
u_manual_pad_attr_regwen_0	51.48	44.44	50.00			60.00
u_manual_pad_attr_regwen_1	51.48	44.44	50.00			60.00
u_manual_pad_attr_regwen_2	51.48	44.44	50.00			60.00
u_manual_pad_attr_regwen_3	51.48	44.44	50.00			60.00
u_prim_reg_we_check	100.00	100.00
u_recov_alert_val_0	100.00	100.00	100.00			100.00
u_recov_alert_val_1	100.00	100.00	100.00			100.00
u_recov_alert_val_10	100.00	100.00	100.00			100.00
u_recov_alert_val_2	100.00	100.00	100.00			100.00
u_recov_alert_val_3	100.00	100.00	100.00			100.00
u_recov_alert_val_4	100.00	100.00	100.00			100.00
u_recov_alert_val_5	100.00	100.00	100.00			100.00
u_recov_alert_val_6	100.00	100.00	100.00			100.00
u_recov_alert_val_7	100.00	100.00	100.00			100.00
u_recov_alert_val_8	100.00	100.00	100.00			100.00
u_recov_alert_val_9	100.00	100.00	100.00			100.00
u_reg_if	89.30	94.29	76.54			86.36	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_status_ast_init_done	62.59	77.78	50.00			60.00
u_status_io_pok	62.59	77.78	50.00			60.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sensor_ctrl_reg_top

	Line No.	Total	Covered	Percent
TOTAL		296	296	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	435	1	1	100.00
CONT_ASSIGN	451	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	823	1	1	100.00
CONT_ASSIGN	855	1	1	100.00
CONT_ASSIGN	887	1	1	100.00
CONT_ASSIGN	919	1	1	100.00
CONT_ASSIGN	951	1	1	100.00
CONT_ASSIGN	983	1	1	100.00
CONT_ASSIGN	1015	1	1	100.00
CONT_ASSIGN	1047	1	1	100.00
CONT_ASSIGN	1079	1	1	100.00
CONT_ASSIGN	1111	1	1	100.00
CONT_ASSIGN	1143	1	1	100.00
CONT_ASSIGN	1175	1	1	100.00
CONT_ASSIGN	2277	1	1	100.00
CONT_ASSIGN	2280	1	1	100.00
CONT_ASSIGN	2295	1	1	100.00
CONT_ASSIGN	2311	1	1	100.00
CONT_ASSIGN	2327	1	1	100.00
CONT_ASSIGN	2334	1	1	100.00
CONT_ASSIGN	2337	1	1	100.00
CONT_ASSIGN	2352	1	1	100.00
CONT_ASSIGN	2368	1	1	100.00
CONT_ASSIGN	2384	1	1	100.00
CONT_ASSIGN	2391	1	1	100.00
CONT_ASSIGN	2394	1	1	100.00
CONT_ASSIGN	2409	1	1	100.00
CONT_ASSIGN	2425	1	1	100.00
CONT_ASSIGN	2441	1	1	100.00
CONT_ASSIGN	2448	1	1	100.00
CONT_ASSIGN	2451	1	1	100.00
CONT_ASSIGN	2466	1	1	100.00
CONT_ASSIGN	2482	1	1	100.00
CONT_ASSIGN	2498	1	1	100.00
ALWAYS	2504	30	30	100.00
CONT_ASSIGN	2536	1	1	100.00
ALWAYS	2540	1	1	100.00
CONT_ASSIGN	2573	1	1	100.00
CONT_ASSIGN	2575	1	1	100.00
CONT_ASSIGN	2577	1	1	100.00
CONT_ASSIGN	2578	1	1	100.00
CONT_ASSIGN	2580	1	1	100.00
CONT_ASSIGN	2582	1	1	100.00
CONT_ASSIGN	2583	1	1	100.00
CONT_ASSIGN	2585	1	1	100.00
CONT_ASSIGN	2587	1	1	100.00
CONT_ASSIGN	2588	1	1	100.00
CONT_ASSIGN	2590	1	1	100.00
CONT_ASSIGN	2592	1	1	100.00
CONT_ASSIGN	2593	1	1	100.00
CONT_ASSIGN	2595	1	1	100.00
CONT_ASSIGN	2596	1	1	100.00
CONT_ASSIGN	2598	1	1	100.00
CONT_ASSIGN	2600	1	1	100.00
CONT_ASSIGN	2602	1	1	100.00
CONT_ASSIGN	2604	1	1	100.00
CONT_ASSIGN	2606	1	1	100.00
CONT_ASSIGN	2608	1	1	100.00
CONT_ASSIGN	2610	1	1	100.00
CONT_ASSIGN	2612	1	1	100.00
CONT_ASSIGN	2614	1	1	100.00
CONT_ASSIGN	2616	1	1	100.00
CONT_ASSIGN	2618	1	1	100.00
CONT_ASSIGN	2619	1	1	100.00
CONT_ASSIGN	2621	1	1	100.00
CONT_ASSIGN	2622	1	1	100.00
CONT_ASSIGN	2624	1	1	100.00
CONT_ASSIGN	2625	1	1	100.00
CONT_ASSIGN	2627	1	1	100.00
CONT_ASSIGN	2628	1	1	100.00
CONT_ASSIGN	2630	1	1	100.00
CONT_ASSIGN	2631	1	1	100.00
CONT_ASSIGN	2633	1	1	100.00
CONT_ASSIGN	2634	1	1	100.00
CONT_ASSIGN	2636	1	1	100.00
CONT_ASSIGN	2637	1	1	100.00
CONT_ASSIGN	2639	1	1	100.00
CONT_ASSIGN	2640	1	1	100.00
CONT_ASSIGN	2642	1	1	100.00
CONT_ASSIGN	2643	1	1	100.00
CONT_ASSIGN	2645	1	1	100.00
CONT_ASSIGN	2646	1	1	100.00
CONT_ASSIGN	2648	1	1	100.00
CONT_ASSIGN	2649	1	1	100.00
CONT_ASSIGN	2651	1	1	100.00
CONT_ASSIGN	2652	1	1	100.00
CONT_ASSIGN	2654	1	1	100.00
CONT_ASSIGN	2656	1	1	100.00
CONT_ASSIGN	2658	1	1	100.00
CONT_ASSIGN	2660	1	1	100.00
CONT_ASSIGN	2662	1	1	100.00
CONT_ASSIGN	2664	1	1	100.00
CONT_ASSIGN	2666	1	1	100.00
CONT_ASSIGN	2668	1	1	100.00
CONT_ASSIGN	2670	1	1	100.00
CONT_ASSIGN	2672	1	1	100.00
CONT_ASSIGN	2674	1	1	100.00
CONT_ASSIGN	2675	1	1	100.00
CONT_ASSIGN	2677	1	1	100.00
CONT_ASSIGN	2679	1	1	100.00
CONT_ASSIGN	2681	1	1	100.00
CONT_ASSIGN	2683	1	1	100.00
CONT_ASSIGN	2685	1	1	100.00
CONT_ASSIGN	2687	1	1	100.00
CONT_ASSIGN	2689	1	1	100.00
CONT_ASSIGN	2691	1	1	100.00
CONT_ASSIGN	2693	1	1	100.00
CONT_ASSIGN	2695	1	1	100.00
CONT_ASSIGN	2697	1	1	100.00
CONT_ASSIGN	2698	1	1	100.00
CONT_ASSIGN	2700	1	1	100.00
CONT_ASSIGN	2701	1	1	100.00
CONT_ASSIGN	2703	1	1	100.00
CONT_ASSIGN	2704	1	1	100.00
CONT_ASSIGN	2706	1	1	100.00
CONT_ASSIGN	2707	1	1	100.00
CONT_ASSIGN	2709	1	1	100.00
CONT_ASSIGN	2710	1	1	100.00
CONT_ASSIGN	2711	1	1	100.00
CONT_ASSIGN	2713	1	1	100.00
CONT_ASSIGN	2715	1	1	100.00
CONT_ASSIGN	2717	1	1	100.00
CONT_ASSIGN	2718	1	1	100.00
CONT_ASSIGN	2719	1	1	100.00
CONT_ASSIGN	2721	1	1	100.00
CONT_ASSIGN	2723	1	1	100.00
CONT_ASSIGN	2725	1	1	100.00
CONT_ASSIGN	2726	1	1	100.00
CONT_ASSIGN	2727	1	1	100.00
CONT_ASSIGN	2729	1	1	100.00
CONT_ASSIGN	2731	1	1	100.00
CONT_ASSIGN	2733	1	1	100.00
CONT_ASSIGN	2734	1	1	100.00
CONT_ASSIGN	2735	1	1	100.00
CONT_ASSIGN	2737	1	1	100.00
CONT_ASSIGN	2739	1	1	100.00
CONT_ASSIGN	2741	1	1	100.00
ALWAYS	2745	30	30	100.00
ALWAYS	2779	85	85	100.00
CONT_ASSIGN	2962	0	0
CONT_ASSIGN	2970	1	1	100.00
CONT_ASSIGN	2971	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv' or '../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
77	1	1
89	1	1
90	1	1
118	1	1
119	1	1
420	1	1
435	1	1
451	1	1
457	1	1
472	1	1
488	1	1
823	1	1
855	1	1
887	1	1
919	1	1
951	1	1
983	1	1
1015	1	1
1047	1	1
1079	1	1
1111	1	1
1143	1	1
1175	1	1
2277	1	1
2280	1	1
2295	1	1
2311	1	1
2327	1	1
2334	1	1
2337	1	1
2352	1	1
2368	1	1
2384	1	1
2391	1	1
2394	1	1
2409	1	1
2425	1	1
2441	1	1
2448	1	1
2451	1	1
2466	1	1
2482	1	1
2498	1	1
2504	1	1
2505	1	1
2506	1	1
2507	1	1
2508	1	1
2509	1	1
2510	1	1
2511	1	1
2512	1	1
2513	1	1
2514	1	1
2515	1	1
2516	1	1
2517	1	1
2518	1	1
2519	1	1
2520	1	1
2521	1	1
2522	1	1
2523	1	1
2524	1	1
2525	1	1
2526	1	1
2527	1	1
2528	1	1
2529	1	1
2530	1	1
2531	1	1
2532	1	1
2533	1	1
2536	1	1
2540	1	1
2573	1	1
2575	1	1
2577	1	1
2578	1	1
2580	1	1
2582	1	1
2583	1	1
2585	1	1
2587	1	1
2588	1	1
2590	1	1
2592	1	1
2593	1	1
2595	1	1
2596	1	1
2598	1	1
2600	1	1
2602	1	1
2604	1	1
2606	1	1
2608	1	1
2610	1	1
2612	1	1
2614	1	1
2616	1	1
2618	1	1
2619	1	1
2621	1	1
2622	1	1
2624	1	1
2625	1	1
2627	1	1
2628	1	1
2630	1	1
2631	1	1
2633	1	1
2634	1	1
2636	1	1
2637	1	1
2639	1	1
2640	1	1
2642	1	1
2643	1	1
2645	1	1
2646	1	1
2648	1	1
2649	1	1
2651	1	1
2652	1	1
2654	1	1
2656	1	1
2658	1	1
2660	1	1
2662	1	1
2664	1	1
2666	1	1
2668	1	1
2670	1	1
2672	1	1
2674	1	1
2675	1	1
2677	1	1
2679	1	1
2681	1	1
2683	1	1
2685	1	1
2687	1	1
2689	1	1
2691	1	1
2693	1	1
2695	1	1
2697	1	1
2698	1	1
2700	1	1
2701	1	1
2703	1	1
2704	1	1
2706	1	1
2707	1	1
2709	1	1
2710	1	1
2711	1	1
2713	1	1
2715	1	1
2717	1	1
2718	1	1
2719	1	1
2721	1	1
2723	1	1
2725	1	1
2726	1	1
2727	1	1
2729	1	1
2731	1	1
2733	1	1
2734	1	1
2735	1	1
2737	1	1
2739	1	1
2741	1	1
2745	1	1
2746	1	1
2747	1	1
2748	1	1
2749	1	1
2750	1	1
2751	1	1
2752	1	1
2753	1	1
2754	1	1
2755	1	1
2756	1	1
2757	1	1
2758	1	1
2759	1	1
2760	1	1
2761	1	1
2762	1	1
2763	1	1
2764	1	1
2765	1	1
2766	1	1
2767	1	1
2768	1	1
2769	1	1
2770	1	1
2771	1	1
2772	1	1
2773	1	1
2774	1	1
2779	1	1
2780	1	1
2782	1	1
2783	1	1
2787	1	1
2788	1	1
2792	1	1
2793	1	1
2797	1	1
2798	1	1
2802	1	1
2806	1	1
2807	1	1
2808	1	1
2809	1	1
2810	1	1
2811	1	1
2812	1	1
2813	1	1
2814	1	1
2815	1	1
2816	1	1
2820	1	1
2824	1	1
2828	1	1
2832	1	1
2836	1	1
2840	1	1
2844	1	1
2848	1	1
2852	1	1
2856	1	1
2860	1	1
2864	1	1
2865	1	1
2866	1	1
2867	1	1
2868	1	1
2869	1	1
2870	1	1
2871	1	1
2872	1	1
2873	1	1
2874	1	1
2878	1	1
2879	1	1
2880	1	1
2881	1	1
2882	1	1
2883	1	1
2884	1	1
2885	1	1
2886	1	1
2887	1	1
2888	1	1
2892	1	1
2893	1	1
2894	1	1
2895	1	1
2896	1	1
2897	1	1
2898	1	1
2899	1	1
2900	1	1
2901	1	1
2902	1	1
2903	1	1
2907	1	1
2908	1	1
2912	1	1
2916	1	1
2920	1	1
2924	1	1
2928	1	1
2929	1	1
2930	1	1
2934	1	1
2935	1	1
2936	1	1
2940	1	1
2941	1	1
2942	1	1
2946	1	1
2947	1	1
2948	1	1
2962		unreachable
2970	1	1
2971	1	1

---

Cond Coverage for Module : sensor_ctrl_reg_top

	Total	Covered	Percent
Conditions	369	257	69.65
Logical	369	257	69.65
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T64,T52,T278

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T375,T376,T377
1	0	Not Covered

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T375,T376,T377
0	1	0	Not Covered
1	0	0	Covered	T375,T376,T377

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       823
 EXPRESSION (alert_en_0_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T64,T52,T278

 LINE       855
 EXPRESSION (alert_en_1_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T64,T52,T278

 LINE       887
 EXPRESSION (alert_en_2_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T64,T52,T278

 LINE       919
 EXPRESSION (alert_en_3_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T64,T52,T278

 LINE       951
 EXPRESSION (alert_en_4_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T64,T52,T278

 LINE       983
 EXPRESSION (alert_en_5_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T64,T52,T278

 LINE       1015
 EXPRESSION (alert_en_6_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T64,T52,T278

 LINE       1047
 EXPRESSION (alert_en_7_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T64,T52,T278

 LINE       1079
 EXPRESSION (alert_en_8_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T64,T52,T278

 LINE       1111
 EXPRESSION (alert_en_9_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T64,T52,T278

 LINE       1143
 EXPRESSION (alert_en_10_we & cfg_regwen_qs)
             -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T64,T52,T278

 LINE       1175
 EXPRESSION (fatal_alert_en_we & cfg_regwen_qs)
             --------1--------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T52,T278,T383

 LINE       2280
 EXPRESSION (manual_pad_attr_0_we & manual_pad_attr_regwen_0_qs)
             ----------1---------   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T37,T38,T39

 LINE       2337
 EXPRESSION (manual_pad_attr_1_we & manual_pad_attr_regwen_1_qs)
             ----------1---------   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T37,T38,T39

 LINE       2394
 EXPRESSION (manual_pad_attr_2_we & manual_pad_attr_regwen_2_qs)
             ----------1---------   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T37,T38,T39

 LINE       2451
 EXPRESSION (manual_pad_attr_3_we & manual_pad_attr_regwen_3_qs)
             ----------1---------   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T37,T38,T39

 LINE       2505
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_INTR_STATE_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2506
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_INTR_ENABLE_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2507
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_INTR_TEST_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2508
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_TEST_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2509
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_CFG_REGWEN_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2510
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_TRIG_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2511
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_0_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2512
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_1_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2513
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_2_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2514
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_3_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2515
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_4_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2516
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_5_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2517
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_6_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2518
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_7_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2519
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_8_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2520
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_9_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2521
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_10_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2522
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_FATAL_ALERT_EN_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2523
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_RECOV_ALERT_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2524
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_FATAL_ALERT_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2525
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_STATUS_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2526
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_REGWEN_0_OFFSET)
            ---------------------------------------1--------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2527
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_REGWEN_1_OFFSET)
            ---------------------------------------1--------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2528
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_REGWEN_2_OFFSET)
            ---------------------------------------1--------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2529
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_REGWEN_3_OFFSET)
            ---------------------------------------1--------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2530
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_0_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2531
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_1_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2532
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_2_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2533
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_3_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2536
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       2536
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T64,T52,T278
1	0	Covered	T4,T5,T6

 LINE       2540
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[18] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[19] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T64,T52,T278
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b0011 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b0011 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T4,T5,T6
29 (addr_hit[28] & ((|(4'...	Not Covered
28 (addr_hit[27] & ((|(4'...	Not Covered
27 (addr_hit[26] & ((|(4'...	Not Covered
26 (addr_hit[25] & ((|(4'...	Not Covered
25 (addr_hit[24] & ((|(4'...	Not Covered
24 (addr_hit[23] & ((|(4'...	Not Covered
23 (addr_hit[22] & ((|(4'...	Not Covered
22 (addr_hit[21] & ((|(4'...	Not Covered
21 (addr_hit[20] & ((|(4'...	Not Covered
20 (addr_hit[19] & ((|(4'...	Covered	T37,T38,T39
19 (addr_hit[18] & ((|(4'...	Covered	T37,T38,T39
18 (addr_hit[17] & ((|(4'...	Covered	T37,T38,T39
17 (addr_hit[16] & ((|(4'...	Not Covered
16 (addr_hit[15] & ((|(4'...	Not Covered
15 (addr_hit[14] & ((|(4'...	Not Covered
14 (addr_hit[13] & ((|(4'...	Not Covered
13 (addr_hit[12] & ((|(4'...	Not Covered
12 (addr_hit[11] & ((|(4'...	Not Covered
11 (addr_hit[10] & ((|(4'...	Not Covered
10 (addr_hit[9] & ((|(4'b...	Not Covered
9 (addr_hit[8] & ((|(4'b...	Not Covered
8 (addr_hit[7] & ((|(4'b...	Not Covered
7 (addr_hit[6] & ((|(4'b...	Not Covered
6 (addr_hit[5] & ((|(4'b...	Covered	T37,T38,T39
5 (addr_hit[4] & ((|(4'b...	Not Covered
4 (addr_hit[3] & ((|(4'b...	Not Covered
3 (addr_hit[2] & ((|(4'b...	Not Covered
2 (addr_hit[1] & ((|(4'b...	Not Covered
1 (addr_hit[0] & ((|(4'b...	Covered	T4,T5,T6

 LINE       2540
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       2540
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T37,T38,T39

 LINE       2540
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T37,T38,T39

 LINE       2540
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T37,T38,T39

 LINE       2540
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T37,T38,T39

 LINE       2540
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       2540
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       2573
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T64,T52,T278
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T149,T161,T151

 LINE       2578
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T64,T52,T278
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T149,T161,T151

 LINE       2583
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T64,T52,T278
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T161,T162,T163

 LINE       2588
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T64,T52,T278
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T61,T62,T63

 LINE       2593
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T64,T52,T278
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       2596
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T64,T52,T278
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T64,T136,T137

 LINE       2619
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T64,T52,T278
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T64,T52,T278

 LINE       2622
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T64,T52,T278
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T64,T52,T278

 LINE       2625
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T64,T52,T278
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T64,T52,T278

 LINE       2628
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T64,T52,T278
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T64,T52,T278

 LINE       2631
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T64,T52,T278
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T64,T52,T278

 LINE       2634
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T64,T52,T278
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T64,T52,T278

 LINE       2637
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T64,T52,T278
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T64,T52,T278

 LINE       2640
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T64,T52,T278
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T64,T52,T278

 LINE       2643
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T64,T52,T278
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T64,T52,T278

 LINE       2646
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T64,T52,T278
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T64,T52,T278

 LINE       2649
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T64,T52,T278
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T64,T52,T278

 LINE       2652
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T64,T52,T278
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T52,T278,T383

 LINE       2675
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T64,T52,T278
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T64,T136,T137

 LINE       2698
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T64,T52,T278
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       2701
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T64,T52,T278
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       2704
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T64,T52,T278
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       2707
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T64,T52,T278
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       2710
 EXPRESSION (addr_hit[25] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       2711
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T64,T52,T278
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T37,T38,T39

 LINE       2718
 EXPRESSION (addr_hit[26] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       2719
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T64,T52,T278
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T37,T38,T39

 LINE       2726
 EXPRESSION (addr_hit[27] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       2727
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T64,T52,T278
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T37,T38,T39

 LINE       2734
 EXPRESSION (addr_hit[28] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       2735
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T64,T52,T278
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T37,T38,T39

---

Branch Coverage for Module : sensor_ctrl_reg_top

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	2536	2	2	100.00
IF	68	3	3	100.00
CASE	2780	30	30	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv' or '../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	2536	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T375,T376,T377
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	2780	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T4,T5,T6
addr_hit[1]	Covered	T4,T5,T6
addr_hit[2]	Covered	T4,T5,T6
addr_hit[3]	Covered	T4,T5,T6
addr_hit[4]	Covered	T4,T5,T6
addr_hit[5]	Covered	T4,T5,T6
addr_hit[6]	Covered	T4,T5,T6
addr_hit[7]	Covered	T4,T5,T6
addr_hit[8]	Covered	T4,T5,T6
addr_hit[9]	Covered	T4,T5,T6
addr_hit[10]	Covered	T4,T5,T6
addr_hit[11]	Covered	T4,T5,T6
addr_hit[12]	Covered	T4,T5,T6
addr_hit[13]	Covered	T4,T5,T6
addr_hit[14]	Covered	T4,T5,T6
addr_hit[15]	Covered	T4,T5,T6
addr_hit[16]	Covered	T4,T5,T6
addr_hit[17]	Covered	T4,T5,T6
addr_hit[18]	Covered	T4,T5,T6
addr_hit[19]	Covered	T4,T5,T6
addr_hit[20]	Covered	T4,T5,T6
addr_hit[21]	Covered	T4,T5,T6
addr_hit[22]	Covered	T4,T5,T6
addr_hit[23]	Covered	T4,T5,T6
addr_hit[24]	Covered	T4,T5,T6
addr_hit[25]	Covered	T4,T5,T6
addr_hit[26]	Covered	T4,T5,T6
addr_hit[27]	Covered	T4,T5,T6
addr_hit[28]	Covered	T4,T5,T6
default	Covered	T4,T5,T6

---

Assert Coverage for Module : sensor_ctrl_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	129376139	5437	0	0
reAfterRv	129376139	5437	0	0
rePulse	129376139	3947	0	0
wePulse	129376139	1490	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	129376139	5437	0	0
T4	211812	1	0	0
T5	63618	2	0	0
T6	64825	1	0	0
T15	84026	1	0	0
T16	286262	0	0	0
T41	65114	2	0	0
T64	38052	64	0	0
T65	35738	1	0	0
T96	23532	1	0	0
T97	51865	1	0	0
T201	0	1	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	129376139	5437	0	0
T4	211812	1	0	0
T5	63618	2	0	0
T6	64825	1	0	0
T15	84026	1	0	0
T16	286262	0	0	0
T41	65114	2	0	0
T64	38052	64	0	0
T65	35738	1	0	0
T96	23532	1	0	0
T97	51865	1	0	0
T201	0	1	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	129376139	3947	0	0
T4	211812	1	0	0
T5	63618	2	0	0
T6	64825	1	0	0
T15	84026	1	0	0
T16	286262	0	0	0
T41	65114	2	0	0
T64	38052	36	0	0
T65	35738	1	0	0
T96	23532	1	0	0
T97	51865	1	0	0
T201	0	1	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	129376139	1490	0	0
T3	0	80	0	0
T41	65114	0	0	0
T42	51021	0	0	0
T43	25483	0	0	0
T52	0	12	0	0
T57	65648	0	0	0
T64	38052	28	0	0
T65	35738	0	0	0
T97	51865	0	0	0
T136	0	55	0	0
T137	0	39	0	0
T149	0	12	0	0
T201	18821	0	0	0
T258	24741	0	0	0
T260	24357	0	0	0
T278	0	12	0	0
T279	0	12	0	0
T383	0	12	0	0
T384	0	12	0	0