Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : spi_device
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.17 79.17

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_spi_device 88.14 88.14



Module Instance : tb.dut.top_earlgrey.u_spi_device

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.14 88.14


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.14 88.14


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.56 90.68 87.00 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : spi_device
TotalCoveredPercent
Totals 65 42 64.62
Total Bits 432 342 79.17
Total Bits 0->1 216 171 79.17
Total Bits 1->0 216 171 79.17

Ports 65 42 64.62
Port Bits 432 342 79.17
Port Bits 0->1 216 171 79.17
Port Bits 1->0 216 171 79.17

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T20,T43,T44 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T51,T27,T52 Yes T51,T27,T52 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T51,T27,T52 Yes T51,T27,T52 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[12:2] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[15:13] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T61,*T62,*T63 Yes T61,T62,T63 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T40,T41,T42 Yes T40,T41,T42 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[0] Yes Yes *T61,*T1,*T64 Yes T61,T1,T64 INPUT
tl_i.a_opcode[1] No No No INPUT
tl_i.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_valid Yes Yes T51,T27,T52 Yes T51,T27,T52 INPUT
tl_o.a_ready Yes Yes T51,T27,T52 Yes T51,T27,T52 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T51,T27,T52 Yes T51,T27,T52 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T51,T27,T52 Yes T51,T27,T52 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes T51,T52,T28 Yes T51,T27,T52 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T51,T27,T52 Yes T51,T27,T52 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[0] No No No OUTPUT
tl_o.d_source[1] Yes Yes *T51,*T27,*T52 Yes T51,T27,T52 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T51,T52,T28 Yes T51,T27,T52 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T51,*T27,*T52 Yes T51,T27,T52 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T51,T27,T52 Yes T51,T27,T52 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T107,T108,T109 Yes T107,T108,T109 INPUT
alert_rx_i[0].ping_n Yes Yes T108,T109,T110 Yes T108,T110,T111 INPUT
alert_rx_i[0].ping_p Yes Yes T108,T110,T111 Yes T108,T109,T110 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T107,T108,T109 Yes T107,T108,T109 OUTPUT
cio_sck_i Yes Yes T51,T27,T52 Yes T51,T27,T52 INPUT
cio_csb_i Yes Yes T27,T28,T112 Yes T27,T28,T112 INPUT
cio_sd_o[3:0] Yes Yes T27,T28,T29 Yes T27,T28,T29 OUTPUT
cio_sd_en_o[3:0] Yes Yes T27,T28,T29 Yes T27,T28,T29 OUTPUT
cio_sd_i[3:0] Yes Yes T51,T27,T52 Yes T51,T27,T52 INPUT
cio_tpm_csb_i Yes Yes T51,T52,T53 Yes T51,T52,T53 INPUT
passthrough_o.s_en[0] Yes Yes *T27,*T28,*T29 Yes T27,T28,T29 OUTPUT
passthrough_o.s_en[3:1] No No No OUTPUT
passthrough_o.s[3:0] Yes Yes T51,T27,T52 Yes T51,T27,T52 OUTPUT
passthrough_o.csb_en No No No OUTPUT
passthrough_o.csb Yes Yes T27,T28,T112 Yes T27,T28,T112 OUTPUT
passthrough_o.sck_en No No No OUTPUT
passthrough_o.sck Yes Yes T51,T27,T52 Yes T51,T27,T52 OUTPUT
passthrough_o.passthrough_en Yes Yes T28,T29,T113 Yes T27,T28,T29 OUTPUT
passthrough_i.s[3:0] Yes Yes T27,T28,T29 Yes T27,T28,T29 INPUT
intr_upload_cmdfifo_not_empty_o Yes Yes T28,T29,T114 Yes T28,T29,T114 OUTPUT
intr_upload_payload_not_empty_o Yes Yes T114,T115,T116 Yes T114,T115,T116 OUTPUT
intr_upload_payload_overflow_o Yes Yes T114,T115,T116 Yes T114,T115,T116 OUTPUT
intr_readbuf_watermark_o Yes Yes T114,T115,T116 Yes T114,T115,T116 OUTPUT
intr_readbuf_flip_o Yes Yes T114,T115,T116 Yes T114,T115,T116 OUTPUT
intr_tpm_header_not_empty_o Yes Yes T51,T52,T53 Yes T51,T52,T53 OUTPUT
intr_tpm_rdfifo_cmd_end_o Yes Yes T114,T115,T116 Yes T114,T115,T116 OUTPUT
intr_tpm_rdfifo_drop_o Yes Yes T114,T115,T116 Yes T114,T115,T116 OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0] No No No INPUT
ram_cfg_i.b_ram_lcfg.cfg_en No No No INPUT
ram_cfg_i.b_ram_lcfg.test No No No INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0] No No No INPUT
ram_cfg_i.a_ram_lcfg.cfg_en No No No INPUT
ram_cfg_i.a_ram_lcfg.test No No No INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0] No No No INPUT
ram_cfg_i.b_ram_fcfg.cfg_en No No No INPUT
ram_cfg_i.b_ram_fcfg.test No No No INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0] No No No INPUT
ram_cfg_i.a_ram_fcfg.cfg_en No No No INPUT
ram_cfg_i.a_ram_fcfg.test No No No INPUT
sck_monitor_o Yes Yes T51,T27,T52 Yes T51,T27,T52 OUTPUT
mbist_en_i Unreachable Unreachable Unreachable INPUT
scan_clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_device
TotalCoveredPercent
Totals 55 42 76.36
Total Bits 388 342 88.14
Total Bits 0->1 194 171 88.14
Total Bits 1->0 194 171 88.14

Ports 55 42 76.36
Port Bits 388 342 88.14
Port Bits 0->1 194 171 88.14
Port Bits 1->0 194 171 88.14

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T20,T43,T44 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T51,T27,T52 Yes T51,T27,T52 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T51,T27,T52 Yes T51,T27,T52 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[12:2] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[15:13] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T61,*T62,*T63 Yes T61,T62,T63 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T40,T41,T42 Yes T40,T41,T42 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[0] Yes Yes *T61,*T1,*T64 Yes T61,T1,T64 INPUT
tl_i.a_opcode[1] No No No INPUT
tl_i.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_valid Yes Yes T51,T27,T52 Yes T51,T27,T52 INPUT
tl_o.a_ready Yes Yes T51,T27,T52 Yes T51,T27,T52 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T51,T27,T52 Yes T51,T27,T52 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T51,T27,T52 Yes T51,T27,T52 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes T51,T52,T28 Yes T51,T27,T52 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T51,T27,T52 Yes T51,T27,T52 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[0] No No No OUTPUT
tl_o.d_source[1] Yes Yes *T51,*T27,*T52 Yes T51,T27,T52 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T51,T52,T28 Yes T51,T27,T52 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T51,*T27,*T52 Yes T51,T27,T52 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T51,T27,T52 Yes T51,T27,T52 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T107,T108,T109 Yes T107,T108,T109 INPUT
alert_rx_i[0].ping_n Yes Yes T108,T109,T110 Yes T108,T110,T111 INPUT
alert_rx_i[0].ping_p Yes Yes T108,T110,T111 Yes T108,T109,T110 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T107,T108,T109 Yes T107,T108,T109 OUTPUT
cio_sck_i Yes Yes T51,T27,T52 Yes T51,T27,T52 INPUT
cio_csb_i Yes Yes T27,T28,T112 Yes T27,T28,T112 INPUT
cio_sd_o[3:0] Yes Yes T27,T28,T29 Yes T27,T28,T29 OUTPUT
cio_sd_en_o[3:0] Yes Yes T27,T28,T29 Yes T27,T28,T29 OUTPUT
cio_sd_i[3:0] Yes Yes T51,T27,T52 Yes T51,T27,T52 INPUT
cio_tpm_csb_i Yes Yes T51,T52,T53 Yes T51,T52,T53 INPUT
passthrough_o.s_en[0] Yes Yes *T27,*T28,*T29 Yes T27,T28,T29 OUTPUT
passthrough_o.s_en[3:1] No No No OUTPUT
passthrough_o.s[3:0] Yes Yes T51,T27,T52 Yes T51,T27,T52 OUTPUT
passthrough_o.csb_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off.
passthrough_o.csb Yes Yes T27,T28,T112 Yes T27,T28,T112 OUTPUT
passthrough_o.sck_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off.
passthrough_o.sck Yes Yes T51,T27,T52 Yes T51,T27,T52 OUTPUT
passthrough_o.passthrough_en Yes Yes T28,T29,T113 Yes T27,T28,T29 OUTPUT
passthrough_i.s[3:0] Yes Yes T27,T28,T29 Yes T27,T28,T29 INPUT
intr_upload_cmdfifo_not_empty_o Yes Yes T28,T29,T114 Yes T28,T29,T114 OUTPUT
intr_upload_payload_not_empty_o Yes Yes T114,T115,T116 Yes T114,T115,T116 OUTPUT
intr_upload_payload_overflow_o Yes Yes T114,T115,T116 Yes T114,T115,T116 OUTPUT
intr_readbuf_watermark_o Yes Yes T114,T115,T116 Yes T114,T115,T116 OUTPUT
intr_readbuf_flip_o Yes Yes T114,T115,T116 Yes T114,T115,T116 OUTPUT
intr_tpm_header_not_empty_o Yes Yes T51,T52,T53 Yes T51,T52,T53 OUTPUT
intr_tpm_rdfifo_cmd_end_o Yes Yes T114,T115,T116 Yes T114,T115,T116 OUTPUT
intr_tpm_rdfifo_drop_o Yes Yes T114,T115,T116 Yes T114,T115,T116 OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_lcfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_lcfg.test No No No INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_lcfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_lcfg.test No No No INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_fcfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_fcfg.test No No No INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_fcfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_fcfg.test No No No INPUT
sck_monitor_o Yes Yes T51,T27,T52 Yes T51,T27,T52 OUTPUT
mbist_en_i Unreachable Unreachable Unreachable INPUT
scan_clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%