| | | | | | | | |
| clk_ctrl_and_main_pd_sva_if |
100.00 |
|
|
100.00 |
|
|
|
| u_adc_ctrl_aon |
89.81 |
|
|
89.81 |
|
|
|
| u_aes |
96.62 |
|
|
96.62 |
|
|
|
| u_alert_handler |
97.29 |
|
|
97.29 |
|
|
|
| u_aon_timer_aon |
90.13 |
|
|
90.13 |
|
|
|
| u_clkmgr_aon |
94.93 |
|
|
94.93 |
|
|
|
| u_csrng |
96.93 |
|
|
96.93 |
|
|
|
| u_dft_tap_breakout |
100.00 |
100.00 |
|
100.00 |
|
|
|
| u_edn0 |
95.61 |
|
|
95.61 |
|
|
|
u_edn1 |
92.86 |
|
|
92.86 |
|
|
|
| u_entropy_src |
89.07 |
|
|
89.07 |
|
|
|
| u_flash_ctrl |
95.60 |
|
|
95.60 |
|
|
|
| u_gpio |
94.44 |
|
|
94.44 |
|
|
|
| u_hmac |
84.81 |
|
|
84.81 |
|
|
|
| u_i2c0 |
84.48 |
|
|
84.48 |
|
|
|
| u_i2c1 |
84.57 |
|
|
84.57 |
|
|
|
| u_i2c2 |
84.57 |
|
|
84.57 |
|
|
|
| u_keymgr |
89.29 |
|
|
89.29 |
|
|
|
| u_kmac |
99.29 |
|
|
99.29 |
|
|
|
| u_lc_ctrl |
91.43 |
|
|
91.43 |
|
|
|
| u_otbn |
98.03 |
|
|
98.03 |
|
|
|
| u_otp_ctrl |
83.78 |
|
|
83.78 |
|
|
|
| u_pattgen |
90.00 |
|
|
90.00 |
|
|
|
| u_pinmux_aon |
93.27 |
92.61 |
80.86 |
97.99 |
|
95.59 |
99.30 |
| gen_alert_tx[0].u_prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
| gen_wkup_detect[0].u_pinmux_wkup |
69.87 |
77.78 |
68.18 |
|
|
63.64 |
|
| u_prim_filter |
93.27 |
100.00 |
88.89 |
|
|
90.91 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_wkup_detect[1].u_pinmux_wkup |
75.34 |
80.56 |
77.27 |
|
|
68.18 |
|
| u_prim_filter |
93.27 |
100.00 |
88.89 |
|
|
90.91 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_wkup_detect[2].u_pinmux_wkup |
69.87 |
77.78 |
63.64 |
|
|
68.18 |
|
| u_prim_filter |
93.27 |
100.00 |
88.89 |
|
|
90.91 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_wkup_detect[3].u_pinmux_wkup |
45.45 |
50.00 |
31.82 |
|
|
54.55 |
|
| u_prim_filter |
67.58 |
76.47 |
44.44 |
|
|
81.82 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_wkup_detect[4].u_pinmux_wkup |
60.10 |
66.67 |
45.45 |
|
|
68.18 |
|
| u_prim_filter |
76.27 |
82.35 |
55.56 |
|
|
90.91 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_wkup_detect[5].u_pinmux_wkup |
71.38 |
77.78 |
68.18 |
|
|
68.18 |
|
| u_prim_filter |
93.27 |
100.00 |
88.89 |
|
|
90.91 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_wkup_detect[6].u_pinmux_wkup |
77.78 |
83.33 |
77.27 |
|
|
72.73 |
|
| u_prim_filter |
93.27 |
100.00 |
88.89 |
|
|
90.91 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_wkup_detect[7].u_pinmux_wkup |
79.29 |
83.33 |
77.27 |
|
|
77.27 |
|
| u_prim_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_pinmux_strap_sampling |
98.82 |
99.62 |
95.65 |
|
|
100.00 |
100.00 |
| subtree... |
|
|
|
|
|
|
|
| u_reg |
92.98 |
92.22 |
80.46 |
|
|
99.24 |
100.00 |
| subtree... |
|
|
|
|
|
|
|
| u_usbdev_aon_wake |
98.43 |
100.00 |
95.59 |
|
|
98.11 |
100.00 |
| filter_activity |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| filter_bus_reset |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| filter_sense |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_pullup_en_cdc |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_pwm_aon |
90.20 |
|
|
90.20 |
|
|
|
| u_pwrmgr_aon |
93.07 |
|
|
93.07 |
|
|
|
| u_rom_ctrl |
97.26 |
|
|
97.26 |
|
|
|
| u_rstmgr_aon |
92.31 |
|
|
92.31 |
|
|
|
| u_rv_core_ibex |
91.52 |
96.51 |
81.77 |
90.41 |
|
96.77 |
92.14 |
| subtree... |
|
|
|
|
|
|
|
| u_rv_dm |
85.71 |
|
|
85.71 |
|
|
|
| u_rv_plic |
90.59 |
92.09 |
81.41 |
90.54 |
|
92.50 |
96.43 |
| gen_alert_tx[0].u_prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
| gen_target[0].u_target |
91.61 |
89.34 |
77.09 |
|
|
100.00 |
100.00 |
| u_prim_max_tree |
91.58 |
89.27 |
77.06 |
|
|
100.00 |
100.00 |
| u_gateway |
75.00 |
100.00 |
25.00 |
|
|
100.00 |
|
| u_prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_reg |
91.49 |
91.95 |
84.17 |
|
|
89.84 |
100.00 |
| subtree... |
|
|
|
|
|
|
|
| u_rv_timer |
89.04 |
|
|
89.04 |
|
|
|
| u_sensor_ctrl_aon |
89.69 |
91.56 |
83.91 |
79.23 |
|
93.75 |
100.00 |
| gen_alert_sync_assign[0].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[10].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[1].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[2].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[3].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[4].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[5].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[6].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[7].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[8].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[9].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| u_alert_n_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_alert_p_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_init_chg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| g_sync.u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_init_intr |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| u_io_intr |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| u_io_status_chg |
100.00 |
100.00 |
|
|
|
100.00 |
|
| g_sync.u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_prim_sec_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| u_reg |
91.72 |
90.70 |
82.88 |
|
|
93.29 |
100.00 |
| subtree... |
|
|
|
|
|
|
|
| u_wake_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_spi_device |
88.14 |
|
|
88.14 |
|
|
|
| u_spi_host0 |
83.52 |
|
|
83.52 |
|
|
|
| u_spi_host1 |
81.48 |
|
|
81.48 |
|
|
|
| u_sram_ctrl_main |
89.17 |
|
|
89.17 |
|
|
|
| u_sram_ctrl_ret_aon |
94.19 |
|
|
94.19 |
|
|
|
| u_sysrst_ctrl_aon |
90.42 |
|
|
90.42 |
|
|
|
| u_uart0 |
90.13 |
|
|
90.13 |
|
|
|
| u_uart1 |
89.54 |
|
|
89.54 |
|
|
|
| u_uart2 |
89.54 |
|
|
89.54 |
|
|
|
| u_uart3 |
89.61 |
|
|
89.61 |
|
|
|
| u_usbdev |
82.35 |
|
|
82.35 |
|
|
|
| u_xbar_main |
83.98 |
|
|
83.98 |
|
|
|
| u_xbar_peri |
89.82 |
|
|
89.82 |
|
|
|