Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.98			83.98

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	83.98			83.98

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.98			83.98

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.98			83.98

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	90.68		87.00			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	309	56.18
Total Bits	6824	5731	83.98
Total Bits 0->1	3412	2866	84.00
Total Bits 1->0	3412	2865	83.97

Ports	550	309	56.18
Port Bits	6824	5731	83.98
Port Bits 0->1	3412	2866	84.00
Port Bits 1->0	3412	2865	83.97

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_fixed_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_usb_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host0_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host1_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_main_ni	Yes	Yes	T20,T43,T44	Yes	T4,T5,T6	INPUT
rst_fixed_ni	Yes	Yes	T20,T43,T44	Yes	T4,T5,T6	INPUT
rst_usb_ni	Yes	Yes	T20,T43,T44	Yes	T4,T5,T6	INPUT
rst_spi_host0_ni	Yes	Yes	T20,T43,T44	Yes	T4,T5,T6	INPUT
rst_spi_host1_ni	Yes	Yes	T20,T43,T44	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.d_ready	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_source[5:3]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T20,T181,T198	Yes	T20,T181,T198	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[5:0]	Yes	Yes	*T20,*T181,*T199	Yes	T20,T181,T199	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_source[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:3]	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[0]	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T61,T1,T64	Yes	T61,T1,T64	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T200,T201	Yes	T200,T201	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_opcode[1]	No	No		No		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T20,T122,T181	Yes	T20,T122,T181	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	No	No		No		OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T20,T43,T83	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T61,T62,T124	Yes	T61,T62,T124	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T20,T43,T83	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.instr_type[0]	Yes	Yes	*T20,*T43,*T83	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_rv_dm__sba_i.a_user.instr_type[3]	Yes	Yes	T20,T43,T83	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T61,T62,T124	Yes	T61,T62,T124	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T20,T43,T83	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	No	No		No		INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[0]	No	No		No		INPUT
tl_rv_dm__sba_i.a_size[1]	Yes	Yes	T20,T43,T83	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[1:0]	No	No		No		INPUT
tl_rv_dm__sba_i.a_opcode[2]	Yes	Yes	T20,T43,T83	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T61,T62,T124	Yes	T61,T62,T124	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T20,T43,T44	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_o.d_error	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T61,T62,T124	Yes	T61,T62,T124	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[1:0]	Yes	Yes	T61,T124,T100	Yes	T61,T124,T100	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[2]	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[5:3]	Yes	Yes	T61,*T62,T124	Yes	T61,T62,T124	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T61,T62,T124	Yes	T61,T62,T124	OUTPUT
tl_rv_dm__sba_o.d_sink	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[0]	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_size[1]	Yes	Yes	T61,T62,T124	Yes	T61,T62,T124	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T61,*T62,*T124	Yes	T61,T62,T124	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T61,T62,T124	Yes	T61,T62,T124	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T20,T43,T44	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[5:0]	Yes	Yes	T1	Yes	T1	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[0]	Yes	Yes	*T1	Yes	T1	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:2]	Yes	Yes	T1	Yes	T1	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[0]	Yes	Yes	*T1	Yes	T1	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3]	Yes	Yes	T1	Yes	T1	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[2:0]	Yes	Yes	T1	Yes	T1	OUTPUT
tl_rv_dm__regs_o.a_data[3]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_data[17:4]	Yes	Yes	T1	Yes	T1	OUTPUT
tl_rv_dm__regs_o.a_data[18]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_data[31:19]	Yes	Yes	T1	Yes	T1	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T1	Yes	T1	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[0]	Yes	Yes	*T1	Yes	T1	OUTPUT
tl_rv_dm__regs_o.a_source[5:1]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[0]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_size[1]	Yes	Yes	T1	Yes	T1	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_opcode[2]	Yes	Yes	T1	Yes	T1	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T1	Yes	T1	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T1	Yes	T1	INPUT
tl_rv_dm__regs_i.d_error	No	No		No		INPUT
tl_rv_dm__regs_i.d_user.data_intg[0]	Yes	Yes	*T1	Yes	T1	INPUT
tl_rv_dm__regs_i.d_user.data_intg[3:1]	No	No		No		INPUT
tl_rv_dm__regs_i.d_user.data_intg[4]	Yes	Yes	*T1	Yes	T1	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:5]	No	No		No		INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[1:0]	Yes	Yes	T1	Yes	T1	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[5:4]	Yes	Yes	T1	Yes	T1	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T1	Yes	T1	INPUT
tl_rv_dm__regs_i.d_sink	No	No		No		INPUT
tl_rv_dm__regs_i.d_source[0]	Yes	Yes	*T1	Yes	T1	INPUT
tl_rv_dm__regs_i.d_source[5:1]	No	No		No		INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[0]	No	No		No		INPUT
tl_rv_dm__regs_i.d_size[1]	Yes	Yes	T1	Yes	T1	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T1	Yes	T1	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T1	Yes	T1	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T20,T43,T44	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T62,T63,T1	Yes	T62,T63,T1	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T62,T63,T1	Yes	T62,T63,T1	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T62,T63,T1	Yes	T62,T63,T1	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T62,T63,T1	Yes	T62,T63,T1	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T62,T63,T1	Yes	T62,T63,T1	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[4:0]	Yes	Yes	*T62,*T63,*T202	Yes	T62,T63,T202	OUTPUT
tl_rv_dm__mem_o.a_source[5]	No	No		No		OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[0]	No	No		No		OUTPUT
tl_rv_dm__mem_o.a_size[1]	Yes	Yes	T62,T63,T1	Yes	T62,T63,T1	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rv_dm__mem_o.a_opcode[2]	Yes	Yes	T62,T63,T1	Yes	T62,T63,T1	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T62,T63,T1	Yes	T62,T63,T1	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T20,T43,T83	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T62,T63,T202	Yes	T62,T63,T202	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[2:0]	Yes	Yes	*T62,*T63,*T1	Yes	T62,T63,T1	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[5:4]	Yes	Yes	*T62,*T1,*T203	Yes	T62,T63,T1	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T20,T43,T83	INPUT
tl_rv_dm__mem_i.d_sink	No	No		No		INPUT
tl_rv_dm__mem_i.d_source[4:0]	Yes	Yes	*T62,*T63,*T202	Yes	T62,T63,T202	INPUT
tl_rv_dm__mem_i.d_source[5]	No	No		No		INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[0]	No	No		No		INPUT
tl_rv_dm__mem_i.d_size[1]	Yes	Yes	T62,T1,T203	Yes	T62,T63,T1	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T20,T43,T83	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T62,T63,T1	Yes	T62,T63,T1	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T125,T54,T55	Yes	T125,T54,T55	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T54,T55,T61	Yes	T54,T55,T61	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[4:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_source[5]	No	No		No		OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[0]	No	No		No		OUTPUT
tl_rom_ctrl__rom_o.a_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_error	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[4]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:5]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_sink	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_source[4:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_source[5]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[0]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T20,T43,T44	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T1,T118,T119	Yes	T1,T118,T119	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T204,T205	Yes	T1,T204,T205	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[0]	Yes	Yes	*T1,*T204,*T205	Yes	T1,T204,T205	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3]	Yes	Yes	T1,T204,T205	Yes	T1,T204,T205	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T1,T118,T119	Yes	T1,T118,T119	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T1,T204,T205	Yes	T1,T204,T205	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[1:0]	Yes	Yes	*T1,*T204,*T205	Yes	T1,T204,T205	OUTPUT
tl_rom_ctrl__regs_o.a_source[5:2]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[0]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_size[1]	Yes	Yes	T1,T204,T205	Yes	T1,T204,T205	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2]	Yes	Yes	T1,T204,T205	Yes	T1,T204,T205	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T1,T204,T205	Yes	T1,T204,T205	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T1,T204,T205	Yes	T1,T204,T205	INPUT
tl_rom_ctrl__regs_i.d_error	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,*T118,*T119	Yes	T1,T118,T119	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[5:4]	Yes	Yes	T1,T204,T206	Yes	T1,T204,T205	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T1,T204,T205	Yes	T1,T204,T205	INPUT
tl_rom_ctrl__regs_i.d_sink	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_source[1:0]	Yes	Yes	*T1,*T204,*T205	Yes	T1,T204,T205	INPUT
tl_rom_ctrl__regs_i.d_source[5:2]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[0]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_size[1]	Yes	Yes	T1,T204,T206	Yes	T1,T204,T205	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T1,*T204,*T206	Yes	T1,T204,T205	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T1,T204,T205	Yes	T1,T204,T205	INPUT
tl_peri_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_peri_o.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T61,*T62,*T63	Yes	T61,T62,T63	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[0]	Yes	Yes	*T61,*T1,*T64	Yes	T61,T1,T64	OUTPUT
tl_peri_o.a_opcode[1]	No	No		No		OUTPUT
tl_peri_o.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_error	Yes	Yes	T20,T199,T207	Yes	T20,T199,T207	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_user.rsp_intg[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_sink	No	No		No		INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T61,*T62,*T63	Yes	T61,T62,T63	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T155,T161,T27	Yes	T155,T161,T27	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T161,T27,T28	Yes	T161,T27,T28	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[0]	Yes	Yes	*T155,*T161,*T27	Yes	T155,T161,T27	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:2]	Yes	Yes	T155,T161,T27	Yes	T155,T161,T27	OUTPUT
tl_spi_host0_o.a_user.instr_type[0]	Yes	Yes	*T155,*T161,*T27	Yes	T155,T161,T27	OUTPUT
tl_spi_host0_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_spi_host0_o.a_user.instr_type[3]	Yes	Yes	T155,T161,T27	Yes	T155,T161,T27	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T161,T27,T28	Yes	T161,T27,T28	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T155,T161,T27	Yes	T155,T161,T27	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[0]	No	No		No		OUTPUT
tl_spi_host0_o.a_source[1]	Yes	Yes	*T155,*T27,*T28	Yes	T155,T27,T28	OUTPUT
tl_spi_host0_o.a_source[5:2]	No	No		No		OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[0]	No	No		No		OUTPUT
tl_spi_host0_o.a_size[1]	Yes	Yes	T155,T161,T27	Yes	T155,T161,T27	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[0]	Yes	Yes	*T28,*T29,*T113	Yes	T28,T29,T113	OUTPUT
tl_spi_host0_o.a_opcode[1]	No	No		No		OUTPUT
tl_spi_host0_o.a_opcode[2]	Yes	Yes	T155,T27,T28	Yes	T155,T27,T28	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T155,T161,T27	Yes	T155,T161,T27	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T155,T161,T27	Yes	T155,T161,T27	INPUT
tl_spi_host0_i.d_error	No	No		No		INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	INPUT
tl_spi_host0_i.d_user.rsp_intg[1:0]	Yes	Yes	T155,T161,T27	Yes	T155,T161,T27	INPUT
tl_spi_host0_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_spi_host0_i.d_user.rsp_intg[5:4]	Yes	Yes	T155,*T161,T28	Yes	T155,T161,T27	INPUT
tl_spi_host0_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	INPUT
tl_spi_host0_i.d_sink	No	No		No		INPUT
tl_spi_host0_i.d_source[0]	No	No		No		INPUT
tl_spi_host0_i.d_source[1]	Yes	Yes	*T155,*T27,*T28	Yes	T155,T27,T28	INPUT
tl_spi_host0_i.d_source[5:2]	No	No		No		INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[0]	No	No		No		INPUT
tl_spi_host0_i.d_size[1]	Yes	Yes	T155,T161,T28	Yes	T155,T161,T27	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T155,*T27,*T28	Yes	T155,T27,T28	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T155,T161,T27	Yes	T155,T161,T27	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T155,T45,T162	Yes	T155,T45,T162	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T45,T114,T163	Yes	T45,T114,T163	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T155,T45,T162	Yes	T155,T45,T162	OUTPUT
tl_spi_host1_o.a_user.instr_type[0]	Yes	Yes	*T155,*T45,*T162	Yes	T155,T45,T162	OUTPUT
tl_spi_host1_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_spi_host1_o.a_user.instr_type[3]	Yes	Yes	T155,T45,T162	Yes	T155,T45,T162	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T45,T114,T163	Yes	T45,T114,T163	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T155,T45,T162	Yes	T155,T45,T162	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[0]	No	No		No		OUTPUT
tl_spi_host1_o.a_source[1]	Yes	Yes	*T155,*T45,*T162	Yes	T155,T45,T162	OUTPUT
tl_spi_host1_o.a_source[5:2]	No	No		No		OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[0]	No	No		No		OUTPUT
tl_spi_host1_o.a_size[1]	Yes	Yes	T155,T45,T162	Yes	T155,T45,T162	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_spi_host1_o.a_opcode[2]	Yes	Yes	T155,T45,T162	Yes	T155,T45,T162	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T155,T45,T162	Yes	T155,T45,T162	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T155,T45,T162	Yes	T155,T45,T162	INPUT
tl_spi_host1_i.d_error	No	No		No		INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T45,T114,T163	Yes	T45,T114,T163	INPUT
tl_spi_host1_i.d_user.rsp_intg[1:0]	Yes	Yes	T155,T45,T162	Yes	T155,T45,T162	INPUT
tl_spi_host1_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_spi_host1_i.d_user.rsp_intg[5:4]	Yes	Yes	T155,T45,T162	Yes	T155,T45,T162	INPUT
tl_spi_host1_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T45,T114,T163	Yes	T45,T114,T163	INPUT
tl_spi_host1_i.d_sink	No	No		No		INPUT
tl_spi_host1_i.d_source[0]	No	No		No		INPUT
tl_spi_host1_i.d_source[1]	Yes	Yes	*T155,*T45,*T162	Yes	T155,T45,T162	INPUT
tl_spi_host1_i.d_source[5:2]	No	No		No		INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[0]	No	No		No		INPUT
tl_spi_host1_i.d_size[1]	Yes	Yes	T155,T45,T162	Yes	T155,T45,T162	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T155,*T45,*T162	Yes	T155,T45,T162	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T155,T45,T162	Yes	T155,T45,T162	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T5,T154,T155	Yes	T5,T154,T155	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T5,T154,T155	Yes	T5,T154,T155	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T154,T155	Yes	T5,T154,T155	OUTPUT
tl_usbdev_o.a_user.instr_type[0]	Yes	Yes	*T5,*T154,*T155	Yes	T5,T154,T155	OUTPUT
tl_usbdev_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_usbdev_o.a_user.instr_type[3]	Yes	Yes	T5,T154,T155	Yes	T5,T154,T155	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T5,T32,T33	Yes	T5,T32,T33	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T5,T154,T155	Yes	T5,T154,T155	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[0]	No	No		No		OUTPUT
tl_usbdev_o.a_source[1]	Yes	Yes	*T5,*T154,*T155	Yes	T5,T154,T155	OUTPUT
tl_usbdev_o.a_source[5:2]	No	No		No		OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[0]	No	No		No		OUTPUT
tl_usbdev_o.a_size[1]	Yes	Yes	T5,T154,T155	Yes	T5,T154,T155	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_usbdev_o.a_opcode[2]	Yes	Yes	T5,T154,T155	Yes	T5,T154,T155	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T5,T154,T155	Yes	T5,T154,T155	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T5,T154,T155	Yes	T5,T154,T155	INPUT
tl_usbdev_i.d_error	No	No		No		INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T5,T154,T155	Yes	T5,T154,T155	INPUT
tl_usbdev_i.d_user.rsp_intg[1:0]	Yes	Yes	T5,T154,T155	Yes	T5,T154,T155	INPUT
tl_usbdev_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_usbdev_i.d_user.rsp_intg[5:4]	Yes	Yes	T5,T154,T155	Yes	T5,T154,T155	INPUT
tl_usbdev_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T5,T154,T155	Yes	T5,T154,T155	INPUT
tl_usbdev_i.d_sink	No	No		No		INPUT
tl_usbdev_i.d_source[0]	No	No		No		INPUT
tl_usbdev_i.d_source[1]	Yes	Yes	*T5,*T154,*T155	Yes	T5,T154,T155	INPUT
tl_usbdev_i.d_source[5:2]	No	No		No		INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[0]	No	No		No		INPUT
tl_usbdev_i.d_size[1]	Yes	Yes	T5,T154,T155	Yes	T5,T154,T155	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T5,*T154,*T155	Yes	T5,T154,T155	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T5,T154,T155	Yes	T5,T154,T155	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[1:0]	Yes	Yes	*T64,*T4,*T5	Yes	T64,T4,T5	OUTPUT
tl_flash_ctrl__core_o.a_source[5:2]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[0]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T4,T5,T6	Yes	T20,T43,T44	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[5:4]	Yes	Yes	T20,*T43,*T44	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T20,T43,T44	INPUT
tl_flash_ctrl__core_i.d_sink	No	No		No		INPUT
tl_flash_ctrl__core_i.d_source[1:0]	Yes	Yes	*T64,*T4,*T5	Yes	T64,T4,T5	INPUT
tl_flash_ctrl__core_i.d_source[5:2]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[0]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_size[1]	Yes	Yes	T20,T43,T44	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T20,T43,T44	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T64	Yes	T64	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T64	Yes	T64	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[0]	Yes	Yes	*T64	Yes	T64	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3]	Yes	Yes	T64	Yes	T64	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T64	Yes	T64	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T64	Yes	T64	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[0]	Yes	Yes	*T64	Yes	T64	OUTPUT
tl_flash_ctrl__prim_o.a_source[5:1]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_size[1]	Yes	Yes	T64	Yes	T64	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2]	Yes	Yes	T64	Yes	T64	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T64	Yes	T64	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T64	Yes	T64	INPUT
tl_flash_ctrl__prim_i.d_error	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T64	Yes	T64	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[1:0]	Yes	Yes	T64	Yes	T64	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[5:4]	Yes	Yes	T64	Yes	T64	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T64	Yes	T64	INPUT
tl_flash_ctrl__prim_i.d_sink	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_source[0]	Yes	Yes	*T64	Yes	T64	INPUT
tl_flash_ctrl__prim_i.d_source[5:1]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[0]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_size[1]	Yes	Yes	T64	Yes	T64	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T64	Yes	T64	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T64	Yes	T64	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T6,T18,T19	Yes	T6,T18,T19	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_source[1]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_source[4:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_source[5]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[0]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T20,T43,T44	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[4]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:5]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_sink	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_source[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_source[1]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_source[4:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_source[5]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[0]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_hmac_o.d_ready	Yes	Yes	T20,T43,T44	Yes	T4,T5,T6	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T54,T55,T208	Yes	T54,T55,T208	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T54,T55,T208	Yes	T54,T55,T208	OUTPUT
tl_hmac_o.a_user.instr_type[0]	Yes	Yes	*T209,*T54,*T55	Yes	T209,T54,T55	OUTPUT
tl_hmac_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_hmac_o.a_user.instr_type[3]	Yes	Yes	T209,T54,T55	Yes	T209,T54,T55	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T54,T55,T208	Yes	T54,T55,T208	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T209,T54,T55	Yes	T209,T54,T55	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[1:0]	Yes	Yes	*T64,*T209,*T54	Yes	T64,T209,T54	OUTPUT
tl_hmac_o.a_source[5:2]	No	No		No		OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[0]	No	No		No		OUTPUT
tl_hmac_o.a_size[1]	Yes	Yes	T209,T54,T55	Yes	T209,T54,T55	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[0]	Yes	Yes	*T208,*T210,*T211	Yes	T208,T210,T211	OUTPUT
tl_hmac_o.a_opcode[1]	No	No		No		OUTPUT
tl_hmac_o.a_opcode[2]	Yes	Yes	T209,T54,T55	Yes	T209,T54,T55	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T209,T54,T55	Yes	T209,T54,T55	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T209,T54,T55	Yes	T209,T54,T55	INPUT
tl_hmac_i.d_error	No	No		No		INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T209,T54,T55	Yes	T209,T54,T55	INPUT
tl_hmac_i.d_user.rsp_intg[1:0]	Yes	Yes	T209,T54,T55	Yes	T209,T54,T55	INPUT
tl_hmac_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_hmac_i.d_user.rsp_intg[5:4]	Yes	Yes	*T209,T54,T55	Yes	T209,T54,T55	INPUT
tl_hmac_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T54,T55,T208	Yes	T54,T55,T208	INPUT
tl_hmac_i.d_sink	No	No		No		INPUT
tl_hmac_i.d_source[1:0]	Yes	Yes	*T64,*T209,*T54	Yes	T64,T209,T54	INPUT
tl_hmac_i.d_source[5:2]	No	No		No		INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[0]	No	No		No		INPUT
tl_hmac_i.d_size[1]	Yes	Yes	T209,T54,T55	Yes	T209,T54,T55	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T54,*T55,*T208	Yes	T54,T55,T208	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T209,T54,T55	Yes	T209,T54,T55	INPUT
tl_kmac_o.d_ready	Yes	Yes	T20,T43,T44	Yes	T4,T5,T6	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T44,T212,T213	Yes	T44,T212,T213	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T44,T83,T209	Yes	T44,T83,T209	OUTPUT
tl_kmac_o.a_user.instr_type[0]	Yes	Yes	*T44,*T83,*T209	Yes	T44,T83,T209	OUTPUT
tl_kmac_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_kmac_o.a_user.instr_type[3]	Yes	Yes	T44,T83,T209	Yes	T44,T83,T209	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T44,T212,T213	Yes	T44,T212,T213	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T44,T83,T209	Yes	T44,T83,T209	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[1:0]	Yes	Yes	*T64,*T117,*T44	Yes	T64,T117,T44	OUTPUT
tl_kmac_o.a_source[5:2]	No	No		No		OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[0]	No	No		No		OUTPUT
tl_kmac_o.a_size[1]	Yes	Yes	T44,T83,T209	Yes	T44,T83,T209	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[0]	Yes	Yes	*T212,*T74,*T214	Yes	T212,T74,T214	OUTPUT
tl_kmac_o.a_opcode[1]	No	No		No		OUTPUT
tl_kmac_o.a_opcode[2]	Yes	Yes	T44,T83,T209	Yes	T44,T83,T209	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T44,T83,T209	Yes	T44,T83,T209	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T44,T83,T209	Yes	T44,T83,T209	INPUT
tl_kmac_i.d_error	No	No		No		INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T44,T83,T209	Yes	T44,T83,T209	INPUT
tl_kmac_i.d_user.rsp_intg[1:0]	Yes	Yes	T44,T83,T209	Yes	T44,T83,T209	INPUT
tl_kmac_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_kmac_i.d_user.rsp_intg[5:4]	Yes	Yes	*T209,T21,T212	Yes	T44,T83,T209	INPUT
tl_kmac_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T44,T83,T21	Yes	T21,T212,T74	INPUT
tl_kmac_i.d_sink	No	No		No		INPUT
tl_kmac_i.d_source[1:0]	Yes	Yes	*T64,*T117,*T44	Yes	T64,T117,T44	INPUT
tl_kmac_i.d_source[5:2]	No	No		No		INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[0]	No	No		No		INPUT
tl_kmac_i.d_size[1]	Yes	Yes	T209,T21,T212	Yes	T44,T83,T209	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T44,*T83,*T21	Yes	T21,T212,T74	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T44,T83,T209	Yes	T44,T83,T209	INPUT
tl_aes_o.d_ready	Yes	Yes	T20,T131,T79	Yes	T4,T5,T6	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T131,T83,T215	Yes	T131,T83,T215	OUTPUT
tl_aes_o.a_user.cmd_intg[0]	Yes	Yes	*T131,*T83,*T215	Yes	T131,T83,T215	OUTPUT
tl_aes_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_aes_o.a_user.cmd_intg[6:2]	Yes	Yes	T131,T79,T83	Yes	T131,T79,T83	OUTPUT
tl_aes_o.a_user.instr_type[0]	Yes	Yes	*T131,*T79,*T83	Yes	T131,T79,T83	OUTPUT
tl_aes_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_aes_o.a_user.instr_type[3]	Yes	Yes	T131,T79,T83	Yes	T131,T79,T83	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T131,T83,T215	Yes	T131,T83,T215	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T131,T79,T83	Yes	T131,T79,T83	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[0]	No	No		No		OUTPUT
tl_aes_o.a_source[1]	Yes	Yes	*T131,*T79,*T83	Yes	T131,T79,T83	OUTPUT
tl_aes_o.a_source[5:2]	No	No		No		OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[0]	No	No		No		OUTPUT
tl_aes_o.a_size[1]	Yes	Yes	T131,T79,T83	Yes	T131,T79,T83	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_aes_o.a_opcode[2]	Yes	Yes	T131,T79,T83	Yes	T131,T79,T83	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T131,T79,T83	Yes	T131,T79,T83	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T131,T79,T83	Yes	T131,T79,T83	INPUT
tl_aes_i.d_error	No	No		No		INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T131,T79,T83	Yes	T131,T79,T83	INPUT
tl_aes_i.d_user.rsp_intg[1:0]	Yes	Yes	T131,T79,T83	Yes	T131,T79,T83	INPUT
tl_aes_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_aes_i.d_user.rsp_intg[5:4]	Yes	Yes	T216,T217,*T218	Yes	T131,T79,T83	INPUT
tl_aes_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T131,T79,T219	Yes	T131,T79,T83	INPUT
tl_aes_i.d_sink	No	No		No		INPUT
tl_aes_i.d_source[0]	No	No		No		INPUT
tl_aes_i.d_source[1]	Yes	Yes	*T131,*T79,*T83	Yes	T131,T79,T83	INPUT
tl_aes_i.d_source[5:2]	No	No		No		INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[0]	No	No		No		INPUT
tl_aes_i.d_size[1]	Yes	Yes	T216,T217,T218	Yes	T131,T79,T83	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T131,*T79,*T83	Yes	T131,T79,T83	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T131,T79,T83	Yes	T131,T79,T83	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_entropy_src_o.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[1:0]	Yes	Yes	*T64,*T4,*T5	Yes	T64,T4,T5	OUTPUT
tl_entropy_src_o.a_source[5:2]	No	No		No		OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[0]	No	No		No		OUTPUT
tl_entropy_src_o.a_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_entropy_src_o.a_opcode[2]	Yes	Yes	T79,T44,T83	Yes	T79,T44,T83	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_error	No	No		No		INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T79,T44,T83	Yes	T79,T44,T83	INPUT
tl_entropy_src_i.d_user.rsp_intg[1:0]	Yes	Yes	T20,*T79,*T43	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_entropy_src_i.d_user.rsp_intg[5:4]	Yes	Yes	*T20,*T43,T44	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T20,T79,T43	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_sink	No	No		No		INPUT
tl_entropy_src_i.d_source[1:0]	Yes	Yes	*T64,*T20,*T79	Yes	T64,T4,T5	INPUT
tl_entropy_src_i.d_source[5:2]	No	No		No		INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[0]	No	No		No		INPUT
tl_entropy_src_i.d_size[1]	Yes	Yes	T20,T43,T44	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T79,*T44,*T83	Yes	T79,T44,T83	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_csrng_o.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T79,T44,T83	Yes	T79,T44,T83	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[1:0]	Yes	Yes	*T64,*T79,*T44	Yes	T64,T79,T44	OUTPUT
tl_csrng_o.a_source[5:2]	No	No		No		OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[0]	No	No		No		OUTPUT
tl_csrng_o.a_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_csrng_o.a_opcode[2]	Yes	Yes	T79,T44,T83	Yes	T79,T44,T83	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_error	No	No		No		INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T79,T44,T83	Yes	T79,T44,T83	INPUT
tl_csrng_i.d_user.rsp_intg[1:0]	Yes	Yes	T20,*T79,*T43	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_csrng_i.d_user.rsp_intg[5:4]	Yes	Yes	*T20,*T43,T44	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T20,T79,T43	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_sink	No	No		No		INPUT
tl_csrng_i.d_source[1:0]	Yes	Yes	*T64,*T79,*T44	Yes	T64,T79,T44	INPUT
tl_csrng_i.d_source[5:2]	No	No		No		INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[0]	No	No		No		INPUT
tl_csrng_i.d_size[1]	Yes	Yes	T20,T43,T44	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T79,*T44,*T83	Yes	T79,T44,T83	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T79,T44,T83	Yes	T79,T44,T83	OUTPUT
tl_edn0_o.a_user.cmd_intg[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_edn0_o.a_user.cmd_intg[6:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_edn0_o.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T79,T44,T83	Yes	T79,T44,T83	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[1:0]	Yes	Yes	*T64,*T4,*T5	Yes	T64,T4,T5	OUTPUT
tl_edn0_o.a_source[5:2]	No	No		No		OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[0]	No	No		No		OUTPUT
tl_edn0_o.a_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_edn0_o.a_opcode[2]	Yes	Yes	T79,T44,T83	Yes	T79,T44,T83	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_error	No	No		No		INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T79,T44,T83	Yes	T79,T44,T83	INPUT
tl_edn0_i.d_user.rsp_intg[1:0]	Yes	Yes	T20,*T79,*T43	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_edn0_i.d_user.rsp_intg[5:4]	Yes	Yes	*T20,*T43,T44	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T20,T79,T43	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_sink	No	No		No		INPUT
tl_edn0_i.d_source[1:0]	Yes	Yes	*T64,*T20,*T79	Yes	T64,T4,T5	INPUT
tl_edn0_i.d_source[5:2]	No	No		No		INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[0]	No	No		No		INPUT
tl_edn0_i.d_size[1]	Yes	Yes	T20,T43,T44	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T79,*T44,*T83	Yes	T79,T44,T83	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn1_o.d_ready	Yes	Yes	T20,T79,T43	Yes	T4,T5,T6	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T79,T44,T83	Yes	T79,T44,T83	OUTPUT
tl_edn1_o.a_user.cmd_intg[0]	Yes	Yes	*T79,*T44,*T83	Yes	T79,T44,T83	OUTPUT
tl_edn1_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_edn1_o.a_user.cmd_intg[6:2]	Yes	Yes	T79,T44,T83	Yes	T79,T44,T83	OUTPUT
tl_edn1_o.a_user.instr_type[0]	Yes	Yes	*T79,*T44,*T83	Yes	T79,T44,T83	OUTPUT
tl_edn1_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_edn1_o.a_user.instr_type[3]	Yes	Yes	T79,T44,T83	Yes	T79,T44,T83	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T79,T44,T83	Yes	T79,T44,T83	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T79,T44,T83	Yes	T79,T44,T83	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[1:0]	Yes	Yes	*T64,*T79,*T44	Yes	T64,T79,T44	OUTPUT
tl_edn1_o.a_source[5:2]	No	No		No		OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[0]	No	No		No		OUTPUT
tl_edn1_o.a_size[1]	Yes	Yes	T79,T44,T83	Yes	T79,T44,T83	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_edn1_o.a_opcode[2]	Yes	Yes	T79,T44,T83	Yes	T79,T44,T83	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T79,T44,T83	Yes	T79,T44,T83	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T79,T44,T83	Yes	T79,T44,T83	INPUT
tl_edn1_i.d_error	No	No		No		INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T79,T44,T83	Yes	T79,T44,T83	INPUT
tl_edn1_i.d_user.rsp_intg[1:0]	Yes	Yes	T79,T44,T83	Yes	T79,T44,T83	INPUT
tl_edn1_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_edn1_i.d_user.rsp_intg[5:4]	Yes	Yes	*T85,*T64,*T220	Yes	T79,T44,T83	INPUT
tl_edn1_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T79,T44,T83	Yes	T79,T44,T83	INPUT
tl_edn1_i.d_sink	No	No		No		INPUT
tl_edn1_i.d_source[1:0]	Yes	Yes	*T64,*T79,*T44	Yes	T64,T79,T44	INPUT
tl_edn1_i.d_source[5:2]	No	No		No		INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[0]	No	No		No		INPUT
tl_edn1_i.d_size[1]	Yes	Yes	T85,T64,T220	Yes	T79,T44,T83	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T79,*T44,*T83	Yes	T79,T44,T83	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T79,T44,T83	Yes	T79,T44,T83	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T18,T19,T20	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
tl_rv_plic_o.a_user.instr_type[0]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
tl_rv_plic_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rv_plic_o.a_user.instr_type[3]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[0]	No	No		No		OUTPUT
tl_rv_plic_o.a_source[1]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	OUTPUT
tl_rv_plic_o.a_source[5:2]	No	No		No		OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[0]	No	No		No		OUTPUT
tl_rv_plic_o.a_size[1]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rv_plic_o.a_opcode[2]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
tl_rv_plic_i.d_error	No	No		No		INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
tl_rv_plic_i.d_user.rsp_intg[1:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
tl_rv_plic_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rv_plic_i.d_user.rsp_intg[5:4]	Yes	Yes	T20,*T122,*T181	Yes	T18,T19,T20	INPUT
tl_rv_plic_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
tl_rv_plic_i.d_sink	No	No		No		INPUT
tl_rv_plic_i.d_source[0]	No	No		No		INPUT
tl_rv_plic_i.d_source[1]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
tl_rv_plic_i.d_source[5:2]	No	No		No		INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[0]	No	No		No		INPUT
tl_rv_plic_i.d_size[1]	Yes	Yes	T20,T122,T181	Yes	T18,T19,T20	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
tl_otbn_o.d_ready	Yes	Yes	T20,T79,T43	Yes	T4,T5,T6	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T79,T83,T73	Yes	T79,T83,T73	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T79,T83,T209	Yes	T79,T83,T209	OUTPUT
tl_otbn_o.a_user.instr_type[0]	Yes	Yes	*T79,*T83,*T209	Yes	T79,T83,T209	OUTPUT
tl_otbn_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_otbn_o.a_user.instr_type[3]	Yes	Yes	T79,T83,T209	Yes	T79,T83,T209	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T79,T83,T73	Yes	T79,T83,T73	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T79,T83,T209	Yes	T79,T83,T209	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[1:0]	Yes	Yes	*T61,*T117,*T221	Yes	T61,T117,T221	OUTPUT
tl_otbn_o.a_source[5:2]	No	No		No		OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[0]	No	No		No		OUTPUT
tl_otbn_o.a_size[1]	Yes	Yes	T79,T83,T209	Yes	T79,T83,T209	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_otbn_o.a_opcode[2]	Yes	Yes	T79,T83,T209	Yes	T79,T83,T209	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T79,T83,T209	Yes	T79,T83,T209	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T79,T83,T209	Yes	T79,T83,T209	INPUT
tl_otbn_i.d_error	No	No		No		INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T79,T83,T73	Yes	T79,T83,T73	INPUT
tl_otbn_i.d_user.rsp_intg[1:0]	Yes	Yes	T79,T83,T209	Yes	T79,T83,T209	INPUT
tl_otbn_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_otbn_i.d_user.rsp_intg[5:4]	Yes	Yes	T79,T83,*T209	Yes	T79,T83,T209	INPUT
tl_otbn_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T79,T83,T209	Yes	T79,T83,T209	INPUT
tl_otbn_i.d_sink	No	No		No		INPUT
tl_otbn_i.d_source[1:0]	Yes	Yes	*T61,*T117,*T221	Yes	T61,T117,T221	INPUT
tl_otbn_i.d_source[5:2]	No	No		No		INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[0]	No	No		No		INPUT
tl_otbn_i.d_size[1]	Yes	Yes	T79,T83,T209	Yes	T79,T83,T209	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T79,*T83,*T73	Yes	T79,T83,T73	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T79,T83,T209	Yes	T79,T83,T209	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T20,T43,T44	Yes	T4,T5,T6	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T43,T44,T83	Yes	T43,T44,T83	OUTPUT
tl_keymgr_o.a_user.cmd_intg[0]	Yes	Yes	*T43,*T44,*T83	Yes	T43,T44,T83	OUTPUT
tl_keymgr_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:2]	Yes	Yes	T43,T44,T83	Yes	T43,T44,T83	OUTPUT
tl_keymgr_o.a_user.instr_type[0]	Yes	Yes	*T43,*T44,*T83	Yes	T43,T44,T83	OUTPUT
tl_keymgr_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_keymgr_o.a_user.instr_type[3]	Yes	Yes	T43,T44,T83	Yes	T43,T44,T83	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T43,T44,T83	Yes	T43,T44,T83	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T43,T44,T83	Yes	T43,T44,T83	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[1:0]	Yes	Yes	*T64,*T43,*T44	Yes	T64,T43,T44	OUTPUT
tl_keymgr_o.a_source[5:2]	No	No		No		OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[0]	No	No		No		OUTPUT
tl_keymgr_o.a_size[1]	Yes	Yes	T43,T44,T83	Yes	T43,T44,T83	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_keymgr_o.a_opcode[2]	Yes	Yes	T43,T44,T83	Yes	T43,T44,T83	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T43,T44,T83	Yes	T43,T44,T83	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T43,T44,T83	Yes	T43,T44,T83	INPUT
tl_keymgr_i.d_error	No	No		No		INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T43,T44,T83	Yes	T43,T44,T83	INPUT
tl_keymgr_i.d_user.rsp_intg[1:0]	Yes	Yes	T43,T44,T83	Yes	T43,T44,T83	INPUT
tl_keymgr_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_keymgr_i.d_user.rsp_intg[5:4]	Yes	Yes	T43,T21,*T7	Yes	T43,T44,T83	INPUT
tl_keymgr_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T43,T44,T83	Yes	T43,T44,T83	INPUT
tl_keymgr_i.d_sink	No	No		No		INPUT
tl_keymgr_i.d_source[1:0]	Yes	Yes	*T64,*T43,*T44	Yes	T64,T43,T44	INPUT
tl_keymgr_i.d_source[5:2]	No	No		No		INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[0]	No	No		No		INPUT
tl_keymgr_i.d_size[1]	Yes	Yes	T43,T21,T7	Yes	T43,T44,T83	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T43,*T44,*T83	Yes	T43,T44,T83	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T43,T44,T83	Yes	T43,T44,T83	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[1:0]	Yes	Yes	*T1,*T222,*T4	Yes	T1,T222,T4	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:2]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[0]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T1	Yes	T1	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T19,T20,T79	Yes	T19,T20,T79	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[2:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[5:4]	Yes	Yes	T20,*T43,*T44	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T19,T20,T79	Yes	T19,T20,T79	INPUT
tl_rv_core_ibex__cfg_i.d_sink	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_source[1:0]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T222,T4	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:2]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[0]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_size[1]	Yes	Yes	T20,T43,T44	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T20,T43,T44	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T54,T55,T57	Yes	T54,T55,T57	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[0]	Yes	Yes	*T54,*T55,*T57	Yes	T54,T55,T57	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:2]	Yes	Yes	T188,T75,T76	Yes	T188,T75,T76	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[0]	Yes	Yes	*T54,*T55,*T57	Yes	T54,T55,T57	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3]	Yes	Yes	T54,T55,T57	Yes	T54,T55,T57	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[4:0]	Yes	Yes	*T54,*T55,*T57	Yes	T54,T55,T57	OUTPUT
tl_sram_ctrl_main__regs_o.a_data[6:5]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[7]	Yes	Yes	*T54,*T55,*T57	Yes	T54,T55,T57	OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:8]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T54,T55,T57	Yes	T54,T55,T57	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[1:0]	Yes	Yes	*T223,*T54,*T55	Yes	T223,T54,T55	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:2]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[0]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1]	Yes	Yes	T54,T55,T57	Yes	T54,T55,T57	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2]	Yes	Yes	T188,T75,T76	Yes	T188,T75,T76	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T54,T55,T57	Yes	T54,T55,T57	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T54,T55,T57	Yes	T54,T55,T57	INPUT
tl_sram_ctrl_main__regs_i.d_error	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[5:0]	Yes	Yes	*T190,*T224,*T225	Yes	T190,T224,T225	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[1:0]	Yes	Yes	T54,T55,T188	Yes	T54,T55,T57	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[5:4]	Yes	Yes	*T54,*T55,T188	Yes	T54,T55,T57	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T54,T55,T188	Yes	T54,T55,T57	INPUT
tl_sram_ctrl_main__regs_i.d_sink	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_source[0]	No	No		Yes	T223	INPUT
tl_sram_ctrl_main__regs_i.d_source[1]	Yes	Yes	*T54,*T55,*T188	Yes	T54,T55,T57	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:2]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[0]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_size[1]	Yes	Yes	T54,T55,T188	Yes	T54,T55,T57	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T188,*T75,*T76	Yes	T188,T75,T76	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T54,T55,T57	Yes	T54,T55,T57	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[4:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5]	No	No		No		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[0]	No	No		No		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[1]	No	No		No		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T20,T43,T44	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[5:4]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_sink	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_source[4:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_source[5]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[0]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range