Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc
| Total | Covered | Percent |
Conditions | 13 | 12 | 92.31 |
Logical | 13 | 12 | 92.31 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T8 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T8 |
1 | 1 | Covered | T1,T2,T8 |
LINE 123
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T1,T2,T8 |
1 | - | Covered | T1,T2,T12 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T8 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T8 |
1 | 1 | Covered | T1,T2,T8 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T8 |
0 |
0 |
1 |
Covered |
T1,T2,T8 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T8 |
0 |
0 |
1 |
Covered |
T1,T2,T8 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
125218 |
0 |
0 |
T1 |
38023 |
648 |
0 |
0 |
T2 |
37930 |
838 |
0 |
0 |
T8 |
0 |
464 |
0 |
0 |
T12 |
0 |
824 |
0 |
0 |
T13 |
0 |
667 |
0 |
0 |
T53 |
459340 |
0 |
0 |
0 |
T101 |
548257 |
0 |
0 |
0 |
T102 |
16085 |
0 |
0 |
0 |
T103 |
271560 |
0 |
0 |
0 |
T104 |
71622 |
0 |
0 |
0 |
T105 |
578469 |
0 |
0 |
0 |
T106 |
26855 |
0 |
0 |
0 |
T107 |
19040 |
0 |
0 |
0 |
T138 |
0 |
5655 |
0 |
0 |
T139 |
0 |
2920 |
0 |
0 |
T140 |
0 |
6431 |
0 |
0 |
T391 |
0 |
334 |
0 |
0 |
T392 |
0 |
714 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1951669 |
1725930 |
0 |
0 |
T4 |
446 |
275 |
0 |
0 |
T5 |
494 |
322 |
0 |
0 |
T6 |
2872 |
2700 |
0 |
0 |
T16 |
663 |
489 |
0 |
0 |
T17 |
1227 |
1053 |
0 |
0 |
T39 |
835 |
662 |
0 |
0 |
T40 |
884 |
711 |
0 |
0 |
T41 |
1613 |
1437 |
0 |
0 |
T47 |
1126 |
954 |
0 |
0 |
T89 |
328 |
154 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
314 |
0 |
0 |
T1 |
38023 |
2 |
0 |
0 |
T2 |
37930 |
2 |
0 |
0 |
T8 |
0 |
1 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T53 |
459340 |
0 |
0 |
0 |
T101 |
548257 |
0 |
0 |
0 |
T102 |
16085 |
0 |
0 |
0 |
T103 |
271560 |
0 |
0 |
0 |
T104 |
71622 |
0 |
0 |
0 |
T105 |
578469 |
0 |
0 |
0 |
T106 |
26855 |
0 |
0 |
0 |
T107 |
19040 |
0 |
0 |
0 |
T138 |
0 |
14 |
0 |
0 |
T139 |
0 |
7 |
0 |
0 |
T140 |
0 |
16 |
0 |
0 |
T391 |
0 |
1 |
0 |
0 |
T392 |
0 |
2 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
162208507 |
0 |
0 |
T4 |
23527 |
23141 |
0 |
0 |
T5 |
26869 |
26481 |
0 |
0 |
T6 |
316536 |
316049 |
0 |
0 |
T16 |
59793 |
58878 |
0 |
0 |
T17 |
34561 |
34102 |
0 |
0 |
T39 |
54670 |
54215 |
0 |
0 |
T40 |
60759 |
60300 |
0 |
0 |
T41 |
85213 |
84571 |
0 |
0 |
T47 |
43300 |
42904 |
0 |
0 |
T89 |
16169 |
15488 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 20 | 90.91 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 0 | 0.00 |
CONT_ASSIGN | 156 | 1 | 0 | 0.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
0 |
1 |
156 |
0 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc
| Total | Covered | Percent |
Conditions | 13 | 11 | 84.62 |
Logical | 13 | 11 | 84.62 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T8,T138,T391 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T8,T138,T391 |
1 | 1 | Covered | T8,T138,T391 |
LINE 123
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T8,T138,T391 |
1 | - | Not Covered | |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T8,T138,T391 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T8,T138,T391 |
1 | 1 | Covered | T8,T138,T391 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T8,T138,T391 |
0 |
0 |
1 |
Covered |
T8,T138,T391 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T8,T138,T391 |
0 |
0 |
1 |
Covered |
T8,T138,T391 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
124151 |
0 |
0 |
T8 |
452183 |
387 |
0 |
0 |
T72 |
26321 |
0 |
0 |
0 |
T81 |
274028 |
0 |
0 |
0 |
T90 |
64923 |
0 |
0 |
0 |
T110 |
401184 |
0 |
0 |
0 |
T138 |
0 |
4037 |
0 |
0 |
T139 |
0 |
1744 |
0 |
0 |
T140 |
0 |
7981 |
0 |
0 |
T238 |
57805 |
0 |
0 |
0 |
T390 |
0 |
396 |
0 |
0 |
T391 |
0 |
361 |
0 |
0 |
T392 |
0 |
725 |
0 |
0 |
T416 |
0 |
705 |
0 |
0 |
T417 |
0 |
733 |
0 |
0 |
T418 |
0 |
385 |
0 |
0 |
T419 |
36972 |
0 |
0 |
0 |
T420 |
67641 |
0 |
0 |
0 |
T421 |
69007 |
0 |
0 |
0 |
T422 |
59437 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1951669 |
1725930 |
0 |
0 |
T4 |
446 |
275 |
0 |
0 |
T5 |
494 |
322 |
0 |
0 |
T6 |
2872 |
2700 |
0 |
0 |
T16 |
663 |
489 |
0 |
0 |
T17 |
1227 |
1053 |
0 |
0 |
T39 |
835 |
662 |
0 |
0 |
T40 |
884 |
711 |
0 |
0 |
T41 |
1613 |
1437 |
0 |
0 |
T47 |
1126 |
954 |
0 |
0 |
T89 |
328 |
154 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
311 |
0 |
0 |
T8 |
452183 |
1 |
0 |
0 |
T72 |
26321 |
0 |
0 |
0 |
T81 |
274028 |
0 |
0 |
0 |
T90 |
64923 |
0 |
0 |
0 |
T110 |
401184 |
0 |
0 |
0 |
T138 |
0 |
10 |
0 |
0 |
T139 |
0 |
4 |
0 |
0 |
T140 |
0 |
20 |
0 |
0 |
T238 |
57805 |
0 |
0 |
0 |
T390 |
0 |
1 |
0 |
0 |
T391 |
0 |
1 |
0 |
0 |
T392 |
0 |
2 |
0 |
0 |
T416 |
0 |
2 |
0 |
0 |
T417 |
0 |
2 |
0 |
0 |
T418 |
0 |
1 |
0 |
0 |
T419 |
36972 |
0 |
0 |
0 |
T420 |
67641 |
0 |
0 |
0 |
T421 |
69007 |
0 |
0 |
0 |
T422 |
59437 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
162208507 |
0 |
0 |
T4 |
23527 |
23141 |
0 |
0 |
T5 |
26869 |
26481 |
0 |
0 |
T6 |
316536 |
316049 |
0 |
0 |
T16 |
59793 |
58878 |
0 |
0 |
T17 |
34561 |
34102 |
0 |
0 |
T39 |
54670 |
54215 |
0 |
0 |
T40 |
60759 |
60300 |
0 |
0 |
T41 |
85213 |
84571 |
0 |
0 |
T47 |
43300 |
42904 |
0 |
0 |
T89 |
16169 |
15488 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc
| Total | Covered | Percent |
Conditions | 13 | 12 | 92.31 |
Logical | 13 | 12 | 92.31 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T14,T8,T143 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T14,T8,T138 |
1 | 1 | Covered | T14,T8,T138 |
LINE 123
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T14,T8,T138 |
1 | - | Covered | T14 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T14,T8,T138 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T14,T8,T138 |
1 | 1 | Covered | T14,T8,T138 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T14,T8,T138 |
0 |
0 |
1 |
Covered |
T14,T8,T138 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T14,T8,T138 |
0 |
0 |
1 |
Covered |
T14,T8,T138 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
115842 |
0 |
0 |
T8 |
0 |
461 |
0 |
0 |
T14 |
34780 |
918 |
0 |
0 |
T136 |
47633 |
0 |
0 |
0 |
T138 |
0 |
3925 |
0 |
0 |
T139 |
0 |
2864 |
0 |
0 |
T140 |
0 |
4600 |
0 |
0 |
T304 |
63585 |
0 |
0 |
0 |
T345 |
40859 |
0 |
0 |
0 |
T362 |
58764 |
0 |
0 |
0 |
T390 |
0 |
368 |
0 |
0 |
T391 |
0 |
244 |
0 |
0 |
T392 |
0 |
724 |
0 |
0 |
T416 |
0 |
721 |
0 |
0 |
T417 |
0 |
686 |
0 |
0 |
T423 |
53848 |
0 |
0 |
0 |
T424 |
139322 |
0 |
0 |
0 |
T425 |
315859 |
0 |
0 |
0 |
T426 |
11261 |
0 |
0 |
0 |
T427 |
63727 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1951669 |
1725930 |
0 |
0 |
T4 |
446 |
275 |
0 |
0 |
T5 |
494 |
322 |
0 |
0 |
T6 |
2872 |
2700 |
0 |
0 |
T16 |
663 |
489 |
0 |
0 |
T17 |
1227 |
1053 |
0 |
0 |
T39 |
835 |
662 |
0 |
0 |
T40 |
884 |
711 |
0 |
0 |
T41 |
1613 |
1437 |
0 |
0 |
T47 |
1126 |
954 |
0 |
0 |
T89 |
328 |
154 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
291 |
0 |
0 |
T8 |
0 |
1 |
0 |
0 |
T14 |
34780 |
2 |
0 |
0 |
T136 |
47633 |
0 |
0 |
0 |
T138 |
0 |
10 |
0 |
0 |
T139 |
0 |
7 |
0 |
0 |
T140 |
0 |
11 |
0 |
0 |
T304 |
63585 |
0 |
0 |
0 |
T345 |
40859 |
0 |
0 |
0 |
T362 |
58764 |
0 |
0 |
0 |
T390 |
0 |
1 |
0 |
0 |
T391 |
0 |
1 |
0 |
0 |
T392 |
0 |
2 |
0 |
0 |
T416 |
0 |
2 |
0 |
0 |
T417 |
0 |
2 |
0 |
0 |
T423 |
53848 |
0 |
0 |
0 |
T424 |
139322 |
0 |
0 |
0 |
T425 |
315859 |
0 |
0 |
0 |
T426 |
11261 |
0 |
0 |
0 |
T427 |
63727 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
162208507 |
0 |
0 |
T4 |
23527 |
23141 |
0 |
0 |
T5 |
26869 |
26481 |
0 |
0 |
T6 |
316536 |
316049 |
0 |
0 |
T16 |
59793 |
58878 |
0 |
0 |
T17 |
34561 |
34102 |
0 |
0 |
T39 |
54670 |
54215 |
0 |
0 |
T40 |
60759 |
60300 |
0 |
0 |
T41 |
85213 |
84571 |
0 |
0 |
T47 |
43300 |
42904 |
0 |
0 |
T89 |
16169 |
15488 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 20 | 90.91 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 0 | 0.00 |
CONT_ASSIGN | 156 | 1 | 0 | 0.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
0 |
1 |
156 |
0 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc
| Total | Covered | Percent |
Conditions | 13 | 11 | 84.62 |
Logical | 13 | 11 | 84.62 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T8,T428,T138 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T8,T138,T391 |
1 | 1 | Covered | T8,T138,T391 |
LINE 123
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T8,T138,T391 |
1 | - | Not Covered | |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T8,T138,T391 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T8,T138,T391 |
1 | 1 | Covered | T8,T138,T391 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T8,T138,T391 |
0 |
0 |
1 |
Covered |
T8,T138,T391 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T8,T138,T391 |
0 |
0 |
1 |
Covered |
T8,T138,T391 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
118060 |
0 |
0 |
T8 |
452183 |
393 |
0 |
0 |
T72 |
26321 |
0 |
0 |
0 |
T81 |
274028 |
0 |
0 |
0 |
T90 |
64923 |
0 |
0 |
0 |
T110 |
401184 |
0 |
0 |
0 |
T138 |
0 |
5044 |
0 |
0 |
T139 |
0 |
1301 |
0 |
0 |
T140 |
0 |
4973 |
0 |
0 |
T238 |
57805 |
0 |
0 |
0 |
T390 |
0 |
456 |
0 |
0 |
T391 |
0 |
335 |
0 |
0 |
T392 |
0 |
618 |
0 |
0 |
T416 |
0 |
670 |
0 |
0 |
T417 |
0 |
636 |
0 |
0 |
T418 |
0 |
407 |
0 |
0 |
T419 |
36972 |
0 |
0 |
0 |
T420 |
67641 |
0 |
0 |
0 |
T421 |
69007 |
0 |
0 |
0 |
T422 |
59437 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1951669 |
1725930 |
0 |
0 |
T4 |
446 |
275 |
0 |
0 |
T5 |
494 |
322 |
0 |
0 |
T6 |
2872 |
2700 |
0 |
0 |
T16 |
663 |
489 |
0 |
0 |
T17 |
1227 |
1053 |
0 |
0 |
T39 |
835 |
662 |
0 |
0 |
T40 |
884 |
711 |
0 |
0 |
T41 |
1613 |
1437 |
0 |
0 |
T47 |
1126 |
954 |
0 |
0 |
T89 |
328 |
154 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
298 |
0 |
0 |
T8 |
452183 |
1 |
0 |
0 |
T72 |
26321 |
0 |
0 |
0 |
T81 |
274028 |
0 |
0 |
0 |
T90 |
64923 |
0 |
0 |
0 |
T110 |
401184 |
0 |
0 |
0 |
T138 |
0 |
13 |
0 |
0 |
T139 |
0 |
3 |
0 |
0 |
T140 |
0 |
12 |
0 |
0 |
T238 |
57805 |
0 |
0 |
0 |
T390 |
0 |
1 |
0 |
0 |
T391 |
0 |
1 |
0 |
0 |
T392 |
0 |
2 |
0 |
0 |
T416 |
0 |
2 |
0 |
0 |
T417 |
0 |
2 |
0 |
0 |
T418 |
0 |
1 |
0 |
0 |
T419 |
36972 |
0 |
0 |
0 |
T420 |
67641 |
0 |
0 |
0 |
T421 |
69007 |
0 |
0 |
0 |
T422 |
59437 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
162208507 |
0 |
0 |
T4 |
23527 |
23141 |
0 |
0 |
T5 |
26869 |
26481 |
0 |
0 |
T6 |
316536 |
316049 |
0 |
0 |
T16 |
59793 |
58878 |
0 |
0 |
T17 |
34561 |
34102 |
0 |
0 |
T39 |
54670 |
54215 |
0 |
0 |
T40 |
60759 |
60300 |
0 |
0 |
T41 |
85213 |
84571 |
0 |
0 |
T47 |
43300 |
42904 |
0 |
0 |
T89 |
16169 |
15488 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc
| Total | Covered | Percent |
Conditions | 13 | 12 | 92.31 |
Logical | 13 | 12 | 92.31 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T15,T8,T138 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T15,T8,T138 |
1 | 1 | Covered | T15,T8,T138 |
LINE 123
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T15,T8,T138 |
1 | - | Covered | T15 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T15,T8,T138 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T15,T8,T138 |
1 | 1 | Covered | T15,T8,T138 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T15,T8,T138 |
0 |
0 |
1 |
Covered |
T15,T8,T138 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T15,T8,T138 |
0 |
0 |
1 |
Covered |
T15,T8,T138 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
112292 |
0 |
0 |
T8 |
0 |
451 |
0 |
0 |
T14 |
34780 |
0 |
0 |
0 |
T15 |
21463 |
1005 |
0 |
0 |
T91 |
55278 |
0 |
0 |
0 |
T92 |
111589 |
0 |
0 |
0 |
T93 |
46711 |
0 |
0 |
0 |
T94 |
328553 |
0 |
0 |
0 |
T95 |
84570 |
0 |
0 |
0 |
T96 |
14960 |
0 |
0 |
0 |
T97 |
93016 |
0 |
0 |
0 |
T138 |
0 |
3087 |
0 |
0 |
T139 |
0 |
4889 |
0 |
0 |
T140 |
0 |
2380 |
0 |
0 |
T390 |
0 |
420 |
0 |
0 |
T391 |
0 |
346 |
0 |
0 |
T392 |
0 |
765 |
0 |
0 |
T416 |
0 |
624 |
0 |
0 |
T417 |
0 |
768 |
0 |
0 |
T423 |
53848 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1951669 |
1725930 |
0 |
0 |
T4 |
446 |
275 |
0 |
0 |
T5 |
494 |
322 |
0 |
0 |
T6 |
2872 |
2700 |
0 |
0 |
T16 |
663 |
489 |
0 |
0 |
T17 |
1227 |
1053 |
0 |
0 |
T39 |
835 |
662 |
0 |
0 |
T40 |
884 |
711 |
0 |
0 |
T41 |
1613 |
1437 |
0 |
0 |
T47 |
1126 |
954 |
0 |
0 |
T89 |
328 |
154 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
282 |
0 |
0 |
T8 |
0 |
1 |
0 |
0 |
T14 |
34780 |
0 |
0 |
0 |
T15 |
21463 |
2 |
0 |
0 |
T91 |
55278 |
0 |
0 |
0 |
T92 |
111589 |
0 |
0 |
0 |
T93 |
46711 |
0 |
0 |
0 |
T94 |
328553 |
0 |
0 |
0 |
T95 |
84570 |
0 |
0 |
0 |
T96 |
14960 |
0 |
0 |
0 |
T97 |
93016 |
0 |
0 |
0 |
T138 |
0 |
8 |
0 |
0 |
T139 |
0 |
12 |
0 |
0 |
T140 |
0 |
6 |
0 |
0 |
T390 |
0 |
1 |
0 |
0 |
T391 |
0 |
1 |
0 |
0 |
T392 |
0 |
2 |
0 |
0 |
T416 |
0 |
2 |
0 |
0 |
T417 |
0 |
2 |
0 |
0 |
T423 |
53848 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
162208507 |
0 |
0 |
T4 |
23527 |
23141 |
0 |
0 |
T5 |
26869 |
26481 |
0 |
0 |
T6 |
316536 |
316049 |
0 |
0 |
T16 |
59793 |
58878 |
0 |
0 |
T17 |
34561 |
34102 |
0 |
0 |
T39 |
54670 |
54215 |
0 |
0 |
T40 |
60759 |
60300 |
0 |
0 |
T41 |
85213 |
84571 |
0 |
0 |
T47 |
43300 |
42904 |
0 |
0 |
T89 |
16169 |
15488 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc
| Total | Covered | Percent |
Conditions | 13 | 12 | 92.31 |
Logical | 13 | 12 | 92.31 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T10,T11 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T3,T10,T11 |
1 | 1 | Covered | T3,T10,T11 |
LINE 123
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T3,T10,T11 |
1 | - | Covered | T3,T10,T11 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T10,T11 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T3,T10,T11 |
1 | 1 | Covered | T3,T10,T11 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T3,T10,T11 |
0 |
0 |
1 |
Covered |
T3,T10,T11 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T3,T10,T11 |
0 |
0 |
1 |
Covered |
T3,T10,T11 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
129649 |
0 |
0 |
T3 |
139731 |
1530 |
0 |
0 |
T8 |
0 |
476 |
0 |
0 |
T10 |
0 |
1418 |
0 |
0 |
T11 |
0 |
1440 |
0 |
0 |
T24 |
112487 |
0 |
0 |
0 |
T27 |
239098 |
0 |
0 |
0 |
T57 |
43818 |
0 |
0 |
0 |
T65 |
52488 |
0 |
0 |
0 |
T66 |
11071 |
0 |
0 |
0 |
T98 |
0 |
663 |
0 |
0 |
T99 |
0 |
751 |
0 |
0 |
T100 |
0 |
611 |
0 |
0 |
T410 |
315432 |
0 |
0 |
0 |
T415 |
0 |
743 |
0 |
0 |
T429 |
0 |
873 |
0 |
0 |
T430 |
0 |
769 |
0 |
0 |
T431 |
24345 |
0 |
0 |
0 |
T432 |
34410 |
0 |
0 |
0 |
T433 |
38857 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1951669 |
1725930 |
0 |
0 |
T4 |
446 |
275 |
0 |
0 |
T5 |
494 |
322 |
0 |
0 |
T6 |
2872 |
2700 |
0 |
0 |
T16 |
663 |
489 |
0 |
0 |
T17 |
1227 |
1053 |
0 |
0 |
T39 |
835 |
662 |
0 |
0 |
T40 |
884 |
711 |
0 |
0 |
T41 |
1613 |
1437 |
0 |
0 |
T47 |
1126 |
954 |
0 |
0 |
T89 |
328 |
154 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
327 |
0 |
0 |
T3 |
139731 |
4 |
0 |
0 |
T8 |
0 |
1 |
0 |
0 |
T10 |
0 |
4 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T24 |
112487 |
0 |
0 |
0 |
T27 |
239098 |
0 |
0 |
0 |
T57 |
43818 |
0 |
0 |
0 |
T65 |
52488 |
0 |
0 |
0 |
T66 |
11071 |
0 |
0 |
0 |
T98 |
0 |
2 |
0 |
0 |
T99 |
0 |
2 |
0 |
0 |
T100 |
0 |
2 |
0 |
0 |
T410 |
315432 |
0 |
0 |
0 |
T415 |
0 |
2 |
0 |
0 |
T429 |
0 |
2 |
0 |
0 |
T430 |
0 |
2 |
0 |
0 |
T431 |
24345 |
0 |
0 |
0 |
T432 |
34410 |
0 |
0 |
0 |
T433 |
38857 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
162208507 |
0 |
0 |
T4 |
23527 |
23141 |
0 |
0 |
T5 |
26869 |
26481 |
0 |
0 |
T6 |
316536 |
316049 |
0 |
0 |
T16 |
59793 |
58878 |
0 |
0 |
T17 |
34561 |
34102 |
0 |
0 |
T39 |
54670 |
54215 |
0 |
0 |
T40 |
60759 |
60300 |
0 |
0 |
T41 |
85213 |
84571 |
0 |
0 |
T47 |
43300 |
42904 |
0 |
0 |
T89 |
16169 |
15488 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 20 | 90.91 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 0 | 0.00 |
CONT_ASSIGN | 156 | 1 | 0 | 0.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
0 |
1 |
156 |
0 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc
| Total | Covered | Percent |
Conditions | 13 | 11 | 84.62 |
Logical | 13 | 11 | 84.62 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T8,T138,T391 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T8,T138,T391 |
1 | 1 | Covered | T8,T138,T391 |
LINE 123
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T8,T138,T391 |
1 | - | Not Covered | |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T8,T138,T391 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T8,T138,T391 |
1 | 1 | Covered | T8,T138,T391 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T8,T138,T391 |
0 |
0 |
1 |
Covered |
T8,T138,T391 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T8,T138,T391 |
0 |
0 |
1 |
Covered |
T8,T138,T391 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
138682 |
0 |
0 |
T8 |
452183 |
385 |
0 |
0 |
T72 |
26321 |
0 |
0 |
0 |
T81 |
274028 |
0 |
0 |
0 |
T90 |
64923 |
0 |
0 |
0 |
T110 |
401184 |
0 |
0 |
0 |
T138 |
0 |
5581 |
0 |
0 |
T140 |
0 |
4127 |
0 |
0 |
T238 |
57805 |
0 |
0 |
0 |
T390 |
0 |
365 |
0 |
0 |
T391 |
0 |
251 |
0 |
0 |
T392 |
0 |
702 |
0 |
0 |
T408 |
0 |
812 |
0 |
0 |
T416 |
0 |
725 |
0 |
0 |
T417 |
0 |
653 |
0 |
0 |
T418 |
0 |
386 |
0 |
0 |
T419 |
36972 |
0 |
0 |
0 |
T420 |
67641 |
0 |
0 |
0 |
T421 |
69007 |
0 |
0 |
0 |
T422 |
59437 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1951669 |
1725930 |
0 |
0 |
T4 |
446 |
275 |
0 |
0 |
T5 |
494 |
322 |
0 |
0 |
T6 |
2872 |
2700 |
0 |
0 |
T16 |
663 |
489 |
0 |
0 |
T17 |
1227 |
1053 |
0 |
0 |
T39 |
835 |
662 |
0 |
0 |
T40 |
884 |
711 |
0 |
0 |
T41 |
1613 |
1437 |
0 |
0 |
T47 |
1126 |
954 |
0 |
0 |
T89 |
328 |
154 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
346 |
0 |
0 |
T8 |
452183 |
1 |
0 |
0 |
T72 |
26321 |
0 |
0 |
0 |
T81 |
274028 |
0 |
0 |
0 |
T90 |
64923 |
0 |
0 |
0 |
T110 |
401184 |
0 |
0 |
0 |
T138 |
0 |
14 |
0 |
0 |
T140 |
0 |
10 |
0 |
0 |
T238 |
57805 |
0 |
0 |
0 |
T390 |
0 |
1 |
0 |
0 |
T391 |
0 |
1 |
0 |
0 |
T392 |
0 |
2 |
0 |
0 |
T408 |
0 |
2 |
0 |
0 |
T416 |
0 |
2 |
0 |
0 |
T417 |
0 |
2 |
0 |
0 |
T418 |
0 |
1 |
0 |
0 |
T419 |
36972 |
0 |
0 |
0 |
T420 |
67641 |
0 |
0 |
0 |
T421 |
69007 |
0 |
0 |
0 |
T422 |
59437 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
162208507 |
0 |
0 |
T4 |
23527 |
23141 |
0 |
0 |
T5 |
26869 |
26481 |
0 |
0 |
T6 |
316536 |
316049 |
0 |
0 |
T16 |
59793 |
58878 |
0 |
0 |
T17 |
34561 |
34102 |
0 |
0 |
T39 |
54670 |
54215 |
0 |
0 |
T40 |
60759 |
60300 |
0 |
0 |
T41 |
85213 |
84571 |
0 |
0 |
T47 |
43300 |
42904 |
0 |
0 |
T89 |
16169 |
15488 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 20 | 90.91 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 0 | 0.00 |
CONT_ASSIGN | 156 | 1 | 0 | 0.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
0 |
1 |
156 |
0 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc
| Total | Covered | Percent |
Conditions | 13 | 11 | 84.62 |
Logical | 13 | 11 | 84.62 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T8,T138,T391 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T8,T138,T391 |
1 | 1 | Covered | T8,T138,T391 |
LINE 123
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T8,T138,T391 |
1 | - | Not Covered | |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T8,T138,T391 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T8,T138,T391 |
1 | 1 | Covered | T8,T138,T391 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T8,T138,T391 |
0 |
0 |
1 |
Covered |
T8,T138,T391 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T8,T138,T391 |
0 |
0 |
1 |
Covered |
T8,T138,T391 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
130222 |
0 |
0 |
T8 |
452183 |
413 |
0 |
0 |
T72 |
26321 |
0 |
0 |
0 |
T81 |
274028 |
0 |
0 |
0 |
T90 |
64923 |
0 |
0 |
0 |
T110 |
401184 |
0 |
0 |
0 |
T138 |
0 |
6238 |
0 |
0 |
T139 |
0 |
4107 |
0 |
0 |
T140 |
0 |
5327 |
0 |
0 |
T238 |
57805 |
0 |
0 |
0 |
T390 |
0 |
366 |
0 |
0 |
T391 |
0 |
347 |
0 |
0 |
T392 |
0 |
709 |
0 |
0 |
T416 |
0 |
734 |
0 |
0 |
T417 |
0 |
749 |
0 |
0 |
T418 |
0 |
432 |
0 |
0 |
T419 |
36972 |
0 |
0 |
0 |
T420 |
67641 |
0 |
0 |
0 |
T421 |
69007 |
0 |
0 |
0 |
T422 |
59437 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1951669 |
1725930 |
0 |
0 |
T4 |
446 |
275 |
0 |
0 |
T5 |
494 |
322 |
0 |
0 |
T6 |
2872 |
2700 |
0 |
0 |
T16 |
663 |
489 |
0 |
0 |
T17 |
1227 |
1053 |
0 |
0 |
T39 |
835 |
662 |
0 |
0 |
T40 |
884 |
711 |
0 |
0 |
T41 |
1613 |
1437 |
0 |
0 |
T47 |
1126 |
954 |
0 |
0 |
T89 |
328 |
154 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
327 |
0 |
0 |
T8 |
452183 |
1 |
0 |
0 |
T72 |
26321 |
0 |
0 |
0 |
T81 |
274028 |
0 |
0 |
0 |
T90 |
64923 |
0 |
0 |
0 |
T110 |
401184 |
0 |
0 |
0 |
T138 |
0 |
16 |
0 |
0 |
T139 |
0 |
10 |
0 |
0 |
T140 |
0 |
13 |
0 |
0 |
T238 |
57805 |
0 |
0 |
0 |
T390 |
0 |
1 |
0 |
0 |
T391 |
0 |
1 |
0 |
0 |
T392 |
0 |
2 |
0 |
0 |
T416 |
0 |
2 |
0 |
0 |
T417 |
0 |
2 |
0 |
0 |
T418 |
0 |
1 |
0 |
0 |
T419 |
36972 |
0 |
0 |
0 |
T420 |
67641 |
0 |
0 |
0 |
T421 |
69007 |
0 |
0 |
0 |
T422 |
59437 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
162208507 |
0 |
0 |
T4 |
23527 |
23141 |
0 |
0 |
T5 |
26869 |
26481 |
0 |
0 |
T6 |
316536 |
316049 |
0 |
0 |
T16 |
59793 |
58878 |
0 |
0 |
T17 |
34561 |
34102 |
0 |
0 |
T39 |
54670 |
54215 |
0 |
0 |
T40 |
60759 |
60300 |
0 |
0 |
T41 |
85213 |
84571 |
0 |
0 |
T47 |
43300 |
42904 |
0 |
0 |
T89 |
16169 |
15488 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T8 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T8 |
1 | 1 | Covered | T1,T2,T8 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T8 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T8 |
1 | 1 | Covered | T1,T2,T8 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T8 |
0 |
0 |
1 |
Covered |
T1,T2,T8 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T8 |
0 |
0 |
1 |
Covered |
T1,T2,T8 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
127035 |
0 |
0 |
T1 |
38023 |
273 |
0 |
0 |
T2 |
37930 |
341 |
0 |
0 |
T8 |
0 |
478 |
0 |
0 |
T12 |
0 |
278 |
0 |
0 |
T13 |
0 |
291 |
0 |
0 |
T53 |
459340 |
0 |
0 |
0 |
T101 |
548257 |
0 |
0 |
0 |
T102 |
16085 |
0 |
0 |
0 |
T103 |
271560 |
0 |
0 |
0 |
T104 |
71622 |
0 |
0 |
0 |
T105 |
578469 |
0 |
0 |
0 |
T106 |
26855 |
0 |
0 |
0 |
T107 |
19040 |
0 |
0 |
0 |
T138 |
0 |
3967 |
0 |
0 |
T139 |
0 |
2878 |
0 |
0 |
T140 |
0 |
4063 |
0 |
0 |
T391 |
0 |
326 |
0 |
0 |
T392 |
0 |
751 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1951669 |
1725930 |
0 |
0 |
T4 |
446 |
275 |
0 |
0 |
T5 |
494 |
322 |
0 |
0 |
T6 |
2872 |
2700 |
0 |
0 |
T16 |
663 |
489 |
0 |
0 |
T17 |
1227 |
1053 |
0 |
0 |
T39 |
835 |
662 |
0 |
0 |
T40 |
884 |
711 |
0 |
0 |
T41 |
1613 |
1437 |
0 |
0 |
T47 |
1126 |
954 |
0 |
0 |
T89 |
328 |
154 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
317 |
0 |
0 |
T1 |
38023 |
1 |
0 |
0 |
T2 |
37930 |
1 |
0 |
0 |
T8 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T53 |
459340 |
0 |
0 |
0 |
T101 |
548257 |
0 |
0 |
0 |
T102 |
16085 |
0 |
0 |
0 |
T103 |
271560 |
0 |
0 |
0 |
T104 |
71622 |
0 |
0 |
0 |
T105 |
578469 |
0 |
0 |
0 |
T106 |
26855 |
0 |
0 |
0 |
T107 |
19040 |
0 |
0 |
0 |
T138 |
0 |
10 |
0 |
0 |
T139 |
0 |
7 |
0 |
0 |
T140 |
0 |
10 |
0 |
0 |
T391 |
0 |
1 |
0 |
0 |
T392 |
0 |
2 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
162208507 |
0 |
0 |
T4 |
23527 |
23141 |
0 |
0 |
T5 |
26869 |
26481 |
0 |
0 |
T6 |
316536 |
316049 |
0 |
0 |
T16 |
59793 |
58878 |
0 |
0 |
T17 |
34561 |
34102 |
0 |
0 |
T39 |
54670 |
54215 |
0 |
0 |
T40 |
60759 |
60300 |
0 |
0 |
T41 |
85213 |
84571 |
0 |
0 |
T47 |
43300 |
42904 |
0 |
0 |
T89 |
16169 |
15488 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T8,T138,T391 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T8,T138,T391 |
1 | 1 | Covered | T8,T138,T391 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T8,T138,T391 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T8,T138,T391 |
1 | 1 | Covered | T8,T138,T391 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T8,T138,T391 |
0 |
0 |
1 |
Covered |
T8,T138,T391 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T8,T138,T391 |
0 |
0 |
1 |
Covered |
T8,T138,T391 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
121646 |
0 |
0 |
T8 |
452183 |
390 |
0 |
0 |
T72 |
26321 |
0 |
0 |
0 |
T81 |
274028 |
0 |
0 |
0 |
T90 |
64923 |
0 |
0 |
0 |
T110 |
401184 |
0 |
0 |
0 |
T138 |
0 |
5987 |
0 |
0 |
T139 |
0 |
3759 |
0 |
0 |
T140 |
0 |
3160 |
0 |
0 |
T238 |
57805 |
0 |
0 |
0 |
T390 |
0 |
397 |
0 |
0 |
T391 |
0 |
256 |
0 |
0 |
T392 |
0 |
718 |
0 |
0 |
T416 |
0 |
772 |
0 |
0 |
T417 |
0 |
787 |
0 |
0 |
T418 |
0 |
404 |
0 |
0 |
T419 |
36972 |
0 |
0 |
0 |
T420 |
67641 |
0 |
0 |
0 |
T421 |
69007 |
0 |
0 |
0 |
T422 |
59437 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1951669 |
1725930 |
0 |
0 |
T4 |
446 |
275 |
0 |
0 |
T5 |
494 |
322 |
0 |
0 |
T6 |
2872 |
2700 |
0 |
0 |
T16 |
663 |
489 |
0 |
0 |
T17 |
1227 |
1053 |
0 |
0 |
T39 |
835 |
662 |
0 |
0 |
T40 |
884 |
711 |
0 |
0 |
T41 |
1613 |
1437 |
0 |
0 |
T47 |
1126 |
954 |
0 |
0 |
T89 |
328 |
154 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
307 |
0 |
0 |
T8 |
452183 |
1 |
0 |
0 |
T72 |
26321 |
0 |
0 |
0 |
T81 |
274028 |
0 |
0 |
0 |
T90 |
64923 |
0 |
0 |
0 |
T110 |
401184 |
0 |
0 |
0 |
T138 |
0 |
15 |
0 |
0 |
T139 |
0 |
9 |
0 |
0 |
T140 |
0 |
8 |
0 |
0 |
T238 |
57805 |
0 |
0 |
0 |
T390 |
0 |
1 |
0 |
0 |
T391 |
0 |
1 |
0 |
0 |
T392 |
0 |
2 |
0 |
0 |
T416 |
0 |
2 |
0 |
0 |
T417 |
0 |
2 |
0 |
0 |
T418 |
0 |
1 |
0 |
0 |
T419 |
36972 |
0 |
0 |
0 |
T420 |
67641 |
0 |
0 |
0 |
T421 |
69007 |
0 |
0 |
0 |
T422 |
59437 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
162208507 |
0 |
0 |
T4 |
23527 |
23141 |
0 |
0 |
T5 |
26869 |
26481 |
0 |
0 |
T6 |
316536 |
316049 |
0 |
0 |
T16 |
59793 |
58878 |
0 |
0 |
T17 |
34561 |
34102 |
0 |
0 |
T39 |
54670 |
54215 |
0 |
0 |
T40 |
60759 |
60300 |
0 |
0 |
T41 |
85213 |
84571 |
0 |
0 |
T47 |
43300 |
42904 |
0 |
0 |
T89 |
16169 |
15488 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T14,T8,T138 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T14,T8,T138 |
1 | 1 | Covered | T14,T8,T138 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T14,T8,T138 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T14,T8,T138 |
1 | 1 | Covered | T14,T8,T138 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T14,T8,T138 |
0 |
0 |
1 |
Covered |
T14,T8,T138 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T14,T8,T138 |
0 |
0 |
1 |
Covered |
T14,T8,T138 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
118209 |
0 |
0 |
T8 |
0 |
366 |
0 |
0 |
T14 |
34780 |
254 |
0 |
0 |
T136 |
47633 |
0 |
0 |
0 |
T138 |
0 |
2614 |
0 |
0 |
T139 |
0 |
2937 |
0 |
0 |
T140 |
0 |
2970 |
0 |
0 |
T304 |
63585 |
0 |
0 |
0 |
T345 |
40859 |
0 |
0 |
0 |
T362 |
58764 |
0 |
0 |
0 |
T390 |
0 |
410 |
0 |
0 |
T391 |
0 |
257 |
0 |
0 |
T392 |
0 |
702 |
0 |
0 |
T416 |
0 |
778 |
0 |
0 |
T417 |
0 |
745 |
0 |
0 |
T423 |
53848 |
0 |
0 |
0 |
T424 |
139322 |
0 |
0 |
0 |
T425 |
315859 |
0 |
0 |
0 |
T426 |
11261 |
0 |
0 |
0 |
T427 |
63727 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1951669 |
1725930 |
0 |
0 |
T4 |
446 |
275 |
0 |
0 |
T5 |
494 |
322 |
0 |
0 |
T6 |
2872 |
2700 |
0 |
0 |
T16 |
663 |
489 |
0 |
0 |
T17 |
1227 |
1053 |
0 |
0 |
T39 |
835 |
662 |
0 |
0 |
T40 |
884 |
711 |
0 |
0 |
T41 |
1613 |
1437 |
0 |
0 |
T47 |
1126 |
954 |
0 |
0 |
T89 |
328 |
154 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
296 |
0 |
0 |
T8 |
0 |
1 |
0 |
0 |
T14 |
34780 |
1 |
0 |
0 |
T136 |
47633 |
0 |
0 |
0 |
T138 |
0 |
7 |
0 |
0 |
T139 |
0 |
7 |
0 |
0 |
T140 |
0 |
7 |
0 |
0 |
T304 |
63585 |
0 |
0 |
0 |
T345 |
40859 |
0 |
0 |
0 |
T362 |
58764 |
0 |
0 |
0 |
T390 |
0 |
1 |
0 |
0 |
T391 |
0 |
1 |
0 |
0 |
T392 |
0 |
2 |
0 |
0 |
T416 |
0 |
2 |
0 |
0 |
T417 |
0 |
2 |
0 |
0 |
T423 |
53848 |
0 |
0 |
0 |
T424 |
139322 |
0 |
0 |
0 |
T425 |
315859 |
0 |
0 |
0 |
T426 |
11261 |
0 |
0 |
0 |
T427 |
63727 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
162208507 |
0 |
0 |
T4 |
23527 |
23141 |
0 |
0 |
T5 |
26869 |
26481 |
0 |
0 |
T6 |
316536 |
316049 |
0 |
0 |
T16 |
59793 |
58878 |
0 |
0 |
T17 |
34561 |
34102 |
0 |
0 |
T39 |
54670 |
54215 |
0 |
0 |
T40 |
60759 |
60300 |
0 |
0 |
T41 |
85213 |
84571 |
0 |
0 |
T47 |
43300 |
42904 |
0 |
0 |
T89 |
16169 |
15488 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T8,T138,T391 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T8,T138,T391 |
1 | 1 | Covered | T8,T138,T391 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T8,T138,T391 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T8,T138,T391 |
1 | 1 | Covered | T8,T138,T391 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T8,T138,T391 |
0 |
0 |
1 |
Covered |
T8,T138,T391 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T8,T138,T391 |
0 |
0 |
1 |
Covered |
T8,T138,T391 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
126433 |
0 |
0 |
T8 |
452183 |
482 |
0 |
0 |
T72 |
26321 |
0 |
0 |
0 |
T81 |
274028 |
0 |
0 |
0 |
T90 |
64923 |
0 |
0 |
0 |
T110 |
401184 |
0 |
0 |
0 |
T138 |
0 |
3566 |
0 |
0 |
T139 |
0 |
793 |
0 |
0 |
T140 |
0 |
6316 |
0 |
0 |
T238 |
57805 |
0 |
0 |
0 |
T390 |
0 |
471 |
0 |
0 |
T391 |
0 |
338 |
0 |
0 |
T392 |
0 |
782 |
0 |
0 |
T416 |
0 |
724 |
0 |
0 |
T417 |
0 |
693 |
0 |
0 |
T418 |
0 |
407 |
0 |
0 |
T419 |
36972 |
0 |
0 |
0 |
T420 |
67641 |
0 |
0 |
0 |
T421 |
69007 |
0 |
0 |
0 |
T422 |
59437 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1951669 |
1725930 |
0 |
0 |
T4 |
446 |
275 |
0 |
0 |
T5 |
494 |
322 |
0 |
0 |
T6 |
2872 |
2700 |
0 |
0 |
T16 |
663 |
489 |
0 |
0 |
T17 |
1227 |
1053 |
0 |
0 |
T39 |
835 |
662 |
0 |
0 |
T40 |
884 |
711 |
0 |
0 |
T41 |
1613 |
1437 |
0 |
0 |
T47 |
1126 |
954 |
0 |
0 |
T89 |
328 |
154 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
317 |
0 |
0 |
T8 |
452183 |
1 |
0 |
0 |
T72 |
26321 |
0 |
0 |
0 |
T81 |
274028 |
0 |
0 |
0 |
T90 |
64923 |
0 |
0 |
0 |
T110 |
401184 |
0 |
0 |
0 |
T138 |
0 |
9 |
0 |
0 |
T139 |
0 |
2 |
0 |
0 |
T140 |
0 |
16 |
0 |
0 |
T238 |
57805 |
0 |
0 |
0 |
T390 |
0 |
1 |
0 |
0 |
T391 |
0 |
1 |
0 |
0 |
T392 |
0 |
2 |
0 |
0 |
T416 |
0 |
2 |
0 |
0 |
T417 |
0 |
2 |
0 |
0 |
T418 |
0 |
1 |
0 |
0 |
T419 |
36972 |
0 |
0 |
0 |
T420 |
67641 |
0 |
0 |
0 |
T421 |
69007 |
0 |
0 |
0 |
T422 |
59437 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
162208507 |
0 |
0 |
T4 |
23527 |
23141 |
0 |
0 |
T5 |
26869 |
26481 |
0 |
0 |
T6 |
316536 |
316049 |
0 |
0 |
T16 |
59793 |
58878 |
0 |
0 |
T17 |
34561 |
34102 |
0 |
0 |
T39 |
54670 |
54215 |
0 |
0 |
T40 |
60759 |
60300 |
0 |
0 |
T41 |
85213 |
84571 |
0 |
0 |
T47 |
43300 |
42904 |
0 |
0 |
T89 |
16169 |
15488 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T15,T8,T138 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T15,T8,T138 |
1 | 1 | Covered | T15,T8,T138 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T15,T8,T138 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T15,T8,T138 |
1 | 1 | Covered | T15,T8,T138 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T15,T8,T138 |
0 |
0 |
1 |
Covered |
T15,T8,T138 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T15,T8,T138 |
0 |
0 |
1 |
Covered |
T15,T8,T138 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
135298 |
0 |
0 |
T8 |
0 |
482 |
0 |
0 |
T14 |
34780 |
0 |
0 |
0 |
T15 |
21463 |
462 |
0 |
0 |
T91 |
55278 |
0 |
0 |
0 |
T92 |
111589 |
0 |
0 |
0 |
T93 |
46711 |
0 |
0 |
0 |
T94 |
328553 |
0 |
0 |
0 |
T95 |
84570 |
0 |
0 |
0 |
T96 |
14960 |
0 |
0 |
0 |
T97 |
93016 |
0 |
0 |
0 |
T138 |
0 |
7519 |
0 |
0 |
T139 |
0 |
2059 |
0 |
0 |
T140 |
0 |
2055 |
0 |
0 |
T390 |
0 |
473 |
0 |
0 |
T391 |
0 |
277 |
0 |
0 |
T392 |
0 |
847 |
0 |
0 |
T416 |
0 |
695 |
0 |
0 |
T417 |
0 |
666 |
0 |
0 |
T423 |
53848 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1951669 |
1725930 |
0 |
0 |
T4 |
446 |
275 |
0 |
0 |
T5 |
494 |
322 |
0 |
0 |
T6 |
2872 |
2700 |
0 |
0 |
T16 |
663 |
489 |
0 |
0 |
T17 |
1227 |
1053 |
0 |
0 |
T39 |
835 |
662 |
0 |
0 |
T40 |
884 |
711 |
0 |
0 |
T41 |
1613 |
1437 |
0 |
0 |
T47 |
1126 |
954 |
0 |
0 |
T89 |
328 |
154 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
336 |
0 |
0 |
T8 |
0 |
1 |
0 |
0 |
T14 |
34780 |
0 |
0 |
0 |
T15 |
21463 |
1 |
0 |
0 |
T91 |
55278 |
0 |
0 |
0 |
T92 |
111589 |
0 |
0 |
0 |
T93 |
46711 |
0 |
0 |
0 |
T94 |
328553 |
0 |
0 |
0 |
T95 |
84570 |
0 |
0 |
0 |
T96 |
14960 |
0 |
0 |
0 |
T97 |
93016 |
0 |
0 |
0 |
T138 |
0 |
19 |
0 |
0 |
T139 |
0 |
5 |
0 |
0 |
T140 |
0 |
5 |
0 |
0 |
T390 |
0 |
1 |
0 |
0 |
T391 |
0 |
1 |
0 |
0 |
T392 |
0 |
2 |
0 |
0 |
T416 |
0 |
2 |
0 |
0 |
T417 |
0 |
2 |
0 |
0 |
T423 |
53848 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
162208507 |
0 |
0 |
T4 |
23527 |
23141 |
0 |
0 |
T5 |
26869 |
26481 |
0 |
0 |
T6 |
316536 |
316049 |
0 |
0 |
T16 |
59793 |
58878 |
0 |
0 |
T17 |
34561 |
34102 |
0 |
0 |
T39 |
54670 |
54215 |
0 |
0 |
T40 |
60759 |
60300 |
0 |
0 |
T41 |
85213 |
84571 |
0 |
0 |
T47 |
43300 |
42904 |
0 |
0 |
T89 |
16169 |
15488 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T10,T11 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T3,T10,T11 |
1 | 1 | Covered | T3,T10,T11 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T10,T11 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T3,T10,T11 |
1 | 1 | Covered | T3,T10,T11 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T3,T10,T11 |
0 |
0 |
1 |
Covered |
T3,T10,T11 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T3,T10,T11 |
0 |
0 |
1 |
Covered |
T3,T10,T11 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
131454 |
0 |
0 |
T3 |
139731 |
659 |
0 |
0 |
T8 |
0 |
476 |
0 |
0 |
T10 |
0 |
546 |
0 |
0 |
T11 |
0 |
691 |
0 |
0 |
T24 |
112487 |
0 |
0 |
0 |
T27 |
239098 |
0 |
0 |
0 |
T57 |
43818 |
0 |
0 |
0 |
T65 |
52488 |
0 |
0 |
0 |
T66 |
11071 |
0 |
0 |
0 |
T98 |
0 |
287 |
0 |
0 |
T99 |
0 |
377 |
0 |
0 |
T100 |
0 |
355 |
0 |
0 |
T410 |
315432 |
0 |
0 |
0 |
T415 |
0 |
246 |
0 |
0 |
T429 |
0 |
378 |
0 |
0 |
T430 |
0 |
394 |
0 |
0 |
T431 |
24345 |
0 |
0 |
0 |
T432 |
34410 |
0 |
0 |
0 |
T433 |
38857 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1951669 |
1725930 |
0 |
0 |
T4 |
446 |
275 |
0 |
0 |
T5 |
494 |
322 |
0 |
0 |
T6 |
2872 |
2700 |
0 |
0 |
T16 |
663 |
489 |
0 |
0 |
T17 |
1227 |
1053 |
0 |
0 |
T39 |
835 |
662 |
0 |
0 |
T40 |
884 |
711 |
0 |
0 |
T41 |
1613 |
1437 |
0 |
0 |
T47 |
1126 |
954 |
0 |
0 |
T89 |
328 |
154 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
331 |
0 |
0 |
T3 |
139731 |
2 |
0 |
0 |
T8 |
0 |
1 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T24 |
112487 |
0 |
0 |
0 |
T27 |
239098 |
0 |
0 |
0 |
T57 |
43818 |
0 |
0 |
0 |
T65 |
52488 |
0 |
0 |
0 |
T66 |
11071 |
0 |
0 |
0 |
T98 |
0 |
1 |
0 |
0 |
T99 |
0 |
1 |
0 |
0 |
T100 |
0 |
1 |
0 |
0 |
T410 |
315432 |
0 |
0 |
0 |
T415 |
0 |
1 |
0 |
0 |
T429 |
0 |
1 |
0 |
0 |
T430 |
0 |
1 |
0 |
0 |
T431 |
24345 |
0 |
0 |
0 |
T432 |
34410 |
0 |
0 |
0 |
T433 |
38857 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
162208507 |
0 |
0 |
T4 |
23527 |
23141 |
0 |
0 |
T5 |
26869 |
26481 |
0 |
0 |
T6 |
316536 |
316049 |
0 |
0 |
T16 |
59793 |
58878 |
0 |
0 |
T17 |
34561 |
34102 |
0 |
0 |
T39 |
54670 |
54215 |
0 |
0 |
T40 |
60759 |
60300 |
0 |
0 |
T41 |
85213 |
84571 |
0 |
0 |
T47 |
43300 |
42904 |
0 |
0 |
T89 |
16169 |
15488 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T8,T138,T391 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T8,T138,T391 |
1 | 1 | Covered | T8,T138,T391 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T8,T138,T391 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T8,T138,T391 |
1 | 1 | Covered | T8,T138,T391 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T8,T138,T391 |
0 |
0 |
1 |
Covered |
T8,T138,T391 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T8,T138,T391 |
0 |
0 |
1 |
Covered |
T8,T138,T391 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
124302 |
0 |
0 |
T8 |
452183 |
474 |
0 |
0 |
T72 |
26321 |
0 |
0 |
0 |
T81 |
274028 |
0 |
0 |
0 |
T90 |
64923 |
0 |
0 |
0 |
T110 |
401184 |
0 |
0 |
0 |
T138 |
0 |
4390 |
0 |
0 |
T139 |
0 |
2419 |
0 |
0 |
T140 |
0 |
1522 |
0 |
0 |
T238 |
57805 |
0 |
0 |
0 |
T390 |
0 |
404 |
0 |
0 |
T391 |
0 |
304 |
0 |
0 |
T392 |
0 |
699 |
0 |
0 |
T416 |
0 |
801 |
0 |
0 |
T417 |
0 |
773 |
0 |
0 |
T418 |
0 |
389 |
0 |
0 |
T419 |
36972 |
0 |
0 |
0 |
T420 |
67641 |
0 |
0 |
0 |
T421 |
69007 |
0 |
0 |
0 |
T422 |
59437 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1951669 |
1725930 |
0 |
0 |
T4 |
446 |
275 |
0 |
0 |
T5 |
494 |
322 |
0 |
0 |
T6 |
2872 |
2700 |
0 |
0 |
T16 |
663 |
489 |
0 |
0 |
T17 |
1227 |
1053 |
0 |
0 |
T39 |
835 |
662 |
0 |
0 |
T40 |
884 |
711 |
0 |
0 |
T41 |
1613 |
1437 |
0 |
0 |
T47 |
1126 |
954 |
0 |
0 |
T89 |
328 |
154 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
312 |
0 |
0 |
T8 |
452183 |
1 |
0 |
0 |
T72 |
26321 |
0 |
0 |
0 |
T81 |
274028 |
0 |
0 |
0 |
T90 |
64923 |
0 |
0 |
0 |
T110 |
401184 |
0 |
0 |
0 |
T138 |
0 |
11 |
0 |
0 |
T139 |
0 |
6 |
0 |
0 |
T140 |
0 |
4 |
0 |
0 |
T238 |
57805 |
0 |
0 |
0 |
T390 |
0 |
1 |
0 |
0 |
T391 |
0 |
1 |
0 |
0 |
T392 |
0 |
2 |
0 |
0 |
T416 |
0 |
2 |
0 |
0 |
T417 |
0 |
2 |
0 |
0 |
T418 |
0 |
1 |
0 |
0 |
T419 |
36972 |
0 |
0 |
0 |
T420 |
67641 |
0 |
0 |
0 |
T421 |
69007 |
0 |
0 |
0 |
T422 |
59437 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
162208507 |
0 |
0 |
T4 |
23527 |
23141 |
0 |
0 |
T5 |
26869 |
26481 |
0 |
0 |
T6 |
316536 |
316049 |
0 |
0 |
T16 |
59793 |
58878 |
0 |
0 |
T17 |
34561 |
34102 |
0 |
0 |
T39 |
54670 |
54215 |
0 |
0 |
T40 |
60759 |
60300 |
0 |
0 |
T41 |
85213 |
84571 |
0 |
0 |
T47 |
43300 |
42904 |
0 |
0 |
T89 |
16169 |
15488 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T8,T138,T391 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T8,T138,T391 |
1 | 1 | Covered | T8,T138,T391 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T8,T138,T391 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T8,T138,T391 |
1 | 1 | Covered | T8,T138,T391 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T8,T138,T391 |
0 |
0 |
1 |
Covered |
T8,T138,T391 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T8,T138,T391 |
0 |
0 |
1 |
Covered |
T8,T138,T391 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
116552 |
0 |
0 |
T8 |
452183 |
383 |
0 |
0 |
T72 |
26321 |
0 |
0 |
0 |
T81 |
274028 |
0 |
0 |
0 |
T90 |
64923 |
0 |
0 |
0 |
T110 |
401184 |
0 |
0 |
0 |
T138 |
0 |
2175 |
0 |
0 |
T139 |
0 |
260 |
0 |
0 |
T140 |
0 |
6785 |
0 |
0 |
T238 |
57805 |
0 |
0 |
0 |
T390 |
0 |
405 |
0 |
0 |
T391 |
0 |
253 |
0 |
0 |
T392 |
0 |
767 |
0 |
0 |
T416 |
0 |
771 |
0 |
0 |
T417 |
0 |
693 |
0 |
0 |
T418 |
0 |
464 |
0 |
0 |
T419 |
36972 |
0 |
0 |
0 |
T420 |
67641 |
0 |
0 |
0 |
T421 |
69007 |
0 |
0 |
0 |
T422 |
59437 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1951669 |
1725930 |
0 |
0 |
T4 |
446 |
275 |
0 |
0 |
T5 |
494 |
322 |
0 |
0 |
T6 |
2872 |
2700 |
0 |
0 |
T16 |
663 |
489 |
0 |
0 |
T17 |
1227 |
1053 |
0 |
0 |
T39 |
835 |
662 |
0 |
0 |
T40 |
884 |
711 |
0 |
0 |
T41 |
1613 |
1437 |
0 |
0 |
T47 |
1126 |
954 |
0 |
0 |
T89 |
328 |
154 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
295 |
0 |
0 |
T8 |
452183 |
1 |
0 |
0 |
T72 |
26321 |
0 |
0 |
0 |
T81 |
274028 |
0 |
0 |
0 |
T90 |
64923 |
0 |
0 |
0 |
T110 |
401184 |
0 |
0 |
0 |
T138 |
0 |
6 |
0 |
0 |
T139 |
0 |
1 |
0 |
0 |
T140 |
0 |
17 |
0 |
0 |
T238 |
57805 |
0 |
0 |
0 |
T390 |
0 |
1 |
0 |
0 |
T391 |
0 |
1 |
0 |
0 |
T392 |
0 |
2 |
0 |
0 |
T416 |
0 |
2 |
0 |
0 |
T417 |
0 |
2 |
0 |
0 |
T418 |
0 |
1 |
0 |
0 |
T419 |
36972 |
0 |
0 |
0 |
T420 |
67641 |
0 |
0 |
0 |
T421 |
69007 |
0 |
0 |
0 |
T422 |
59437 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
162208507 |
0 |
0 |
T4 |
23527 |
23141 |
0 |
0 |
T5 |
26869 |
26481 |
0 |
0 |
T6 |
316536 |
316049 |
0 |
0 |
T16 |
59793 |
58878 |
0 |
0 |
T17 |
34561 |
34102 |
0 |
0 |
T39 |
54670 |
54215 |
0 |
0 |
T40 |
60759 |
60300 |
0 |
0 |
T41 |
85213 |
84571 |
0 |
0 |
T47 |
43300 |
42904 |
0 |
0 |
T89 |
16169 |
15488 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T8,T138,T391 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T8,T138,T391 |
1 | 1 | Covered | T8,T138,T391 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T8,T138,T391 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T8,T138,T391 |
1 | 1 | Covered | T8,T138,T391 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T8,T138,T391 |
0 |
0 |
1 |
Covered |
T8,T138,T391 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T8,T138,T391 |
0 |
0 |
1 |
Covered |
T8,T138,T391 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
133680 |
0 |
0 |
T8 |
452183 |
402 |
0 |
0 |
T72 |
26321 |
0 |
0 |
0 |
T81 |
274028 |
0 |
0 |
0 |
T90 |
64923 |
0 |
0 |
0 |
T110 |
401184 |
0 |
0 |
0 |
T138 |
0 |
7103 |
0 |
0 |
T139 |
0 |
3311 |
0 |
0 |
T140 |
0 |
7494 |
0 |
0 |
T238 |
57805 |
0 |
0 |
0 |
T390 |
0 |
468 |
0 |
0 |
T391 |
0 |
249 |
0 |
0 |
T392 |
0 |
812 |
0 |
0 |
T416 |
0 |
695 |
0 |
0 |
T417 |
0 |
671 |
0 |
0 |
T418 |
0 |
418 |
0 |
0 |
T419 |
36972 |
0 |
0 |
0 |
T420 |
67641 |
0 |
0 |
0 |
T421 |
69007 |
0 |
0 |
0 |
T422 |
59437 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1951669 |
1725930 |
0 |
0 |
T4 |
446 |
275 |
0 |
0 |
T5 |
494 |
322 |
0 |
0 |
T6 |
2872 |
2700 |
0 |
0 |
T16 |
663 |
489 |
0 |
0 |
T17 |
1227 |
1053 |
0 |
0 |
T39 |
835 |
662 |
0 |
0 |
T40 |
884 |
711 |
0 |
0 |
T41 |
1613 |
1437 |
0 |
0 |
T47 |
1126 |
954 |
0 |
0 |
T89 |
328 |
154 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
333 |
0 |
0 |
T8 |
452183 |
1 |
0 |
0 |
T72 |
26321 |
0 |
0 |
0 |
T81 |
274028 |
0 |
0 |
0 |
T90 |
64923 |
0 |
0 |
0 |
T110 |
401184 |
0 |
0 |
0 |
T138 |
0 |
18 |
0 |
0 |
T139 |
0 |
8 |
0 |
0 |
T140 |
0 |
19 |
0 |
0 |
T238 |
57805 |
0 |
0 |
0 |
T390 |
0 |
1 |
0 |
0 |
T391 |
0 |
1 |
0 |
0 |
T392 |
0 |
2 |
0 |
0 |
T416 |
0 |
2 |
0 |
0 |
T417 |
0 |
2 |
0 |
0 |
T418 |
0 |
1 |
0 |
0 |
T419 |
36972 |
0 |
0 |
0 |
T420 |
67641 |
0 |
0 |
0 |
T421 |
69007 |
0 |
0 |
0 |
T422 |
59437 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
162208507 |
0 |
0 |
T4 |
23527 |
23141 |
0 |
0 |
T5 |
26869 |
26481 |
0 |
0 |
T6 |
316536 |
316049 |
0 |
0 |
T16 |
59793 |
58878 |
0 |
0 |
T17 |
34561 |
34102 |
0 |
0 |
T39 |
54670 |
54215 |
0 |
0 |
T40 |
60759 |
60300 |
0 |
0 |
T41 |
85213 |
84571 |
0 |
0 |
T47 |
43300 |
42904 |
0 |
0 |
T89 |
16169 |
15488 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T7,T8,T9 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T7,T8,T9 |
1 | 1 | Covered | T7,T8,T9 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T7,T8,T9 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T7,T8,T9 |
1 | 1 | Covered | T7,T8,T9 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T7,T8,T9 |
0 |
0 |
1 |
Covered |
T7,T8,T9 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T7,T8,T9 |
0 |
0 |
1 |
Covered |
T7,T8,T9 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
125161 |
0 |
0 |
T7 |
31427 |
300 |
0 |
0 |
T8 |
0 |
426 |
0 |
0 |
T9 |
0 |
454 |
0 |
0 |
T126 |
75932 |
0 |
0 |
0 |
T138 |
0 |
2667 |
0 |
0 |
T139 |
0 |
3675 |
0 |
0 |
T140 |
0 |
4495 |
0 |
0 |
T160 |
43036 |
0 |
0 |
0 |
T255 |
171712 |
0 |
0 |
0 |
T270 |
300741 |
0 |
0 |
0 |
T322 |
62222 |
0 |
0 |
0 |
T327 |
73931 |
0 |
0 |
0 |
T390 |
0 |
469 |
0 |
0 |
T391 |
0 |
261 |
0 |
0 |
T392 |
0 |
813 |
0 |
0 |
T434 |
0 |
260 |
0 |
0 |
T435 |
42720 |
0 |
0 |
0 |
T436 |
268320 |
0 |
0 |
0 |
T437 |
26620 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1951669 |
1725930 |
0 |
0 |
T4 |
446 |
275 |
0 |
0 |
T5 |
494 |
322 |
0 |
0 |
T6 |
2872 |
2700 |
0 |
0 |
T16 |
663 |
489 |
0 |
0 |
T17 |
1227 |
1053 |
0 |
0 |
T39 |
835 |
662 |
0 |
0 |
T40 |
884 |
711 |
0 |
0 |
T41 |
1613 |
1437 |
0 |
0 |
T47 |
1126 |
954 |
0 |
0 |
T89 |
328 |
154 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
314 |
0 |
0 |
T7 |
31427 |
1 |
0 |
0 |
T8 |
0 |
1 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T126 |
75932 |
0 |
0 |
0 |
T138 |
0 |
7 |
0 |
0 |
T139 |
0 |
9 |
0 |
0 |
T140 |
0 |
11 |
0 |
0 |
T160 |
43036 |
0 |
0 |
0 |
T255 |
171712 |
0 |
0 |
0 |
T270 |
300741 |
0 |
0 |
0 |
T322 |
62222 |
0 |
0 |
0 |
T327 |
73931 |
0 |
0 |
0 |
T390 |
0 |
1 |
0 |
0 |
T391 |
0 |
1 |
0 |
0 |
T392 |
0 |
2 |
0 |
0 |
T434 |
0 |
1 |
0 |
0 |
T435 |
42720 |
0 |
0 |
0 |
T436 |
268320 |
0 |
0 |
0 |
T437 |
26620 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163029454 |
162208507 |
0 |
0 |
T4 |
23527 |
23141 |
0 |
0 |
T5 |
26869 |
26481 |
0 |
0 |
T6 |
316536 |
316049 |
0 |
0 |
T16 |
59793 |
58878 |
0 |
0 |
T17 |
34561 |
34102 |
0 |
0 |
T39 |
54670 |
54215 |
0 |
0 |
T40 |
60759 |
60300 |
0 |
0 |
T41 |
85213 |
84571 |
0 |
0 |
T47 |
43300 |
42904 |
0 |
0 |
T89 |
16169 |
15488 |
0 |
0 |