Module Definition
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Module : prim_generic_buf
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_prim_usb_diff_rx.gen_generic.u_impl_generic.obs_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[2].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[2].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[2].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[2].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[3].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[3].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[3].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_buffs[3].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[2].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[2].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[2].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[2].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[3].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[3].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[3].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_buffs[3].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_buffs[2].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_buffs[2].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_buffs[2].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_buffs[2].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_pinmux_jtag_buf_lc.prim_buf_trst_n.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_pinmux_jtag_buf_lc.prim_buf_tms.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_pinmux_jtag_buf_lc.prim_buf_tdi.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_pinmux_jtag_buf_lc.prim_buf_tdo.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_pinmux_jtag_buf_lc.prim_buf_tdo_oe.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_pinmux_jtag_buf_rv.prim_buf_trst_n.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_pinmux_jtag_buf_rv.prim_buf_tms.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_pinmux_jtag_buf_rv.prim_buf_tdi.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_pinmux_jtag_buf_rv.prim_buf_tdo.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_pinmux_jtag_buf_rv.prim_buf_tdo_oe.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_pinmux_jtag_buf_dft.prim_buf_trst_n.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_pinmux_jtag_buf_dft.prim_buf_tms.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_pinmux_jtag_buf_dft.prim_buf_tdi.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_pinmux_jtag_buf_dft.prim_buf_tdo.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_pinmux_jtag_buf_dft.prim_buf_tdo_oe.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_prim_sec_anchor_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_sensor_ctrl_aon.gen_alert_sync_assign[0].u_alert_in_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_sensor_ctrl_aon.gen_alert_sync_assign[1].u_alert_in_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_sensor_ctrl_aon.gen_alert_sync_assign[2].u_alert_in_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_sensor_ctrl_aon.gen_alert_sync_assign[3].u_alert_in_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_sensor_ctrl_aon.gen_alert_sync_assign[4].u_alert_in_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_sensor_ctrl_aon.gen_alert_sync_assign[5].u_alert_in_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_sensor_ctrl_aon.gen_alert_sync_assign[6].u_alert_in_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_sensor_ctrl_aon.gen_alert_sync_assign[7].u_alert_in_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_sensor_ctrl_aon.gen_alert_sync_assign[8].u_alert_in_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_sensor_ctrl_aon.gen_alert_sync_assign[9].u_alert_in_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_sensor_ctrl_aon.gen_alert_sync_assign[10].u_alert_in_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_buf_irq.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_core_sleeping_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_tlul_req_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_tlul_rsp_buf.gen_generic.u_impl_generic 100.00 100.00

Line Coverage for Module : prim_generic_buf
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
15 1 1
16 1 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%