Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_edn1.u_edn_core.u_prim_mubi4_sync_edn_enable.gen_buffs[15].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_buf_irq.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_core_sleeping_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_core_sleeping_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_tlul_req_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_tlul_req_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_tlul_rsp_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_tlul_rsp_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_buf_irq.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_core_sleeping_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_tlul_req_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_tlul_rsp_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' or '../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
15	1	1
16	1	1