Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sram_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.94 97.94

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_sram_ctrl_ret_aon 99.64 99.64
tb.dut.top_earlgrey.u_sram_ctrl_main 99.65 99.65


Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.64 99.64


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.64 99.64


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_main

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.65 99.65


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.65 99.65


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : sram_ctrl
TotalCoveredPercent
Totals 66 60 90.91
Total Bits 1164 1140 97.94
Total Bits 0->1 582 570 97.94
Total Bits 1->0 582 570 97.94

Ports 66 60 90.91
Port Bits 1164 1140 97.94
Port Bits 0->1 582 570 97.94
Port Bits 1->0 582 570 97.94

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T5,T6 Yes T1,T2,T3 INPUT
clk_otp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_otp_ni Yes Yes T3,T5,T6 Yes T1,T2,T3 INPUT
ram_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[16:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 INPUT
ram_tl_i.a_address[20:17] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[22:21] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
ram_tl_i.a_address[27:23] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[28] Yes Yes *T1,*T2,*T4 Yes T1,T2,T4 INPUT
ram_tl_i.a_address[29] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[5:0] Yes Yes *T1,*T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_valid Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
ram_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_error Yes Yes T1,T2,T3 Yes T3,T5,T6 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
ram_tl_o.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
ram_tl_o.d_sink Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
ram_tl_o.d_source[5:0] Yes Yes *T1,*T2,*T4 Yes T1,T2,T4 OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T1,*T2,*T4 Yes T1,T2,T4 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
regs_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T44,T45,T296 Yes T44,T45,T296 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T44,T45,T296 Yes T44,T45,T296 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[5:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 INPUT
regs_tl_i.a_address[17:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20:18] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[23] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[24] Yes Yes *T44,*T45,*T296 Yes T44,T45,T296 INPUT
regs_tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes T3,*T68,*T75 Yes T3,T68,T75 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[2:0] Yes Yes T3,T68,T76 Yes T3,T68,T76 INPUT
regs_tl_i.a_valid Yes Yes T44,T45,T296 Yes T44,T45,T296 INPUT
regs_tl_o.a_ready Yes Yes T44,T45,T296 Yes T44,T45,T296 OUTPUT
regs_tl_o.d_error Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
regs_tl_o.d_user.data_intg[6:0] Yes Yes T205,T206,T208 Yes T205,T206,T208 OUTPUT
regs_tl_o.d_user.rsp_intg[6:0] Yes Yes T205,T206,T41 Yes T44,T45,T46 OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T205,T206,T41 Yes T44,T45,T46 OUTPUT
regs_tl_o.d_sink Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
regs_tl_o.d_source[5:0] Yes Yes *T47,*T72,*T73 Yes T47,T448,T449 OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T205,*T206,*T208 Yes T296,T205,T206 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T44,T45,T296 Yes T44,T45,T296 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T48,T78,T47 Yes T48,T78,T47 INPUT
alert_rx_i[0].ping_n Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
alert_rx_i[0].ping_p Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T48,T78,T47 Yes T48,T78,T47 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T5,T62,T63 Yes T5,T62,T63 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T3,T5,T6 Yes T1,T2,T3 INPUT
otp_en_sram_ifetch_i[7:0] Yes Yes T1,T2,T3 Yes T3,T5,T6 INPUT
sram_otp_key_o.req Yes Yes T44,T45,T46 Yes T44,T45,T46 OUTPUT
sram_otp_key_i.seed_valid Yes Yes T5,T6,T62 Yes T1,T2,T4 INPUT
sram_otp_key_i.nonce[127:0] Yes Yes T6,T81,T82 Yes T2,T6,T81 INPUT
sram_otp_key_i.key[127:0] Yes Yes T2,T5,T6 Yes T5,T6,T82 INPUT
sram_otp_key_i.ack Yes Yes T44,T45,T46 Yes T44,T45,T46 INPUT
cfg_i.rf_cfg.cfg[3:0] No No No INPUT
cfg_i.rf_cfg.cfg_en No No No INPUT
cfg_i.rf_cfg.test No No No INPUT
cfg_i.ram_cfg.cfg[3:0] No No No INPUT
cfg_i.ram_cfg.cfg_en No No No INPUT
cfg_i.ram_cfg.test No No No INPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon
TotalCoveredPercent
Totals 60 58 96.67
Total Bits 1102 1098 99.64
Total Bits 0->1 551 549 99.64
Total Bits 1->0 551 549 99.64

Ports 60 58 96.67
Port Bits 1102 1098 99.64
Port Bits 0->1 551 549 99.64
Port Bits 1->0 551 549 99.64

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T5,T6 Yes T1,T2,T3 INPUT
clk_otp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_otp_ni Yes Yes T3,T5,T6 Yes T1,T2,T3 INPUT
ram_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T5,T44,T62 Yes T5,T44,T62 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[11:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 INPUT
ram_tl_i.a_address[20:12] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[22:21] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
ram_tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[5:0] Yes Yes T3,*T68,*T75 Yes T3,T68,T75 INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[2:0] Yes Yes T3,T68,T76 Yes T3,T68,T76 INPUT
ram_tl_i.a_valid Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
ram_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_error Yes Yes T1,T2,T3 Yes T3,T5,T6 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T5,T44,T62 Yes T5,T44,T62 OUTPUT
ram_tl_o.d_user.rsp_intg[6:0] Yes Yes T3,T5,T6 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T5,T44,T62 Yes T5,T44,T62 OUTPUT
ram_tl_o.d_sink Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
ram_tl_o.d_source[5:0] Yes Yes *T68,*T76,*T163 Yes T68,T76,T163 OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T1,*T2,*T4 Yes T1,T2,T4 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
regs_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T44,T45,T296 Yes T44,T45,T296 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T44,T45,T296 Yes T44,T45,T296 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[5:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 INPUT
regs_tl_i.a_address[19:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes T3,*T68,*T75 Yes T3,T68,T75 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[2:0] Yes Yes T3,T68,T76 Yes T3,T68,T76 INPUT
regs_tl_i.a_valid Yes Yes T44,T45,T296 Yes T44,T45,T296 INPUT
regs_tl_o.a_ready Yes Yes T44,T45,T296 Yes T44,T45,T296 OUTPUT
regs_tl_o.d_error Yes Yes T72,T74,T178 Yes T72,T73,T178 OUTPUT
regs_tl_o.d_user.data_intg[6:0] Yes Yes T205,T206,T207 Yes T205,T206,T207 OUTPUT
regs_tl_o.d_user.rsp_intg[6:0] Yes Yes T205,T206,T41 Yes T44,T45,T46 OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T205,T206,T41 Yes T44,T45,T46 OUTPUT
regs_tl_o.d_sink Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
regs_tl_o.d_source[5:0] Yes Yes *T47,*T72,*T73 Yes T47,T72,T73 OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T205,*T206,*T207 Yes T296,T205,T206 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T44,T45,T296 Yes T44,T45,T296 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T48,T78,T47 Yes T48,T78,T47 INPUT
alert_rx_i[0].ping_n Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
alert_rx_i[0].ping_p Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T48,T78,T47 Yes T48,T78,T47 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T5,T62,T63 Yes T5,T62,T63 INPUT
lc_hw_debug_en_i[3:0] Unreachable Unreachable Unreachable INPUT
otp_en_sram_ifetch_i[7:0] Unreachable Unreachable Unreachable INPUT
sram_otp_key_o.req Yes Yes T205,T206,T207 Yes T205,T206,T207 OUTPUT
sram_otp_key_i.seed_valid Yes Yes T5,T6,T62 Yes T1,T2,T4 INPUT
sram_otp_key_i.nonce[127:0] Yes Yes T6,T81,T82 Yes T2,T6,T81 INPUT
sram_otp_key_i.key[127:0] Yes Yes T2,T5,T6 Yes T5,T6,T82 INPUT
sram_otp_key_i.ack Yes Yes T205,T206,T207 Yes T205,T206,T207 INPUT
cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.test No No No INPUT
cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.test No No No INPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_main
TotalCoveredPercent
Totals 62 60 96.77
Total Bits 1136 1132 99.65
Total Bits 0->1 568 566 99.65
Total Bits 1->0 568 566 99.65

Ports 62 60 96.77
Port Bits 1136 1132 99.65
Port Bits 0->1 568 566 99.65
Port Bits 1->0 568 566 99.65

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T5,T6 Yes T1,T2,T3 INPUT
clk_otp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_otp_ni Yes Yes T3,T5,T6 Yes T1,T2,T3 INPUT
ram_tl_i.d_ready Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
ram_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
ram_tl_i.a_address[16:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 INPUT
ram_tl_i.a_address[27:17] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[28] Yes Yes *T1,*T2,*T4 Yes T1,T2,T4 INPUT
ram_tl_i.a_address[31:29] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[5:0] Yes Yes *T1,*T2,*T4 Yes T1,T2,T4 INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[2:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
ram_tl_i.a_valid Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
ram_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_error Yes Yes T1,T2,T3 Yes T3,T5,T6 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
ram_tl_o.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
ram_tl_o.d_sink Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
ram_tl_o.d_source[5:0] Yes Yes *T1,*T2,*T4 Yes T1,T2,T4 OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T1,*T2,*T4 Yes T1,T2,T4 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
regs_tl_i.d_ready Yes Yes T3,T5,T6 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T44,T45,T46 Yes T44,T45,T46 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T44,T45,T296 Yes T44,T45,T296 INPUT
regs_tl_i.a_user.instr_type[3:0] Yes Yes T44,T45,T296 Yes T44,T45,T296 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T44,T45,T46 Yes T44,T45,T46 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T44,T45,T296 Yes T44,T45,T296 INPUT
regs_tl_i.a_address[5:0] Yes Yes *T72,*T74,*T214 Yes T72,T74,T214 INPUT
regs_tl_i.a_address[17:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20:18] Yes Yes T44,T45,T296 Yes T44,T45,T296 INPUT
regs_tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[24] Yes Yes *T44,*T45,*T296 Yes T44,T45,T296 INPUT
regs_tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T44,*T45,*T296 Yes T44,T45,T296 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes *T47,*T448,*T449 Yes T47,T448,T449 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[2:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 INPUT
regs_tl_i.a_valid Yes Yes T44,T45,T296 Yes T44,T45,T296 INPUT
regs_tl_o.a_ready Yes Yes T44,T45,T296 Yes T44,T45,T296 OUTPUT
regs_tl_o.d_error Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
regs_tl_o.d_user.data_intg[6:0] Yes Yes T208,T209,T47 Yes T208,T209,T47 OUTPUT
regs_tl_o.d_user.rsp_intg[6:0] Yes Yes T41,T42,T208 Yes T44,T45,T46 OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T41,T42,T208 Yes T44,T45,T46 OUTPUT
regs_tl_o.d_sink Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
regs_tl_o.d_source[5:0] Yes Yes *T47,*T72,*T73 Yes T47,T448,T449 OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T208,*T209,*T207 Yes T296,T450,T208 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T44,T45,T296 Yes T44,T45,T296 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T48,T78,T47 Yes T48,T78,T47 INPUT
alert_rx_i[0].ping_n Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
alert_rx_i[0].ping_p Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T48,T78,T47 Yes T48,T78,T47 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T5,T62,T63 Yes T5,T62,T63 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T3,T5,T6 Yes T1,T2,T3 INPUT
otp_en_sram_ifetch_i[7:0] Yes Yes T1,T2,T3 Yes T3,T5,T6 INPUT
sram_otp_key_o.req Yes Yes T44,T45,T46 Yes T44,T45,T46 OUTPUT
sram_otp_key_i.seed_valid Yes Yes T5,T6,T62 Yes T1,T2,T4 INPUT
sram_otp_key_i.nonce[127:0] Yes Yes T6,T81,T82 Yes T2,T6,T81 INPUT
sram_otp_key_i.key[127:0] Yes Yes T2,T5,T6 Yes T5,T6,T82 INPUT
sram_otp_key_i.ack Yes Yes T44,T45,T46 Yes T44,T45,T46 INPUT
cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.test No No No INPUT
cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.test No No No INPUT

*Tests covering at least one bit in the range
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