Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T3,T44,T63	Yes	T3,T44,T63	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T3,T44,T63	Yes	T3,T44,T63	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T3,*T68,*T75	Yes	T3,T68,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T3,T68,T76	Yes	T3,T68,T76	INPUT
tl_i.a_valid	Yes	Yes	T3,T44,T63	Yes	T3,T44,T63	INPUT
tl_o.a_ready	Yes	Yes	T3,T44,T45	Yes	T3,T44,T45	OUTPUT
tl_o.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T44,T45	Yes	T3,T44,T45	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T3,T44,T45	Yes	T3,T44,T45	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T3,T44,T45	Yes	T3,T44,T45	OUTPUT
tl_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T3,*T724,*T730	Yes	T3,T724,T730	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T3,*T44,*T45	Yes	T3,T44,T45	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T3,T44,T45	Yes	T3,T44,T45	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T731,T350	Yes	T3,T731,T350	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T254,T78,T187	Yes	T254,T78,T187	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T254,T78,T187	Yes	T254,T78,T187	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T731,T350	Yes	T3,T731,T350	OUTPUT
cio_rx_i	Yes	Yes	T5,T6,T7	Yes	T1,T2,T4	INPUT
cio_tx_o	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T3,T99,T100	Yes	T3,T99,T100	OUTPUT
intr_tx_empty_o	Yes	Yes	T3,T99,T100	Yes	T3,T99,T100	OUTPUT
intr_rx_watermark_o	Yes	Yes	T99,T100,T101	Yes	T99,T100,T101	OUTPUT
intr_tx_done_o	Yes	Yes	T99,T100,T101	Yes	T99,T100,T101	OUTPUT
intr_rx_overflow_o	Yes	Yes	T99,T100,T101	Yes	T99,T100,T101	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T101,T305,T315	Yes	T101,T305,T315	OUTPUT
intr_rx_break_err_o	Yes	Yes	T101,T305,T315	Yes	T101,T305,T315	OUTPUT
intr_rx_timeout_o	Yes	Yes	T101,T305,T315	Yes	T101,T305,T315	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T101,T305,T315	Yes	T101,T305,T315	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T3,T44,T63	Yes	T3,T44,T63	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T3,T44,T63	Yes	T3,T44,T63	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T3,*T68,*T75	Yes	T3,T68,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T3,T68,T76	Yes	T3,T68,T76	INPUT
tl_i.a_valid	Yes	Yes	T3,T44,T63	Yes	T3,T44,T63	INPUT
tl_o.a_ready	Yes	Yes	T3,T44,T45	Yes	T3,T44,T45	OUTPUT
tl_o.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T44,T45	Yes	T3,T44,T45	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T3,T44,T45	Yes	T3,T44,T45	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T3,T44,T45	Yes	T3,T44,T45	OUTPUT
tl_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T3,*T724,*T730	Yes	T3,T724,T730	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T3,*T44,*T45	Yes	T3,T44,T45	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T3,T44,T45	Yes	T3,T44,T45	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T48,T254,T190	Yes	T48,T254,T190	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T321,T79	Yes	T78,T321,T79	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T321,T79	Yes	T78,T321,T79	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T48,T254,T190	Yes	T48,T254,T190	OUTPUT
cio_rx_i	Yes	Yes	T5,T6,T7	Yes	T1,T2,T4	INPUT
cio_tx_o	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T3,T101,T305	Yes	T3,T101,T305	OUTPUT
intr_tx_empty_o	Yes	Yes	T101,T305,T315	Yes	T101,T305,T315	OUTPUT
intr_rx_watermark_o	Yes	Yes	T101,T305,T315	Yes	T101,T305,T315	OUTPUT
intr_tx_done_o	Yes	Yes	T101,T305,T315	Yes	T101,T305,T315	OUTPUT
intr_rx_overflow_o	Yes	Yes	T101,T305,T315	Yes	T101,T305,T315	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T101,T305,T315	Yes	T101,T305,T315	OUTPUT
intr_rx_break_err_o	Yes	Yes	T101,T305,T315	Yes	T101,T305,T315	OUTPUT
intr_rx_timeout_o	Yes	Yes	T101,T305,T315	Yes	T101,T305,T315	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T101,T305,T315	Yes	T101,T305,T315	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T3,T99,T101	Yes	T3,T99,T101	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T3,T99,T101	Yes	T3,T99,T101	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T3,*T68,*T75	Yes	T3,T68,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T3,T68,T76	Yes	T3,T68,T76	INPUT
tl_i.a_valid	Yes	Yes	T3,T99,T101	Yes	T3,T99,T101	INPUT
tl_o.a_ready	Yes	Yes	T3,T99,T101	Yes	T3,T99,T101	OUTPUT
tl_o.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T99,T101	Yes	T3,T99,T101	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T3,T99,T101	Yes	T3,T99,T101	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T3,T99,T101	Yes	T3,T99,T101	OUTPUT
tl_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T3,*T164,*T72	Yes	T3,T164,T72	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T74,T178	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T3,*T99,*T101	Yes	T3,T99,T101	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T3,T99,T101	Yes	T3,T99,T101	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T731,T48,T732	Yes	T731,T48,T732	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T254,T78,T187	Yes	T254,T78,T187	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T254,T78,T187	Yes	T254,T78,T187	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T731,T48,T732	Yes	T731,T48,T732	OUTPUT
cio_rx_i	Yes	Yes	T32,T99,T329	Yes	T32,T8,T99	INPUT
cio_tx_o	Yes	Yes	T99,T329,T353	Yes	T99,T329,T353	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T99,T101,T305	Yes	T99,T101,T305	OUTPUT
intr_tx_empty_o	Yes	Yes	T3,T99,T101	Yes	T3,T99,T101	OUTPUT
intr_rx_watermark_o	Yes	Yes	T99,T101,T305	Yes	T99,T101,T305	OUTPUT
intr_tx_done_o	Yes	Yes	T99,T101,T305	Yes	T99,T101,T305	OUTPUT
intr_rx_overflow_o	Yes	Yes	T99,T101,T305	Yes	T99,T101,T305	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T101,T305,T315	Yes	T101,T305,T315	OUTPUT
intr_rx_break_err_o	Yes	Yes	T101,T305,T315	Yes	T101,T305,T315	OUTPUT
intr_rx_timeout_o	Yes	Yes	T101,T305,T315	Yes	T101,T305,T315	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T101,T305,T315	Yes	T101,T305,T315	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T3,T100,T101	Yes	T3,T100,T101	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T3,T100,T101	Yes	T3,T100,T101	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T3,*T68,*T75	Yes	T3,T68,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T3,T68,T76	Yes	T3,T68,T76	INPUT
tl_i.a_valid	Yes	Yes	T3,T100,T101	Yes	T3,T100,T101	INPUT
tl_o.a_ready	Yes	Yes	T3,T100,T101	Yes	T3,T100,T101	OUTPUT
tl_o.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T100,T101	Yes	T3,T100,T101	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T3,T100,T101	Yes	T3,T100,T101	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T3,T100,T101	Yes	T3,T100,T101	OUTPUT
tl_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T3,*T164,*T72	Yes	T3,T164,T72	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T74,T178	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T3,*T100,*T101	Yes	T3,T100,T101	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T3,T100,T101	Yes	T3,T100,T101	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T48,T254	Yes	T3,T48,T254	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T187,T79	Yes	T78,T187,T79	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T187,T79	Yes	T78,T187,T79	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T48,T254	Yes	T3,T48,T254	OUTPUT
cio_rx_i	Yes	Yes	T100,T146,T330	Yes	T100,T146,T330	INPUT
cio_tx_o	Yes	Yes	T100,T146,T330	Yes	T100,T146,T330	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T3,T100,T101	Yes	T3,T100,T101	OUTPUT
intr_tx_empty_o	Yes	Yes	T3,T100,T101	Yes	T3,T100,T101	OUTPUT
intr_rx_watermark_o	Yes	Yes	T100,T101,T146	Yes	T100,T101,T146	OUTPUT
intr_tx_done_o	Yes	Yes	T100,T101,T146	Yes	T100,T101,T146	OUTPUT
intr_rx_overflow_o	Yes	Yes	T100,T101,T146	Yes	T100,T101,T146	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T101,T305,T315	Yes	T101,T305,T315	OUTPUT
intr_rx_break_err_o	Yes	Yes	T101,T305,T315	Yes	T101,T305,T315	OUTPUT
intr_rx_timeout_o	Yes	Yes	T101,T305,T315	Yes	T101,T305,T315	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T101,T305,T315	Yes	T101,T305,T315	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T3,T101,T15	Yes	T3,T101,T15	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T3,T101,T15	Yes	T3,T101,T15	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T3,*T68,*T75	Yes	T3,T68,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T3,T68,T76	Yes	T3,T68,T76	INPUT
tl_i.a_valid	Yes	Yes	T3,T101,T15	Yes	T3,T101,T15	INPUT
tl_o.a_ready	Yes	Yes	T3,T101,T15	Yes	T3,T101,T15	OUTPUT
tl_o.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T101,T15	Yes	T3,T101,T15	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T3,T101,T15	Yes	T3,T101,T15	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T3,T101,T15	Yes	T3,T101,T15	OUTPUT
tl_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T3,*T164,*T72	Yes	T3,T164,T72	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T3,*T101,*T15	Yes	T3,T101,T15	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T3,T101,T15	Yes	T3,T101,T15	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T350,T48	Yes	T3,T350,T48	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T350,T48	Yes	T3,T350,T48	OUTPUT
cio_rx_i	Yes	Yes	T15,T16,T355	Yes	T15,T16,T355	INPUT
cio_tx_o	Yes	Yes	T3,T15,T16	Yes	T3,T15,T16	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T3,T101,T15	Yes	T3,T101,T15	OUTPUT
intr_tx_empty_o	Yes	Yes	T101,T15,T305	Yes	T101,T15,T305	OUTPUT
intr_rx_watermark_o	Yes	Yes	T101,T15,T305	Yes	T101,T15,T305	OUTPUT
intr_tx_done_o	Yes	Yes	T101,T15,T305	Yes	T101,T15,T305	OUTPUT
intr_rx_overflow_o	Yes	Yes	T101,T15,T305	Yes	T101,T15,T305	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T101,T305,T315	Yes	T101,T305,T315	OUTPUT
intr_rx_break_err_o	Yes	Yes	T101,T305,T315	Yes	T101,T305,T315	OUTPUT
intr_rx_timeout_o	Yes	Yes	T101,T305,T315	Yes	T101,T305,T315	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T101,T305,T315	Yes	T101,T305,T315	OUTPUT

*Tests covering at least one bit in the range