Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T72,T74,T214	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T74,T257,T258	Yes	T74,T257,T258	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T5,T204,T226	Yes	T5,T204,T226	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T157,T204	Yes	T5,T157,T204	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T3,T68,T76	Yes	T3,T68,T76	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T68,T74,T178	Yes	T68,T74,T178	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T68,T72,T73	Yes	T68,T72,T73	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T5,T62,T157	Yes	T5,T62,T157	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T3,T67,T68	Yes	T3,T67,T68	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T3,T67,T68	Yes	T3,T67,T68	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T3,T67,T68	Yes	T3,T67,T68	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T3,T67,T68	Yes	T3,T67,T68	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T3,T67,T68	Yes	T3,T67,T68	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T3,T67,T68	Yes	T3,T67,T68	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T3,*T67,*T68	Yes	T3,T67,T68	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T3,T67,T68	Yes	T3,T67,T68	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T72,T74,T178	Yes	T72,T74,T178	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T72,T74,T178	Yes	T72,T74,T178	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T72,T74,T178	Yes	T72,T73,T74	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T263,T264,T47	Yes	T263,T264,T47	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T263,T264,T47	Yes	T263,T264,T47	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T263,T264,T47	Yes	T263,T264,T47	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T263,T264,T47	Yes	T263,T264,T47	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T263,T264,T47	Yes	T263,T264,T47	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T263,*T264,*T265	Yes	T263,T264,T265	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T263,T264,T47	Yes	T263,T264,T47	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T5,T6	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T263,T264,T265	Yes	T263,T264,T265	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T263,T264,T47	Yes	T263,T264,T47	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T3,T5,T6	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T263,*T264,*T265	Yes	T263,T264,T265	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T3,T5,T6	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T263,T264,T47	Yes	T263,T264,T47	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T44,T67,T45	Yes	T44,T67,T45	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T412,T48,T281	Yes	T412,T48,T281	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T412,T48,T281	Yes	T412,T48,T281	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T412,T48,T281	Yes	T412,T48,T281	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	T72,*T73,*T74	Yes	T72,T73,T74	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T72,T74,T178	Yes	T72,T74,T178	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T412,T48,T281	Yes	T412,T48,T281	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T412,T48,T281	Yes	T412,T48,T281	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T412,T281,T413	Yes	T412,T281,T413	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T48,T49,T50	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T412,T281,T413	Yes	T412,T48,T281	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T72,T74,T178	Yes	T72,T74,T178	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T281,*T414,*T415	Yes	T412,T281,T413	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T412,T48,T281	Yes	T412,T48,T281	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	T3,*T68,*T75	Yes	T3,T68,T75	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T3,T68,T76	Yes	T3,T68,T76	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T5,T157,T204	Yes	T5,T157,T204	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	T3,*T68,*T75	Yes	T3,T68,T75	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T180,T377,T405	Yes	T180,T377,T405	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T180,T377,T48	Yes	T180,T377,T48	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T180,T377,T405	Yes	T180,T377,T405	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T180,T377,T405	Yes	T180,T377,T405	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T180,T377,T48	Yes	T180,T377,T48	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T180,T377,T405	Yes	T180,T377,T405	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T47,*T72,*T74	Yes	T47,T72,T74	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T12,T161,T72	Yes	T12,T161,T72	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T180,T377,T405	Yes	T180,T377,T405	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T180,T377,T405	Yes	T180,T377,T405	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T74,T178	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T180,T377,T181	Yes	T180,T377,T181	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T180,T377,T405	Yes	T180,T377,T405	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T180,T377,T181	Yes	T180,T377,T181	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T47,*T72,*T73	Yes	T47,T72,T73	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T180,*T377,*T405	Yes	T180,T377,T405	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T180,T377,T405	Yes	T180,T377,T405	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T32,T180,T377	Yes	T32,T180,T377	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T32,T180,T377	Yes	T32,T180,T377	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T32,T180,T377	Yes	T32,T180,T377	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T32,T180,T377	Yes	T32,T180,T377	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T32,T180,T377	Yes	T32,T180,T377	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T32,T180,T377	Yes	T32,T180,T377	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T47,*T72,*T73	Yes	T47,T72,T73	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T32,T180,T377	Yes	T32,T180,T377	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T32,T180,T377	Yes	T32,T180,T377	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T32,T180,T377	Yes	T32,T180,T377	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T32,T180,T377	Yes	T32,T180,T377	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T32,T180,T377	Yes	T32,T180,T377	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T47,*T72,*T73	Yes	T47,T72,T73	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T32,*T180,*T377	Yes	T32,T180,T377	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T32,T180,T377	Yes	T32,T180,T377	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T3,T17,T18	Yes	T3,T17,T18	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T3,T17,T18	Yes	T3,T17,T18	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T17,T18	Yes	T3,T17,T18	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T3,T17,T18	Yes	T3,T17,T18	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T3,T17,T18	Yes	T3,T17,T18	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T3,T17,T18	Yes	T3,T17,T18	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T3,*T164,*T72	Yes	T3,T164,T72	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T3,T17,T18	Yes	T3,T17,T18	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T3,T17,T18	Yes	T3,T17,T18	INPUT
tl_usbdev_i.d_error	Yes	Yes	T72,T74,T178	Yes	T72,T73,T74	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T3,T17,T18	Yes	T3,T17,T18	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T17,T18	Yes	T3,T17,T18	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T3,T17,T18	Yes	T3,T17,T18	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T74,T214	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T3,*T164,*T72	Yes	T3,T164,T72	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T3,*T17,*T18	Yes	T3,T17,T18	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T3,T17,T18	Yes	T3,T17,T18	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T5,T6	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T5,T6,T44	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T72,T74,T214	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T72,*T74,*T214	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T72,T74,T178	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_hmac_o.d_ready	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T44,T300,T45	Yes	T44,T300,T45	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T44,T300,T45	Yes	T44,T300,T45	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T44,T300,T45	Yes	T44,T300,T45	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T44,T300,T45	Yes	T44,T300,T45	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T44,T300,T45	Yes	T44,T300,T45	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T300,T713,T375	Yes	T300,T713,T375	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T44,T300,T45	Yes	T44,T300,T45	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T44,T300,T45	Yes	T44,T300,T45	INPUT
tl_hmac_i.d_error	Yes	Yes	T72,T74,T178	Yes	T72,T74,T178	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T44,T300,T45	Yes	T44,T300,T45	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T44,T300,T45	Yes	T44,T300,T45	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T44,T300,T45	Yes	T44,T300,T45	INPUT
tl_hmac_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T44,*T300,*T45	Yes	T44,T300,T45	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T44,T300,T45	Yes	T44,T300,T45	INPUT
tl_kmac_o.d_ready	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T180,T97,T112	Yes	T180,T97,T112	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T180,T159,T97	Yes	T180,T159,T97	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T180,T159,T97	Yes	T180,T159,T97	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T180,T97,T112	Yes	T180,T97,T112	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T180,T159,T97	Yes	T180,T159,T97	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T47,*T72,*T73	Yes	T47,T72,T73	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T459,T460,T461	Yes	T459,T460,T461	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T180,T159,T97	Yes	T180,T159,T97	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T180,T159,T97	Yes	T180,T159,T97	INPUT
tl_kmac_i.d_error	Yes	Yes	T72,T74,T178	Yes	T72,T74,T178	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T180,T159,T97	Yes	T180,T159,T97	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T180,T159,T97	Yes	T180,T159,T97	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T180,T159,T97	Yes	T180,T159,T97	INPUT
tl_kmac_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T74,T214	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T47,*T72,*T73	Yes	T47,T72,T73	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T72,T74,T178	Yes	T72,T73,T74	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T180,*T159,*T97	Yes	T180,T159,T227	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T180,T159,T97	Yes	T180,T159,T97	INPUT
tl_aes_o.d_ready	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T3,T82,T295	Yes	T3,T82,T295	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T82,T295	Yes	T3,T82,T295	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T3,T82,T295	Yes	T3,T82,T295	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T3,T82,T295	Yes	T3,T82,T295	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T3,T82,T295	Yes	T3,T82,T295	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T3,*T72,*T73	Yes	T3,T72,T73	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T3,T82,T295	Yes	T3,T82,T295	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T3,T82,T295	Yes	T3,T82,T295	INPUT
tl_aes_i.d_error	Yes	Yes	T72,T74,T178	Yes	T72,T74,T178	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T3,T82,T295	Yes	T3,T82,T295	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T82,T295	Yes	T3,T82,T295	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T3,T82,T295	Yes	T3,T82,T295	INPUT
tl_aes_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T74,T214	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T3,*T72,*T73	Yes	T3,T72,T73	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T3,*T82,*T295	Yes	T3,T82,T295	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T3,T82,T295	Yes	T3,T82,T295	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T72,T74,T178	Yes	T72,T74,T178	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T4,T121,T122	Yes	T4,T121,T122	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T1,T2,T4	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T5,T6,T44	Yes	T1,T2,T4	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T72,T74,T214	Yes	T72,T74,T214	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T74,T214	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T72,T74,T178	Yes	T72,T73,T74	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T4,*T121,*T122	Yes	T4,T44,T121	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T3,T4,T121	Yes	T3,T4,T121	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T3,*T72,*T73	Yes	T3,T72,T73	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T72,T74,T178	Yes	T72,T74,T178	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T121	Yes	T3,T4,T121	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T3,*T72,*T73	Yes	T3,T72,T73	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T3,*T4,*T121	Yes	T3,T4,T121	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T4,T121,T295	Yes	T4,T121,T295	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T4,T121,T295	Yes	T4,T121,T295	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T72,T74,T178	Yes	T72,T74,T178	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_edn0_i.d_error	Yes	Yes	T72,T74,T178	Yes	T72,T74,T178	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T4,T121,T295	Yes	T4,T121,T295	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T1,T2,T4	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T1,T2,T4	INPUT
tl_edn0_i.d_sink	Yes	Yes	T72,T74,T214	Yes	T72,T73,T74	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T72,*T74,*T214	Yes	T72,T73,T74	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T72,T74,T178	Yes	T72,T74,T178	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T4,*T121,*T295	Yes	T4,T121,T295	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_edn1_o.d_ready	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T4,T121,T122	Yes	T4,T121,T122	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T121,T122	Yes	T4,T121,T122	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T121,T122	Yes	T4,T121,T122	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T4,T121,T122	Yes	T4,T121,T122	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T4,T121,T122	Yes	T4,T121,T122	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T4,T121,T122	Yes	T4,T121,T122	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T4,T121,T122	Yes	T4,T121,T122	INPUT
tl_edn1_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T4,T121,T122	Yes	T4,T121,T122	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T121,T122	Yes	T4,T121,T122	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T4,T121,T122	Yes	T4,T121,T122	INPUT
tl_edn1_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T4,*T121,*T122	Yes	T4,T121,T122	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T4,T121,T122	Yes	T4,T121,T122	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T2,T5,T62	Yes	T2,T5,T62	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T5,T62	Yes	T2,T5,T62	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T2,T5,T62	Yes	T2,T5,T62	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T2,T5,T62	Yes	T2,T5,T62	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T2,T5,T62	Yes	T2,T5,T62	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T47,*T72,*T73	Yes	T47,T72,T73	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T72,T74,T178	Yes	T72,T74,T178	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T2,T5,T62	Yes	T2,T5,T62	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T2,T5,T62	Yes	T2,T5,T62	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T72,T74,T178	Yes	T72,T74,T178	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T2,T5,T62	Yes	T2,T5,T62	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T5,T62	Yes	T2,T5,T62	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T2,T5,T62	Yes	T2,T5,T62	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T72,T74,T214	Yes	T72,T73,T74	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T47,*T72,*T73	Yes	T47,T72,T73	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T2,*T5,*T62	Yes	T2,T5,T62	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T2,T5,T62	Yes	T2,T5,T62	INPUT
tl_otbn_o.d_ready	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T44,T180,T45	Yes	T44,T180,T45	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T44,T180,T45	Yes	T44,T180,T45	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T44,T180,T45	Yes	T44,T180,T45	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T44,T180,T45	Yes	T44,T180,T45	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T44,T180,T45	Yes	T44,T180,T45	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T68,*T76,*T47	Yes	T68,T76,T47	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T44,T180,T45	Yes	T44,T180,T45	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T44,T180,T45	Yes	T44,T180,T45	INPUT
tl_otbn_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T44,T180,T45	Yes	T44,T180,T45	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T44,T180,T45	Yes	T44,T180,T45	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T44,T180,T45	Yes	T44,T180,T45	INPUT
tl_otbn_i.d_sink	Yes	Yes	T72,T74,T214	Yes	T72,T74,T214	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T68,*T76,*T47	Yes	T68,T76,T47	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T44,*T180,*T45	Yes	T44,T180,T45	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T44,T180,T45	Yes	T44,T180,T45	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T44,T180,T63	Yes	T44,T180,T63	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T44,T180,T63	Yes	T44,T180,T63	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T44,T180,T63	Yes	T44,T180,T63	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T180,T63,T159	Yes	T180,T63,T159	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T44,T180,T63	Yes	T44,T180,T63	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T44,T180,T63	Yes	T44,T180,T63	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T44,T180,T63	Yes	T44,T180,T63	INPUT
tl_keymgr_i.d_error	Yes	Yes	T72,T74,T178	Yes	T72,T74,T178	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T180,T63,T45	Yes	T180,T63,T45	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T44,T180,T63	Yes	T44,T180,T63	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T44,T63,T45	Yes	T44,T180,T63	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T74,T178	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T44,*T180,*T63	Yes	T44,T180,T63	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T44,T180,T63	Yes	T44,T180,T63	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T72,*T214,*T257	Yes	T72,T214,T257	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T72,T178,T214	Yes	T72,T178,T214	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T72,T73,T178	Yes	T72,T73,T178	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T72,T73,T214	Yes	T72,T73,T214	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T72,T73,T214	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T214	Yes	T72,T73,T214	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T72,T73,T178	Yes	T72,T73,T178	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T3,T5,T6	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T44,T45,T296	Yes	T44,T45,T296	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T44,T45,T296	Yes	T44,T45,T296	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T44,T45,T296	Yes	T44,T45,T296	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T47,*T448,*T449	Yes	T47,T448,T449	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T44,T45,T296	Yes	T44,T45,T296	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T44,T45,T296	Yes	T44,T45,T296	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T208,T209,T47	Yes	T208,T209,T47	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T41,T42,T208	Yes	T44,T45,T46	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T41,T42,T208	Yes	T44,T45,T46	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T47,*T72,*T73	Yes	T47,T448,T449	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T208,*T209,*T207	Yes	T296,T450,T208	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T44,T45,T296	Yes	T44,T45,T296	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range