Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.34 99.34

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_edn1 99.02 99.02
tb.dut.top_earlgrey.u_edn0 99.25 99.25


Module Instance : tb.dut.top_earlgrey.u_edn1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.02 99.02


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.02 99.02


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_edn0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.25 99.25


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.25 99.25


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 78 75 96.15
Total Bits 1210 1202 99.34
Total Bits 0->1 605 602 99.50
Total Bits 1->0 605 600 99.17

Ports 78 75 96.15
Port Bits 1210 1202 99.34
Port Bits 0->1 605 602 99.50
Port Bits 1->0 605 600 99.17

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T5,T6 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T4,T121,T295 Yes T4,T121,T295 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T4,T121,T295 Yes T4,T121,T295 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
tl_i.a_address[6:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:16] Yes Yes *T1,*T2,T4 Yes T1,T2,T4 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T4 Yes T1,T2,T4 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T4 Yes T1,T2,T4 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 INPUT
tl_i.a_valid Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
tl_o.a_ready Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
tl_o.d_error Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T4,T121,T295 Yes T4,T121,T295 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T1,T2,T4 OUTPUT
tl_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T1,T2,T4 OUTPUT
tl_o.d_sink Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
tl_o.d_source[5:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T4,*T121,*T295 Yes T4,T121,T295 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
edn_i[0].edn_req Yes Yes T63,T122,T159 Yes T63,T122,T159 INPUT
edn_i[1].edn_req Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
edn_i[2].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[3].edn_req Yes Yes T176,T278,T284 Yes T176,T278,T284 INPUT
edn_i[4].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[5].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[6].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[7].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T63,T122,T159 Yes T63,T122,T159 OUTPUT
edn_o[0].edn_fips Yes Yes T122,T111,T444 Yes T122,T112,T318 OUTPUT
edn_o[0].edn_ack Yes Yes T63,T122,T159 Yes T63,T122,T159 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T1,T4,T5 Yes T1,T2,T4 OUTPUT
edn_o[1].edn_fips No No Yes T175,T176,T177 OUTPUT
edn_o[1].edn_ack Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
edn_o[2].edn_fips Yes Yes T108,T111,T110 Yes T112,T108,T111 OUTPUT
edn_o[2].edn_ack Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T278,T284,T462 Yes T176,T278,T284 OUTPUT
edn_o[3].edn_fips No No Yes T176,T278,T284 OUTPUT
edn_o[3].edn_ack Yes Yes T176,T278,T284 Yes T176,T278,T284 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T4,T7,T121 Yes T1,T2,T4 OUTPUT
edn_o[4].edn_fips Yes Yes T676 Yes T111,T677,T678 OUTPUT
edn_o[4].edn_ack Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
edn_o[5].edn_fips Yes Yes T122,T111,T444 Yes T122,T176,T111 OUTPUT
edn_o[5].edn_ack Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
edn_o[6].edn_fips Yes Yes T122,T111,T444 Yes T122,T318,T175 OUTPUT
edn_o[6].edn_ack Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T4,T5,T44 Yes T1,T4,T5 OUTPUT
edn_o[7].edn_fips Yes Yes T122,T108,T111 Yes T4,T121,T122 OUTPUT
edn_o[7].edn_ack Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T4,T5,T6 Yes T1,T2,T4 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
csrng_cmd_i.genbits_fips Yes Yes T108,T110,T463 Yes T4,T121,T122 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T295,T122,T111 Yes T295,T122,T111 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T295,T48,T78 Yes T295,T48,T78 INPUT
alert_rx_i[0].ping_n Yes Yes T78,T187,T79 Yes T78,T187,T79 INPUT
alert_rx_i[0].ping_p Yes Yes T78,T187,T79 Yes T78,T187,T79 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T158,T48,T78 Yes T158,T48,T78 INPUT
alert_rx_i[1].ping_n Yes Yes T78,T187,T79 Yes T78,T187,T79 INPUT
alert_rx_i[1].ping_p Yes Yes T78,T187,T79 Yes T78,T187,T79 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T295,T48,T78 Yes T295,T48,T78 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T158,T48,T78 Yes T158,T48,T78 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T262,T316,T120 Yes T262,T316,T120 OUTPUT
intr_edn_fatal_err_o Yes Yes T262,T316,T317 Yes T262,T316,T317 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn1
TotalCoveredPercent
Totals 50 48 96.00
Total Bits 714 707 99.02
Total Bits 0->1 357 354 99.16
Total Bits 1->0 357 353 98.88

Ports 50 48 96.00
Port Bits 714 707 99.02
Port Bits 0->1 357 354 99.16
Port Bits 1->0 357 353 98.88

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T5,T6 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T3,T4,T5 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T4,T121,T122 Yes T4,T121,T122 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T121,T122 Yes T4,T121,T122 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T121,T122 Yes T4,T121,T122 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T4,T121,T122 Yes T4,T121,T122 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T121,T122 Yes T4,T121,T122 INPUT
tl_i.a_address[6:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 INPUT
tl_i.a_address[18:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:19] Yes Yes T4,T121,T122 Yes T4,T121,T122 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T4,*T121,*T122 Yes T4,T121,T122 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T121,*T122 Yes T4,T121,T122 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 INPUT
tl_i.a_valid Yes Yes T4,T121,T122 Yes T4,T121,T122 INPUT
tl_o.a_ready Yes Yes T4,T121,T122 Yes T4,T121,T122 OUTPUT
tl_o.d_error Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T4,T121,T122 Yes T4,T121,T122 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T4,T121,T122 Yes T4,T121,T122 OUTPUT
tl_o.d_data[31:0] Yes Yes T4,T121,T122 Yes T4,T121,T122 OUTPUT
tl_o.d_sink Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
tl_o.d_source[5:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T4,*T121,*T122 Yes T4,T121,T122 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T4,T121,T122 Yes T4,T121,T122 OUTPUT
edn_i[0].edn_req Yes Yes T122,T318,T175 Yes T122,T318,T175 INPUT
edn_i[1].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[2].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[3].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[4].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[5].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[6].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[7].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_o[0].edn_bus[31:0] Yes Yes T122,T318,T175 Yes T122,T318,T175 OUTPUT
edn_o[0].edn_fips Yes Yes T122,T111,T444 Yes T122,T318,T175 OUTPUT
edn_o[0].edn_ack Yes Yes T122,T318,T175 Yes T122,T318,T175 OUTPUT
edn_o[1].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
csrng_cmd_o.genbits_ready Yes Yes T4,T121,T122 Yes T4,T121,T122 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T122,T108,T318 Yes T4,T121,T122 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T4,T121,T122 Yes T4,T121,T122 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T4,T122,T108 Yes T122,T112,T108 INPUT
csrng_cmd_i.genbits_fips No No Yes T463,T464,T673 INPUT
csrng_cmd_i.genbits_valid Yes Yes T4,T121,T122 Yes T4,T121,T122 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T4,T121,T122 Yes T4,T121,T122 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T122,T111,T444 Yes T122,T111,T444 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T48,T78,T187 Yes T48,T78,T187 INPUT
alert_rx_i[0].ping_n Yes Yes T78,T187,T79 Yes T187,T80,T268 INPUT
alert_rx_i[0].ping_p Yes Yes T187,T80,T268 Yes T78,T187,T79 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T48,T78,T79 Yes T48,T78,T79 INPUT
alert_rx_i[1].ping_n Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
alert_rx_i[1].ping_p Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T48,T78,T187 Yes T48,T78,T187 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T48,T78,T79 Yes T48,T78,T79 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T262,T316,T120 Yes T262,T316,T120 OUTPUT
intr_edn_fatal_err_o Yes Yes T262,T316,T317 Yes T262,T316,T317 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn0
TotalCoveredPercent
Totals 78 74 94.87
Total Bits 1208 1199 99.25
Total Bits 0->1 604 601 99.50
Total Bits 1->0 604 598 99.01

Ports 78 74 94.87
Port Bits 1208 1199 99.25
Port Bits 0->1 604 601 99.50
Port Bits 1->0 604 598 99.01

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T5,T6 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T4,T121,T295 Yes T4,T121,T295 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T4,T121,T295 Yes T4,T121,T295 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
tl_i.a_address[6:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:16] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
tl_i.a_address[19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T1,*T2,*T4 Yes T1,T2,T4 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T4 Yes T1,T2,T4 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T4 Yes T1,T2,T4 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T72,T74,T178 Yes T72,T74,T178 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 INPUT
tl_i.a_valid Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
tl_o.a_ready Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
tl_o.d_error Yes Yes T72,T74,T178 Yes T72,T74,T178 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T4,T121,T295 Yes T4,T121,T295 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T1,T2,T4 OUTPUT
tl_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T1,T2,T4 OUTPUT
tl_o.d_sink Yes Yes T72,T74,T214 Yes T72,T73,T74 OUTPUT
tl_o.d_source[5:0] Yes Yes *T72,*T74,*T214 Yes T72,T73,T74 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T72,T74,T178 Yes T72,T74,T178 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T4,*T121,*T295 Yes T4,T121,T295 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
edn_i[0].edn_req Yes Yes T63,T159,T97 Yes T63,T159,T97 INPUT
edn_i[1].edn_req Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
edn_i[2].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[3].edn_req Yes Yes T176,T278,T284 Yes T176,T278,T284 INPUT
edn_i[4].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[5].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[6].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[7].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T63,T159,T112 Yes T63,T159,T112 OUTPUT
edn_o[0].edn_fips No No Yes T112,T176,T229 OUTPUT
edn_o[0].edn_ack Yes Yes T63,T159,T97 Yes T63,T159,T97 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T1,T4,T5 Yes T1,T2,T4 OUTPUT
edn_o[1].edn_fips No No Yes T175,T176,T177 OUTPUT
edn_o[1].edn_ack Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
edn_o[2].edn_fips Yes Yes T108,T111,T110 Yes T112,T108,T111 OUTPUT
edn_o[2].edn_ack Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T278,T284,T462 Yes T176,T278,T284 OUTPUT
edn_o[3].edn_fips No No Yes T176,T278,T284 OUTPUT
edn_o[3].edn_ack Yes Yes T176,T278,T284 Yes T176,T278,T284 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T4,T7,T121 Yes T1,T2,T4 OUTPUT
edn_o[4].edn_fips Yes Yes T676 Yes T111,T677,T678 OUTPUT
edn_o[4].edn_ack Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
edn_o[5].edn_fips Yes Yes T122,T111,T444 Yes T122,T176,T111 OUTPUT
edn_o[5].edn_ack Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
edn_o[6].edn_fips Yes Yes T122,T111,T444 Yes T122,T318,T175 OUTPUT
edn_o[6].edn_ack Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T4,T5,T44 Yes T1,T4,T5 OUTPUT
edn_o[7].edn_fips Yes Yes T122,T108,T111 Yes T4,T121,T122 OUTPUT
edn_o[7].edn_ack Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T4,T5,T6 Yes T1,T2,T4 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
csrng_cmd_i.genbits_fips Yes Yes T108,T110,T463 Yes T4,T121,T122 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T295,T122,T111 Yes T295,T122,T111 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T295,T48,T78 Yes T295,T48,T78 INPUT
alert_rx_i[0].ping_n Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
alert_rx_i[0].ping_p Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T158,T48,T78 Yes T158,T48,T78 INPUT
alert_rx_i[1].ping_n Yes Yes T78,T187,T79 Yes T78,T187,T79 INPUT
alert_rx_i[1].ping_p Yes Yes T78,T187,T79 Yes T78,T187,T79 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T295,T48,T78 Yes T295,T48,T78 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T158,T48,T78 Yes T158,T48,T78 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T262,T316,T120 Yes T262,T316,T120 OUTPUT
intr_edn_fatal_err_o Yes Yes T262,T316,T317 Yes T262,T316,T317 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%