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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.08 95.51 93.81 95.54 94.55 97.53 99.52


Total test records in report: 2930
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T284 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.4099020609 Jul 23 07:56:56 PM PDT 24 Jul 23 08:14:40 PM PDT 24 6641176164 ps
T285 /workspace/coverage/default/2.chip_tap_straps_rma.1402341767 Jul 23 07:59:57 PM PDT 24 Jul 23 08:07:08 PM PDT 24 5269387891 ps
T286 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2085038164 Jul 23 07:45:20 PM PDT 24 Jul 23 07:47:54 PM PDT 24 2759338846 ps
T287 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.1717442943 Jul 23 07:50:26 PM PDT 24 Jul 23 08:03:37 PM PDT 24 6991542634 ps
T84 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.230990318 Jul 23 08:11:45 PM PDT 24 Jul 23 08:20:13 PM PDT 24 3497797986 ps
T238 /workspace/coverage/default/1.chip_sw_flash_init.4058514060 Jul 23 07:44:33 PM PDT 24 Jul 23 08:32:33 PM PDT 24 21287815028 ps
T288 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.400179559 Jul 23 07:33:17 PM PDT 24 Jul 23 08:45:49 PM PDT 24 19977338705 ps
T265 /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.1977441797 Jul 23 07:40:30 PM PDT 24 Jul 23 08:36:13 PM PDT 24 21801566715 ps
T755 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3547010920 Jul 23 08:07:24 PM PDT 24 Jul 23 08:15:19 PM PDT 24 4124121574 ps
T170 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2280493698 Jul 23 07:55:20 PM PDT 24 Jul 23 08:29:21 PM PDT 24 25776833490 ps
T1032 /workspace/coverage/default/2.chip_sw_hmac_oneshot.4246783345 Jul 23 07:57:18 PM PDT 24 Jul 23 08:02:03 PM PDT 24 2878764470 ps
T79 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.3650057149 Jul 23 07:32:14 PM PDT 24 Jul 23 07:37:29 PM PDT 24 3699536060 ps
T1033 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.418107766 Jul 23 07:33:35 PM PDT 24 Jul 23 07:37:31 PM PDT 24 3024701534 ps
T93 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1676303349 Jul 23 07:58:20 PM PDT 24 Jul 23 08:23:07 PM PDT 24 24539559912 ps
T80 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2028467425 Jul 23 07:47:32 PM PDT 24 Jul 23 08:14:03 PM PDT 24 12703046300 ps
T770 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2822269656 Jul 23 08:05:46 PM PDT 24 Jul 23 08:13:11 PM PDT 24 4396177032 ps
T1034 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3737612833 Jul 23 08:02:56 PM PDT 24 Jul 23 08:13:57 PM PDT 24 4124867448 ps
T335 /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.709894195 Jul 23 07:59:13 PM PDT 24 Jul 23 08:07:08 PM PDT 24 4149762640 ps
T779 /workspace/coverage/default/83.chip_sw_all_escalation_resets.2231361849 Jul 23 08:13:26 PM PDT 24 Jul 23 08:23:03 PM PDT 24 6328469160 ps
T1035 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.751209355 Jul 23 07:39:24 PM PDT 24 Jul 23 07:50:08 PM PDT 24 4128819378 ps
T1036 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.4199467559 Jul 23 07:49:28 PM PDT 24 Jul 23 07:58:04 PM PDT 24 6231216666 ps
T1037 /workspace/coverage/default/0.chip_tap_straps_dev.3032890282 Jul 23 07:37:07 PM PDT 24 Jul 23 07:49:26 PM PDT 24 7957421988 ps
T683 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1141389860 Jul 23 07:35:39 PM PDT 24 Jul 23 07:38:03 PM PDT 24 2593473855 ps
T448 /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.1918754562 Jul 23 07:41:12 PM PDT 24 Jul 23 08:26:14 PM PDT 24 37185587864 ps
T332 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.4154313997 Jul 23 07:54:38 PM PDT 24 Jul 23 08:06:43 PM PDT 24 5251521708 ps
T1038 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.999291425 Jul 23 07:46:35 PM PDT 24 Jul 23 07:58:09 PM PDT 24 19830361318 ps
T415 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3876381231 Jul 23 07:33:49 PM PDT 24 Jul 23 07:44:14 PM PDT 24 8204977178 ps
T699 /workspace/coverage/default/1.chip_sw_plic_sw_irq.3131168736 Jul 23 07:49:11 PM PDT 24 Jul 23 07:53:53 PM PDT 24 2775797468 ps
T808 /workspace/coverage/default/6.chip_sw_all_escalation_resets.3280901468 Jul 23 08:04:51 PM PDT 24 Jul 23 08:16:08 PM PDT 24 5373932480 ps
T1039 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.1694090669 Jul 23 07:57:49 PM PDT 24 Jul 23 08:03:00 PM PDT 24 2862180280 ps
T291 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3706789775 Jul 23 07:57:42 PM PDT 24 Jul 23 08:08:12 PM PDT 24 5339349570 ps
T245 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.1029962746 Jul 23 08:02:06 PM PDT 24 Jul 23 08:35:10 PM PDT 24 21916851041 ps
T818 /workspace/coverage/default/86.chip_sw_all_escalation_resets.4174487979 Jul 23 08:12:36 PM PDT 24 Jul 23 08:21:21 PM PDT 24 5464916424 ps
T1040 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3957705727 Jul 23 07:57:07 PM PDT 24 Jul 23 08:45:23 PM PDT 24 13143041664 ps
T684 /workspace/coverage/default/2.rom_volatile_raw_unlock.525250175 Jul 23 08:02:10 PM PDT 24 Jul 23 08:04:01 PM PDT 24 2581568126 ps
T1041 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.18529933 Jul 23 07:47:05 PM PDT 24 Jul 23 07:59:54 PM PDT 24 6194092008 ps
T1042 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2273204726 Jul 23 07:58:50 PM PDT 24 Jul 23 08:05:32 PM PDT 24 5000429308 ps
T1043 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.1558218752 Jul 23 07:50:36 PM PDT 24 Jul 23 08:03:07 PM PDT 24 7305627000 ps
T685 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.577093196 Jul 23 07:44:32 PM PDT 24 Jul 23 07:46:12 PM PDT 24 2444733580 ps
T1044 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.3718882376 Jul 23 07:46:08 PM PDT 24 Jul 23 07:49:34 PM PDT 24 3002708433 ps
T1045 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3948680526 Jul 23 07:42:06 PM PDT 24 Jul 23 07:45:56 PM PDT 24 2343290880 ps
T768 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.4088462909 Jul 23 08:12:02 PM PDT 24 Jul 23 08:18:42 PM PDT 24 4202525408 ps
T1046 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.463613746 Jul 23 07:36:03 PM PDT 24 Jul 23 07:42:07 PM PDT 24 4076030328 ps
T1047 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.1343452899 Jul 23 08:05:44 PM PDT 24 Jul 23 08:21:35 PM PDT 24 5116246758 ps
T337 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3146056174 Jul 23 07:49:48 PM PDT 24 Jul 23 07:57:49 PM PDT 24 3828277960 ps
T292 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.1901014622 Jul 23 07:54:14 PM PDT 24 Jul 23 08:04:05 PM PDT 24 5334008056 ps
T783 /workspace/coverage/default/19.chip_sw_all_escalation_resets.3346992257 Jul 23 08:08:05 PM PDT 24 Jul 23 08:19:29 PM PDT 24 6100015464 ps
T1048 /workspace/coverage/default/1.rom_e2e_self_hash.1437852515 Jul 23 07:57:05 PM PDT 24 Jul 23 09:48:44 PM PDT 24 25636530540 ps
T1049 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.2002386433 Jul 23 07:34:23 PM PDT 24 Jul 23 07:38:42 PM PDT 24 3293131160 ps
T821 /workspace/coverage/default/56.chip_sw_all_escalation_resets.2930771592 Jul 23 08:10:28 PM PDT 24 Jul 23 08:21:06 PM PDT 24 5598949112 ps
T341 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4102719737 Jul 23 07:50:28 PM PDT 24 Jul 23 08:01:32 PM PDT 24 5005498861 ps
T1050 /workspace/coverage/default/1.rom_e2e_static_critical.1987536711 Jul 23 07:56:57 PM PDT 24 Jul 23 09:06:13 PM PDT 24 17112951168 ps
T1051 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2972098602 Jul 23 07:33:32 PM PDT 24 Jul 23 07:43:44 PM PDT 24 4664933641 ps
T1052 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.911093948 Jul 23 07:54:00 PM PDT 24 Jul 23 08:02:47 PM PDT 24 4275106054 ps
T373 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.929258501 Jul 23 08:09:10 PM PDT 24 Jul 23 08:15:00 PM PDT 24 3035618036 ps
T1053 /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2471090817 Jul 23 08:02:12 PM PDT 24 Jul 23 09:08:27 PM PDT 24 15768155664 ps
T1054 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.124759876 Jul 23 08:02:38 PM PDT 24 Jul 23 08:21:43 PM PDT 24 9230257657 ps
T788 /workspace/coverage/default/66.chip_sw_all_escalation_resets.1638000061 Jul 23 08:11:37 PM PDT 24 Jul 23 08:23:11 PM PDT 24 6009249708 ps
T1055 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.380950153 Jul 23 07:39:16 PM PDT 24 Jul 23 08:13:44 PM PDT 24 11368890963 ps
T1056 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.986194975 Jul 23 07:33:10 PM PDT 24 Jul 23 08:44:42 PM PDT 24 17665910500 ps
T804 /workspace/coverage/default/46.chip_sw_all_escalation_resets.2279468289 Jul 23 08:10:34 PM PDT 24 Jul 23 08:21:16 PM PDT 24 4384179726 ps
T1057 /workspace/coverage/default/17.chip_sw_all_escalation_resets.3222096093 Jul 23 08:05:52 PM PDT 24 Jul 23 08:16:17 PM PDT 24 6026435264 ps
T1058 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1522553791 Jul 23 07:48:56 PM PDT 24 Jul 23 08:00:59 PM PDT 24 4642475816 ps
T792 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2254647326 Jul 23 08:09:51 PM PDT 24 Jul 23 08:16:07 PM PDT 24 3171703904 ps
T1059 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.616049734 Jul 23 08:05:20 PM PDT 24 Jul 23 09:04:17 PM PDT 24 15010706360 ps
T1060 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3556723235 Jul 23 07:41:21 PM PDT 24 Jul 23 07:53:48 PM PDT 24 5752228240 ps
T137 /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1299260041 Jul 23 07:51:37 PM PDT 24 Jul 23 08:34:21 PM PDT 24 18015823833 ps
T182 /workspace/coverage/default/1.chip_plic_all_irqs_10.3075814529 Jul 23 07:49:46 PM PDT 24 Jul 23 07:59:09 PM PDT 24 3751613150 ps
T246 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1495594707 Jul 23 07:45:40 PM PDT 24 Jul 23 09:31:33 PM PDT 24 45843611068 ps
T1061 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3356638386 Jul 23 07:54:05 PM PDT 24 Jul 23 08:06:17 PM PDT 24 4459527692 ps
T1062 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1456144188 Jul 23 08:06:09 PM PDT 24 Jul 23 08:20:03 PM PDT 24 11641985409 ps
T1063 /workspace/coverage/default/1.chip_sw_edn_kat.1887485382 Jul 23 07:47:44 PM PDT 24 Jul 23 07:59:21 PM PDT 24 2817177720 ps
T1064 /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.146073022 Jul 23 07:53:30 PM PDT 24 Jul 23 11:40:04 PM PDT 24 78507655344 ps
T1065 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.735927114 Jul 23 07:55:57 PM PDT 24 Jul 23 08:09:59 PM PDT 24 10109942836 ps
T1066 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1500708339 Jul 23 07:53:31 PM PDT 24 Jul 23 08:08:10 PM PDT 24 5341689656 ps
T794 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.329105309 Jul 23 08:09:13 PM PDT 24 Jul 23 08:14:24 PM PDT 24 3644141560 ps
T1067 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.1369466588 Jul 23 07:36:20 PM PDT 24 Jul 23 07:43:10 PM PDT 24 5247719412 ps
T678 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2848314520 Jul 23 08:05:38 PM PDT 24 Jul 23 09:29:58 PM PDT 24 23579160950 ps
T751 /workspace/coverage/default/74.chip_sw_all_escalation_resets.1130582037 Jul 23 08:11:56 PM PDT 24 Jul 23 08:22:37 PM PDT 24 4816525940 ps
T293 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.2907355837 Jul 23 07:46:09 PM PDT 24 Jul 23 07:53:09 PM PDT 24 3376099288 ps
T36 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3018923240 Jul 23 07:46:25 PM PDT 24 Jul 23 07:55:58 PM PDT 24 7051183096 ps
T1068 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.4113165377 Jul 23 08:00:23 PM PDT 24 Jul 23 09:15:25 PM PDT 24 21719610300 ps
T145 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.1923678382 Jul 23 07:33:38 PM PDT 24 Jul 23 07:42:19 PM PDT 24 3590179724 ps
T9 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.647708844 Jul 23 07:54:10 PM PDT 24 Jul 23 07:59:45 PM PDT 24 3002425492 ps
T127 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1749763415 Jul 23 07:35:45 PM PDT 24 Jul 23 07:45:24 PM PDT 24 5736011492 ps
T1069 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.4144163884 Jul 23 07:57:11 PM PDT 24 Jul 23 08:17:02 PM PDT 24 6007427242 ps
T1070 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3197541680 Jul 23 07:58:38 PM PDT 24 Jul 23 08:07:20 PM PDT 24 3909336060 ps
T1071 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2571728750 Jul 23 07:44:24 PM PDT 24 Jul 23 08:56:46 PM PDT 24 15332537258 ps
T1072 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1347592503 Jul 23 07:35:38 PM PDT 24 Jul 23 07:40:07 PM PDT 24 3352659169 ps
T1073 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1592397850 Jul 23 07:45:52 PM PDT 24 Jul 23 08:08:10 PM PDT 24 7276924312 ps
T1074 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1356336596 Jul 23 07:43:12 PM PDT 24 Jul 23 08:53:38 PM PDT 24 16118820280 ps
T1075 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.3330819944 Jul 23 07:56:29 PM PDT 24 Jul 23 08:22:14 PM PDT 24 10724002284 ps
T374 /workspace/coverage/default/48.chip_sw_all_escalation_resets.3643380952 Jul 23 08:09:28 PM PDT 24 Jul 23 08:22:13 PM PDT 24 4722967648 ps
T761 /workspace/coverage/default/88.chip_sw_all_escalation_resets.1793109605 Jul 23 08:13:22 PM PDT 24 Jul 23 08:21:00 PM PDT 24 4582082540 ps
T1076 /workspace/coverage/default/0.chip_sw_usbdev_config_host.2903610964 Jul 23 07:33:05 PM PDT 24 Jul 23 08:03:01 PM PDT 24 8255723624 ps
T1077 /workspace/coverage/default/2.chip_sw_hmac_smoketest.1163894384 Jul 23 08:02:34 PM PDT 24 Jul 23 08:08:45 PM PDT 24 3298162212 ps
T210 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.685321481 Jul 23 07:50:13 PM PDT 24 Jul 23 07:53:28 PM PDT 24 2768346330 ps
T1078 /workspace/coverage/default/1.chip_sw_edn_sw_mode.2292710922 Jul 23 07:46:37 PM PDT 24 Jul 23 08:17:54 PM PDT 24 7252477158 ps
T1079 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1833816087 Jul 23 07:31:11 PM PDT 24 Jul 23 11:17:25 PM PDT 24 79199938597 ps
T1080 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3371218266 Jul 23 08:02:25 PM PDT 24 Jul 23 08:29:06 PM PDT 24 7993139632 ps
T1081 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1709963052 Jul 23 08:05:34 PM PDT 24 Jul 23 08:12:39 PM PDT 24 5381973300 ps
T724 /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.748309203 Jul 23 07:43:03 PM PDT 24 Jul 23 08:22:53 PM PDT 24 10544943183 ps
T1082 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3244218966 Jul 23 07:58:27 PM PDT 24 Jul 23 08:02:36 PM PDT 24 2502515978 ps
T357 /workspace/coverage/default/0.chip_sw_pattgen_ios.3109014302 Jul 23 07:32:24 PM PDT 24 Jul 23 07:36:04 PM PDT 24 2819483396 ps
T743 /workspace/coverage/default/4.chip_sw_all_escalation_resets.736417451 Jul 23 08:02:17 PM PDT 24 Jul 23 08:12:57 PM PDT 24 5400029200 ps
T397 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.866782425 Jul 23 07:44:23 PM PDT 24 Jul 23 09:08:05 PM PDT 24 18498564500 ps
T1083 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.909164505 Jul 23 07:46:10 PM PDT 24 Jul 23 08:15:49 PM PDT 24 18416212219 ps
T802 /workspace/coverage/default/96.chip_sw_all_escalation_resets.2912124251 Jul 23 08:15:10 PM PDT 24 Jul 23 08:25:30 PM PDT 24 5780209664 ps
T1084 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.189049297 Jul 23 08:04:50 PM PDT 24 Jul 23 08:16:30 PM PDT 24 4338565800 ps
T1085 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1093752471 Jul 23 07:34:23 PM PDT 24 Jul 23 08:26:11 PM PDT 24 13356496754 ps
T1086 /workspace/coverage/default/1.chip_sw_gpio_smoketest.1325911367 Jul 23 07:53:26 PM PDT 24 Jul 23 07:58:46 PM PDT 24 2976752799 ps
T462 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1712074657 Jul 23 07:48:20 PM PDT 24 Jul 23 08:03:36 PM PDT 24 6498822572 ps
T1087 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.2916932431 Jul 23 07:41:12 PM PDT 24 Jul 23 07:45:44 PM PDT 24 2401641592 ps
T239 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.3385536478 Jul 23 07:53:36 PM PDT 24 Jul 23 09:29:19 PM PDT 24 47012464825 ps
T1088 /workspace/coverage/default/0.rom_e2e_self_hash.2347443565 Jul 23 07:45:00 PM PDT 24 Jul 23 09:41:16 PM PDT 24 26434780568 ps
T1089 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3605895383 Jul 23 07:55:51 PM PDT 24 Jul 23 08:04:26 PM PDT 24 7861758704 ps
T1090 /workspace/coverage/default/3.chip_tap_straps_dev.2856402678 Jul 23 08:02:45 PM PDT 24 Jul 23 08:06:48 PM PDT 24 3540782410 ps
T94 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.599410537 Jul 23 07:53:57 PM PDT 24 Jul 23 07:59:50 PM PDT 24 3452946818 ps
T398 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2698593118 Jul 23 07:43:26 PM PDT 24 Jul 23 09:28:49 PM PDT 24 23627651558 ps
T434 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.2185281673 Jul 23 07:51:34 PM PDT 24 Jul 23 07:56:36 PM PDT 24 3026765513 ps
T435 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3448766162 Jul 23 07:51:53 PM PDT 24 Jul 23 07:57:40 PM PDT 24 3681978060 ps
T436 /workspace/coverage/default/1.chip_sw_aes_masking_off.684242877 Jul 23 07:46:39 PM PDT 24 Jul 23 07:52:02 PM PDT 24 2690502218 ps
T362 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3953789262 Jul 23 07:43:57 PM PDT 24 Jul 23 07:56:05 PM PDT 24 4205008160 ps
T437 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.972632692 Jul 23 07:35:37 PM PDT 24 Jul 23 08:52:04 PM PDT 24 15687562980 ps
T438 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3366594088 Jul 23 08:13:22 PM PDT 24 Jul 23 08:19:10 PM PDT 24 3342486224 ps
T439 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2972104429 Jul 23 07:47:16 PM PDT 24 Jul 23 08:10:19 PM PDT 24 9558733320 ps
T440 /workspace/coverage/default/1.chip_sw_kmac_idle.3587957963 Jul 23 07:48:03 PM PDT 24 Jul 23 07:53:05 PM PDT 24 3473963050 ps
T795 /workspace/coverage/default/5.chip_sw_all_escalation_resets.1218111148 Jul 23 08:05:32 PM PDT 24 Jul 23 08:20:15 PM PDT 24 4907239204 ps
T1091 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2778715220 Jul 23 08:06:12 PM PDT 24 Jul 23 08:17:37 PM PDT 24 4741608509 ps
T1092 /workspace/coverage/default/1.chip_sw_uart_smoketest.3641628169 Jul 23 07:51:54 PM PDT 24 Jul 23 07:57:01 PM PDT 24 2871596088 ps
T1093 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3631354816 Jul 23 07:51:35 PM PDT 24 Jul 23 07:56:34 PM PDT 24 3370278354 ps
T1094 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3762563103 Jul 23 08:00:21 PM PDT 24 Jul 23 08:03:27 PM PDT 24 2694439652 ps
T1095 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.197379040 Jul 23 07:44:36 PM PDT 24 Jul 23 08:50:07 PM PDT 24 15015074684 ps
T1096 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.1038237513 Jul 23 07:43:57 PM PDT 24 Jul 23 08:46:41 PM PDT 24 14834533724 ps
T1097 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.853378819 Jul 23 07:56:21 PM PDT 24 Jul 23 08:05:00 PM PDT 24 3960778896 ps
T1098 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2940965733 Jul 23 07:44:48 PM PDT 24 Jul 23 07:50:24 PM PDT 24 6611821216 ps
T1099 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.3725015222 Jul 23 07:57:45 PM PDT 24 Jul 23 08:02:05 PM PDT 24 2815987176 ps
T1100 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2505266097 Jul 23 08:02:53 PM PDT 24 Jul 23 08:12:34 PM PDT 24 3577124956 ps
T1101 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3837426968 Jul 23 07:36:36 PM PDT 24 Jul 23 07:59:30 PM PDT 24 7655653234 ps
T1102 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.3222186467 Jul 23 07:56:42 PM PDT 24 Jul 23 08:58:04 PM PDT 24 15202609032 ps
T1103 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.449518313 Jul 23 07:47:58 PM PDT 24 Jul 23 07:57:37 PM PDT 24 4947792400 ps
T1104 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1168676744 Jul 23 07:47:09 PM PDT 24 Jul 23 07:58:53 PM PDT 24 7686848635 ps
T1105 /workspace/coverage/default/0.chip_sw_kmac_entropy.3678066254 Jul 23 07:32:46 PM PDT 24 Jul 23 07:36:00 PM PDT 24 3440989448 ps
T37 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.321764899 Jul 23 07:55:22 PM PDT 24 Jul 23 08:01:25 PM PDT 24 5011738296 ps
T680 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3918101653 Jul 23 07:50:41 PM PDT 24 Jul 23 08:00:13 PM PDT 24 5062530623 ps
T193 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2804255999 Jul 23 07:36:42 PM PDT 24 Jul 23 07:38:28 PM PDT 24 1950897401 ps
T1106 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1635827460 Jul 23 07:51:43 PM PDT 24 Jul 23 09:04:17 PM PDT 24 25078819055 ps
T1107 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3558409021 Jul 23 08:10:55 PM PDT 24 Jul 23 08:18:09 PM PDT 24 3854658128 ps
T1108 /workspace/coverage/default/2.chip_sw_flash_crash_alert.1912076383 Jul 23 08:00:59 PM PDT 24 Jul 23 08:11:59 PM PDT 24 4187387592 ps
T1109 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.590631183 Jul 23 07:53:59 PM PDT 24 Jul 23 08:40:45 PM PDT 24 13299953270 ps
T805 /workspace/coverage/default/65.chip_sw_all_escalation_resets.1991074708 Jul 23 08:13:07 PM PDT 24 Jul 23 08:26:56 PM PDT 24 6311239652 ps
T1110 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1268390901 Jul 23 07:56:06 PM PDT 24 Jul 23 08:42:35 PM PDT 24 27419448959 ps
T1111 /workspace/coverage/default/0.chip_sw_edn_kat.3053390278 Jul 23 07:35:38 PM PDT 24 Jul 23 07:46:08 PM PDT 24 3329915386 ps
T1112 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.548800442 Jul 23 07:33:12 PM PDT 24 Jul 23 09:10:13 PM PDT 24 45884046620 ps
T1113 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1458776694 Jul 23 07:42:17 PM PDT 24 Jul 23 08:50:06 PM PDT 24 15887599380 ps
T1114 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.309037797 Jul 23 07:49:48 PM PDT 24 Jul 23 08:00:07 PM PDT 24 3916172824 ps
T1115 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.381606515 Jul 23 08:12:12 PM PDT 24 Jul 23 08:18:03 PM PDT 24 3233294752 ps
T1116 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1314605552 Jul 23 07:56:19 PM PDT 24 Jul 23 08:00:34 PM PDT 24 3331642402 ps
T1117 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.1350831050 Jul 23 07:50:23 PM PDT 24 Jul 23 08:11:26 PM PDT 24 7262246140 ps
T1118 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3905265155 Jul 23 07:40:38 PM PDT 24 Jul 23 07:44:49 PM PDT 24 2803498002 ps
T294 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2532581638 Jul 23 07:59:35 PM PDT 24 Jul 23 08:09:01 PM PDT 24 5211895877 ps
T1119 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1072505324 Jul 23 07:53:34 PM PDT 24 Jul 23 08:01:39 PM PDT 24 5845355880 ps
T763 /workspace/coverage/default/69.chip_sw_all_escalation_resets.479396557 Jul 23 08:13:10 PM PDT 24 Jul 23 08:26:18 PM PDT 24 5403538150 ps
T1120 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.3109312992 Jul 23 07:33:56 PM PDT 24 Jul 23 09:12:23 PM PDT 24 27682747200 ps
T1121 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3093661375 Jul 23 07:58:39 PM PDT 24 Jul 23 08:08:12 PM PDT 24 6386148872 ps
T270 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.921555692 Jul 23 07:45:38 PM PDT 24 Jul 23 07:58:52 PM PDT 24 6435622226 ps
T1122 /workspace/coverage/default/1.chip_sw_example_manufacturer.2364703701 Jul 23 07:42:22 PM PDT 24 Jul 23 07:46:53 PM PDT 24 3101283790 ps
T1123 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.1101979470 Jul 23 07:55:44 PM PDT 24 Jul 23 08:07:16 PM PDT 24 7165504900 ps
T1124 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2935530106 Jul 23 07:36:23 PM PDT 24 Jul 23 07:42:04 PM PDT 24 3111980720 ps
T698 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2647789710 Jul 23 07:46:09 PM PDT 24 Jul 23 07:51:15 PM PDT 24 3515103678 ps
T1125 /workspace/coverage/default/4.chip_tap_straps_testunlock0.3827411237 Jul 23 08:02:28 PM PDT 24 Jul 23 08:08:56 PM PDT 24 4872506619 ps
T211 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3388291011 Jul 23 07:51:39 PM PDT 24 Jul 23 07:56:28 PM PDT 24 3335060874 ps
T1126 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.2930017930 Jul 23 07:55:13 PM PDT 24 Jul 23 08:00:14 PM PDT 24 3063919536 ps
T1127 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.621735946 Jul 23 07:59:48 PM PDT 24 Jul 23 08:12:31 PM PDT 24 4585858232 ps
T1128 /workspace/coverage/default/2.chip_sw_aes_entropy.2072243904 Jul 23 07:56:47 PM PDT 24 Jul 23 08:01:04 PM PDT 24 2808827104 ps
T1129 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.3923950889 Jul 23 08:01:59 PM PDT 24 Jul 23 08:10:58 PM PDT 24 3993577946 ps
T331 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.818224199 Jul 23 07:43:16 PM PDT 24 Jul 23 08:01:41 PM PDT 24 5267214984 ps
T1130 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.6040532 Jul 23 07:56:31 PM PDT 24 Jul 23 08:18:18 PM PDT 24 9909132030 ps
T807 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3714845052 Jul 23 08:08:16 PM PDT 24 Jul 23 08:15:38 PM PDT 24 3919003416 ps
T771 /workspace/coverage/default/50.chip_sw_all_escalation_resets.2504723446 Jul 23 08:09:50 PM PDT 24 Jul 23 08:20:52 PM PDT 24 5065219484 ps
T1131 /workspace/coverage/default/1.rom_e2e_asm_init_prod.2922923821 Jul 23 07:56:38 PM PDT 24 Jul 23 09:06:59 PM PDT 24 15304195044 ps
T1132 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3088432722 Jul 23 07:44:03 PM PDT 24 Jul 23 08:52:51 PM PDT 24 14237174644 ps
T1133 /workspace/coverage/default/1.chip_sw_edn_auto_mode.1122795687 Jul 23 07:49:18 PM PDT 24 Jul 23 08:09:30 PM PDT 24 4361939248 ps
T1134 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3969945609 Jul 23 07:33:36 PM PDT 24 Jul 23 07:41:51 PM PDT 24 8632829072 ps
T131 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.4274467921 Jul 23 08:03:19 PM PDT 24 Jul 23 08:15:45 PM PDT 24 6793369814 ps
T54 /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.508711958 Jul 23 07:34:34 PM PDT 24 Jul 23 07:40:13 PM PDT 24 3232060766 ps
T235 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.593288862 Jul 23 07:57:02 PM PDT 24 Jul 23 09:11:14 PM PDT 24 16850135308 ps
T1135 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3518419911 Jul 23 07:46:12 PM PDT 24 Jul 23 07:54:01 PM PDT 24 7923956032 ps
T681 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1367649158 Jul 23 07:59:38 PM PDT 24 Jul 23 08:09:36 PM PDT 24 6044231507 ps
T1136 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.124426247 Jul 23 07:33:51 PM PDT 24 Jul 23 07:37:49 PM PDT 24 3152850541 ps
T449 /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.4082157696 Jul 23 07:43:47 PM PDT 24 Jul 23 08:40:56 PM PDT 24 31251308735 ps
T1137 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.3698849782 Jul 23 07:34:22 PM PDT 24 Jul 23 07:58:44 PM PDT 24 7458160160 ps
T416 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1341767522 Jul 23 07:52:20 PM PDT 24 Jul 23 08:19:40 PM PDT 24 22352959884 ps
T1138 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3382950961 Jul 23 08:03:07 PM PDT 24 Jul 23 08:23:32 PM PDT 24 10264265016 ps
T323 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.336305009 Jul 23 07:56:02 PM PDT 24 Jul 23 08:26:53 PM PDT 24 8818130844 ps
T1139 /workspace/coverage/default/0.chip_sw_example_rom.1053439084 Jul 23 07:32:17 PM PDT 24 Jul 23 07:34:15 PM PDT 24 1919631692 ps
T1140 /workspace/coverage/default/2.rom_e2e_static_critical.1392667837 Jul 23 08:06:47 PM PDT 24 Jul 23 09:12:35 PM PDT 24 17297965914 ps
T1141 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.729222577 Jul 23 07:50:27 PM PDT 24 Jul 23 07:55:41 PM PDT 24 3447788426 ps
T1142 /workspace/coverage/default/36.chip_sw_all_escalation_resets.4256531767 Jul 23 08:08:34 PM PDT 24 Jul 23 08:17:35 PM PDT 24 4480606440 ps
T1143 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.4133510382 Jul 23 07:36:59 PM PDT 24 Jul 23 07:44:19 PM PDT 24 3151437244 ps
T399 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.3310233795 Jul 23 07:50:20 PM PDT 24 Jul 23 07:55:21 PM PDT 24 2822244336 ps
T1144 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2323952530 Jul 23 07:49:55 PM PDT 24 Jul 23 08:01:45 PM PDT 24 9614542266 ps
T1145 /workspace/coverage/default/0.chip_sw_aes_masking_off.2765142186 Jul 23 07:35:58 PM PDT 24 Jul 23 07:40:18 PM PDT 24 3603927712 ps
T1146 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.4163868898 Jul 23 07:35:51 PM PDT 24 Jul 23 07:43:31 PM PDT 24 5749906170 ps
T1147 /workspace/coverage/default/1.chip_sw_kmac_entropy.3547054013 Jul 23 07:45:07 PM PDT 24 Jul 23 07:50:31 PM PDT 24 3435721480 ps
T816 /workspace/coverage/default/32.chip_sw_all_escalation_resets.3178472075 Jul 23 08:09:55 PM PDT 24 Jul 23 08:21:23 PM PDT 24 5254404994 ps
T1148 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2573632862 Jul 23 07:34:03 PM PDT 24 Jul 23 07:38:07 PM PDT 24 2338454540 ps
T301 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.2463994189 Jul 23 08:00:53 PM PDT 24 Jul 23 08:05:40 PM PDT 24 3081752466 ps
T336 /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.79283504 Jul 23 07:35:18 PM PDT 24 Jul 23 07:42:58 PM PDT 24 3593493352 ps
T812 /workspace/coverage/default/76.chip_sw_all_escalation_resets.3891485019 Jul 23 08:11:28 PM PDT 24 Jul 23 08:20:52 PM PDT 24 4578202924 ps
T1149 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2687071840 Jul 23 07:53:15 PM PDT 24 Jul 23 08:05:22 PM PDT 24 3667952618 ps
T1150 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2359981690 Jul 23 07:35:33 PM PDT 24 Jul 23 07:39:58 PM PDT 24 2736746015 ps
T1151 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.834875217 Jul 23 07:48:28 PM PDT 24 Jul 23 07:54:05 PM PDT 24 2502470000 ps
T1152 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.556144124 Jul 23 07:37:10 PM PDT 24 Jul 23 07:49:46 PM PDT 24 4060579800 ps
T1153 /workspace/coverage/default/1.chip_sw_hmac_oneshot.4124466460 Jul 23 07:49:15 PM PDT 24 Jul 23 07:53:41 PM PDT 24 2682041960 ps
T676 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2992325616 Jul 23 08:04:07 PM PDT 24 Jul 23 11:35:04 PM PDT 24 88373220441 ps
T686 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3501162913 Jul 23 07:32:25 PM PDT 24 Jul 23 07:34:06 PM PDT 24 2817265575 ps
T1154 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1123402492 Jul 23 07:36:10 PM PDT 24 Jul 23 07:39:21 PM PDT 24 2339808312 ps
T1155 /workspace/coverage/default/99.chip_sw_all_escalation_resets.2301204174 Jul 23 08:15:04 PM PDT 24 Jul 23 08:26:58 PM PDT 24 4661663464 ps
T171 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.1528551408 Jul 23 07:46:49 PM PDT 24 Jul 23 07:53:24 PM PDT 24 3587992123 ps
T1156 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3936359639 Jul 23 07:54:46 PM PDT 24 Jul 23 08:05:19 PM PDT 24 5733629955 ps
T1157 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.307886288 Jul 23 07:35:52 PM PDT 24 Jul 23 07:50:23 PM PDT 24 4792486360 ps
T1158 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1997242602 Jul 23 07:35:51 PM PDT 24 Jul 23 07:56:59 PM PDT 24 6926968232 ps
T1159 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1927950750 Jul 23 07:55:06 PM PDT 24 Jul 23 08:33:58 PM PDT 24 40404696050 ps
T1160 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3240730573 Jul 23 07:41:32 PM PDT 24 Jul 23 07:47:51 PM PDT 24 5162519996 ps
T1161 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.3938453376 Jul 23 08:02:49 PM PDT 24 Jul 23 08:06:18 PM PDT 24 3195013272 ps
T1162 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.558549181 Jul 23 07:36:35 PM PDT 24 Jul 23 07:50:29 PM PDT 24 7979724584 ps
T430 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3237520084 Jul 23 07:51:07 PM PDT 24 Jul 23 07:58:58 PM PDT 24 7028811390 ps
T10 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3479031404 Jul 23 07:46:35 PM PDT 24 Jul 23 07:51:50 PM PDT 24 2317481301 ps
T1163 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2067940985 Jul 23 07:45:59 PM PDT 24 Jul 23 07:47:50 PM PDT 24 2114966837 ps
T1164 /workspace/coverage/default/0.rom_e2e_asm_init_prod.1716317226 Jul 23 07:48:09 PM PDT 24 Jul 23 08:55:30 PM PDT 24 15682526191 ps
T1165 /workspace/coverage/default/2.chip_sw_example_concurrency.3482919508 Jul 23 08:02:30 PM PDT 24 Jul 23 08:07:01 PM PDT 24 2664558376 ps
T1166 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3170555262 Jul 23 07:55:19 PM PDT 24 Jul 23 08:03:28 PM PDT 24 4008370510 ps
T360 /workspace/coverage/default/0.chip_sw_aon_timer_irq.3787307468 Jul 23 07:32:06 PM PDT 24 Jul 23 07:37:45 PM PDT 24 3536545236 ps
T198 /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.3170859689 Jul 23 08:00:50 PM PDT 24 Jul 23 08:09:42 PM PDT 24 4760316248 ps
T1167 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2163848792 Jul 23 07:45:20 PM PDT 24 Jul 23 07:55:54 PM PDT 24 4591769304 ps
T772 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2902411314 Jul 23 08:09:10 PM PDT 24 Jul 23 08:16:21 PM PDT 24 4314247940 ps
T1168 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3303616420 Jul 23 07:45:31 PM PDT 24 Jul 23 08:11:10 PM PDT 24 7664738302 ps
T33 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1108011155 Jul 23 07:32:36 PM PDT 24 Jul 23 07:37:07 PM PDT 24 3539172142 ps
T1169 /workspace/coverage/default/0.rom_e2e_shutdown_output.979173456 Jul 23 07:42:32 PM PDT 24 Jul 23 08:50:01 PM PDT 24 27448247771 ps
T268 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.227432361 Jul 23 07:47:45 PM PDT 24 Jul 23 07:52:12 PM PDT 24 3128919176 ps
T1170 /workspace/coverage/default/0.chip_sw_gpio_smoketest.3641072279 Jul 23 07:41:47 PM PDT 24 Jul 23 07:47:34 PM PDT 24 3094661378 ps
T1171 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.466359273 Jul 23 07:36:45 PM PDT 24 Jul 23 07:43:46 PM PDT 24 4214229660 ps
T1172 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2881136264 Jul 23 08:06:51 PM PDT 24 Jul 23 08:14:02 PM PDT 24 4535031670 ps
T1173 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2572604042 Jul 23 07:44:33 PM PDT 24 Jul 23 09:32:42 PM PDT 24 22916929314 ps
T1174 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.111576819 Jul 23 08:13:28 PM PDT 24 Jul 23 08:19:31 PM PDT 24 4130958726 ps
T1175 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.2435827743 Jul 23 08:05:19 PM PDT 24 Jul 23 09:08:49 PM PDT 24 14888284500 ps
T1176 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3709387801 Jul 23 07:56:19 PM PDT 24 Jul 23 08:23:49 PM PDT 24 6685333092 ps
T813 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2310049859 Jul 23 08:13:13 PM PDT 24 Jul 23 08:19:51 PM PDT 24 3589269194 ps
T1177 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1883787462 Jul 23 07:36:21 PM PDT 24 Jul 23 07:54:55 PM PDT 24 5752227667 ps
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