| T1178 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx.2514405850 |
|
|
Jul 23 07:42:10 PM PDT 24 |
Jul 23 07:49:40 PM PDT 24 |
3630206088 ps |
| T328 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3803327305 |
|
|
Jul 23 07:54:29 PM PDT 24 |
Jul 23 08:06:58 PM PDT 24 |
5305504600 ps |
| T784 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.3125073737 |
|
|
Jul 23 07:53:06 PM PDT 24 |
Jul 23 08:06:43 PM PDT 24 |
4236150224 ps |
| T1179 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.106807495 |
|
|
Jul 23 07:49:51 PM PDT 24 |
Jul 23 08:03:32 PM PDT 24 |
4342147064 ps |
| T1180 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.754683960 |
|
|
Jul 23 07:54:47 PM PDT 24 |
Jul 23 07:56:46 PM PDT 24 |
2673100144 ps |
| T1181 |
/workspace/coverage/default/2.chip_tap_straps_dev.1822027206 |
|
|
Jul 23 07:59:20 PM PDT 24 |
Jul 23 08:02:33 PM PDT 24 |
2975020526 ps |
| T810 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3776159529 |
|
|
Jul 23 08:12:14 PM PDT 24 |
Jul 23 08:19:18 PM PDT 24 |
3616274760 ps |
| T1182 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3616007779 |
|
|
Jul 23 07:45:53 PM PDT 24 |
Jul 23 08:51:48 PM PDT 24 |
15549351136 ps |
| T1183 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.1671727173 |
|
|
Jul 23 07:54:04 PM PDT 24 |
Jul 23 08:03:36 PM PDT 24 |
7821647778 ps |
| T773 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.230845858 |
|
|
Jul 23 08:12:30 PM PDT 24 |
Jul 23 08:22:32 PM PDT 24 |
5252358944 ps |
| T1184 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.311980284 |
|
|
Jul 23 07:56:26 PM PDT 24 |
Jul 23 08:22:01 PM PDT 24 |
8480071832 ps |
| T1185 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.88475595 |
|
|
Jul 23 08:06:16 PM PDT 24 |
Jul 23 08:50:34 PM PDT 24 |
12946288184 ps |
| T1186 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1915587223 |
|
|
Jul 23 07:45:00 PM PDT 24 |
Jul 23 07:52:44 PM PDT 24 |
6380323441 ps |
| T750 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.2957930853 |
|
|
Jul 23 08:06:15 PM PDT 24 |
Jul 23 08:17:19 PM PDT 24 |
5587335660 ps |
| T764 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.3293335854 |
|
|
Jul 23 08:11:21 PM PDT 24 |
Jul 23 08:23:43 PM PDT 24 |
6044142134 ps |
| T1187 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.1882121940 |
|
|
Jul 23 08:10:51 PM PDT 24 |
Jul 23 08:20:08 PM PDT 24 |
4272940090 ps |
| T1188 |
/workspace/coverage/default/2.chip_sw_kmac_smoketest.1810048092 |
|
|
Jul 23 08:02:38 PM PDT 24 |
Jul 23 08:07:08 PM PDT 24 |
3121724338 ps |
| T774 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3509410028 |
|
|
Jul 23 08:12:44 PM PDT 24 |
Jul 23 08:19:54 PM PDT 24 |
3413119188 ps |
| T1189 |
/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.418053772 |
|
|
Jul 23 07:33:26 PM PDT 24 |
Jul 23 07:38:06 PM PDT 24 |
3016819608 ps |
| T1190 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3679736126 |
|
|
Jul 23 07:46:01 PM PDT 24 |
Jul 23 08:13:08 PM PDT 24 |
11658305898 ps |
| T1191 |
/workspace/coverage/default/1.chip_sw_example_concurrency.2526441541 |
|
|
Jul 23 07:41:13 PM PDT 24 |
Jul 23 07:44:23 PM PDT 24 |
2709884352 ps |
| T1192 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2334574150 |
|
|
Jul 23 07:47:01 PM PDT 24 |
Jul 23 08:51:15 PM PDT 24 |
16951264970 ps |
| T1193 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1377059047 |
|
|
Jul 23 08:05:36 PM PDT 24 |
Jul 23 08:14:12 PM PDT 24 |
5477352070 ps |
| T814 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1078955255 |
|
|
Jul 23 08:06:41 PM PDT 24 |
Jul 23 08:13:54 PM PDT 24 |
3492914762 ps |
| T1194 |
/workspace/coverage/default/4.chip_tap_straps_prod.3680967939 |
|
|
Jul 23 08:03:25 PM PDT 24 |
Jul 23 08:32:41 PM PDT 24 |
15665638643 ps |
| T785 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.1854597313 |
|
|
Jul 23 08:13:10 PM PDT 24 |
Jul 23 08:25:07 PM PDT 24 |
6217088490 ps |
| T759 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2362919196 |
|
|
Jul 23 08:06:09 PM PDT 24 |
Jul 23 08:13:44 PM PDT 24 |
3690586102 ps |
| T756 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.936385651 |
|
|
Jul 23 08:11:41 PM PDT 24 |
Jul 23 08:17:24 PM PDT 24 |
3999454960 ps |
| T107 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.3647712256 |
|
|
Jul 23 07:32:54 PM PDT 24 |
Jul 23 07:38:19 PM PDT 24 |
3440080072 ps |
| T389 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.147446682 |
|
|
Jul 23 08:07:18 PM PDT 24 |
Jul 23 08:15:07 PM PDT 24 |
3530140624 ps |
| T1195 |
/workspace/coverage/default/0.chip_sw_edn_sw_mode.2933835012 |
|
|
Jul 23 07:33:42 PM PDT 24 |
Jul 23 08:13:58 PM PDT 24 |
9352686140 ps |
| T1196 |
/workspace/coverage/default/2.chip_sival_flash_info_access.2886404450 |
|
|
Jul 23 07:52:30 PM PDT 24 |
Jul 23 07:56:57 PM PDT 24 |
3469659720 ps |
| T348 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.4119735855 |
|
|
Jul 23 07:53:42 PM PDT 24 |
Jul 23 08:03:58 PM PDT 24 |
4213347848 ps |
| T1197 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.222189 |
|
|
Jul 23 08:07:20 PM PDT 24 |
Jul 23 08:18:37 PM PDT 24 |
3539765640 ps |
| T1198 |
/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.3678626711 |
|
|
Jul 23 07:53:04 PM PDT 24 |
Jul 23 07:57:01 PM PDT 24 |
3052105000 ps |
| T1199 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1590441536 |
|
|
Jul 23 07:43:09 PM PDT 24 |
Jul 23 08:15:28 PM PDT 24 |
7996867736 ps |
| T66 |
/workspace/coverage/default/4.chip_tap_straps_rma.3969139597 |
|
|
Jul 23 08:02:53 PM PDT 24 |
Jul 23 08:05:32 PM PDT 24 |
2742204523 ps |
| T271 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3630725847 |
|
|
Jul 23 07:34:45 PM PDT 24 |
Jul 23 07:47:38 PM PDT 24 |
6552966150 ps |
| T767 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2922965997 |
|
|
Jul 23 08:09:19 PM PDT 24 |
Jul 23 08:15:58 PM PDT 24 |
3711514590 ps |
| T1200 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2836268963 |
|
|
Jul 23 08:02:54 PM PDT 24 |
Jul 23 08:13:26 PM PDT 24 |
6342317288 ps |
| T199 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.751628963 |
|
|
Jul 23 07:48:48 PM PDT 24 |
Jul 23 07:57:45 PM PDT 24 |
5153671192 ps |
| T1201 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1780290537 |
|
|
Jul 23 07:45:37 PM PDT 24 |
Jul 23 08:07:21 PM PDT 24 |
7403976068 ps |
| T1202 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1710657036 |
|
|
Jul 23 08:06:16 PM PDT 24 |
Jul 23 08:12:41 PM PDT 24 |
4028275640 ps |
| T1203 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.1246929472 |
|
|
Jul 23 07:42:02 PM PDT 24 |
Jul 23 07:49:31 PM PDT 24 |
3836274856 ps |
| T1204 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.2247418224 |
|
|
Jul 23 07:45:55 PM PDT 24 |
Jul 23 08:01:16 PM PDT 24 |
7862209428 ps |
| T326 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2967008566 |
|
|
Jul 23 07:42:08 PM PDT 24 |
Jul 23 07:57:19 PM PDT 24 |
5779103920 ps |
| T1205 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.499570301 |
|
|
Jul 23 07:58:01 PM PDT 24 |
Jul 23 09:18:50 PM PDT 24 |
14700426952 ps |
| T1206 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.103915306 |
|
|
Jul 23 07:34:15 PM PDT 24 |
Jul 23 07:46:00 PM PDT 24 |
5519747256 ps |
| T1207 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3976605124 |
|
|
Jul 23 07:57:15 PM PDT 24 |
Jul 23 08:05:59 PM PDT 24 |
6232185892 ps |
| T1208 |
/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.396026080 |
|
|
Jul 23 07:37:21 PM PDT 24 |
Jul 23 07:42:42 PM PDT 24 |
3719445654 ps |
| T1209 |
/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3685772900 |
|
|
Jul 23 07:34:17 PM PDT 24 |
Jul 23 07:43:31 PM PDT 24 |
3825344732 ps |
| T781 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2861865121 |
|
|
Jul 23 08:13:38 PM PDT 24 |
Jul 23 08:25:01 PM PDT 24 |
4949497300 ps |
| T798 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.857697205 |
|
|
Jul 23 08:12:41 PM PDT 24 |
Jul 23 08:23:24 PM PDT 24 |
5103622056 ps |
| T747 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.3257274101 |
|
|
Jul 23 08:12:54 PM PDT 24 |
Jul 23 08:22:27 PM PDT 24 |
5678654500 ps |
| T1210 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1882498168 |
|
|
Jul 23 07:53:18 PM PDT 24 |
Jul 23 08:00:47 PM PDT 24 |
5368756568 ps |
| T809 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.2961016195 |
|
|
Jul 23 08:14:51 PM PDT 24 |
Jul 23 08:30:23 PM PDT 24 |
5496935944 ps |
| T769 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.3273400654 |
|
|
Jul 23 08:07:49 PM PDT 24 |
Jul 23 08:19:12 PM PDT 24 |
4377622360 ps |
| T1211 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.462646615 |
|
|
Jul 23 07:54:00 PM PDT 24 |
Jul 23 07:59:43 PM PDT 24 |
3649339894 ps |
| T1212 |
/workspace/coverage/default/0.rom_e2e_static_critical.3111608817 |
|
|
Jul 23 07:44:56 PM PDT 24 |
Jul 23 08:44:25 PM PDT 24 |
17157985398 ps |
| T1213 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2456837960 |
|
|
Jul 23 08:02:32 PM PDT 24 |
Jul 23 08:13:37 PM PDT 24 |
4718216150 ps |
| T1214 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.860045984 |
|
|
Jul 23 07:45:55 PM PDT 24 |
Jul 23 07:58:14 PM PDT 24 |
5551788596 ps |
| T777 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2880346501 |
|
|
Jul 23 08:11:23 PM PDT 24 |
Jul 23 08:17:44 PM PDT 24 |
3540545872 ps |
| T1215 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.879546674 |
|
|
Jul 23 07:45:13 PM PDT 24 |
Jul 23 08:26:50 PM PDT 24 |
23919184044 ps |
| T106 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2759496385 |
|
|
Jul 23 07:35:51 PM PDT 24 |
Jul 23 08:05:36 PM PDT 24 |
24144838422 ps |
| T132 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1022937829 |
|
|
Jul 23 07:50:10 PM PDT 24 |
Jul 23 07:58:37 PM PDT 24 |
4963128384 ps |
| T317 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.3695970078 |
|
|
Jul 23 07:58:12 PM PDT 24 |
Jul 23 08:20:20 PM PDT 24 |
6238104048 ps |
| T1216 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1870673990 |
|
|
Jul 23 08:00:47 PM PDT 24 |
Jul 23 08:34:11 PM PDT 24 |
11820647680 ps |
| T1217 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3381573464 |
|
|
Jul 23 07:51:29 PM PDT 24 |
Jul 23 07:55:30 PM PDT 24 |
2919905038 ps |
| T52 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.59648534 |
|
|
Jul 23 07:54:04 PM PDT 24 |
Jul 23 07:58:19 PM PDT 24 |
3049813984 ps |
| T40 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.1798705031 |
|
|
Jul 23 08:07:11 PM PDT 24 |
Jul 23 08:14:01 PM PDT 24 |
4070017641 ps |
| T1218 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.2191076296 |
|
|
Jul 23 08:04:53 PM PDT 24 |
Jul 23 09:09:19 PM PDT 24 |
15246881544 ps |
| T161 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2238282228 |
|
|
Jul 23 07:53:32 PM PDT 24 |
Jul 23 08:03:19 PM PDT 24 |
4530401175 ps |
| T1219 |
/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.193276602 |
|
|
Jul 23 07:58:02 PM PDT 24 |
Jul 23 11:33:31 PM PDT 24 |
254520587392 ps |
| T1220 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.397037941 |
|
|
Jul 23 07:42:48 PM PDT 24 |
Jul 23 09:21:18 PM PDT 24 |
24263350030 ps |
| T269 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1756430892 |
|
|
Jul 23 07:33:57 PM PDT 24 |
Jul 23 07:53:50 PM PDT 24 |
11191075006 ps |
| T1221 |
/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.1216352890 |
|
|
Jul 23 07:56:29 PM PDT 24 |
Jul 23 09:04:01 PM PDT 24 |
14954738720 ps |
| T1222 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.679619027 |
|
|
Jul 23 07:52:45 PM PDT 24 |
Jul 23 08:00:21 PM PDT 24 |
6817305128 ps |
| T1223 |
/workspace/coverage/default/2.chip_sw_csrng_kat_test.3296846005 |
|
|
Jul 23 07:57:01 PM PDT 24 |
Jul 23 08:00:18 PM PDT 24 |
2304438394 ps |
| T1224 |
/workspace/coverage/default/0.chip_sw_otbn_randomness.572732835 |
|
|
Jul 23 07:32:26 PM PDT 24 |
Jul 23 07:47:35 PM PDT 24 |
5389069092 ps |
| T1225 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.819282622 |
|
|
Jul 23 08:01:16 PM PDT 24 |
Jul 23 08:04:48 PM PDT 24 |
2548911974 ps |
| T752 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.3190518276 |
|
|
Jul 23 08:07:35 PM PDT 24 |
Jul 23 08:18:05 PM PDT 24 |
5090868580 ps |
| T1226 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.2617459932 |
|
|
Jul 23 07:54:37 PM PDT 24 |
Jul 23 09:32:50 PM PDT 24 |
50941362858 ps |
| T1227 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.3885723521 |
|
|
Jul 23 07:53:56 PM PDT 24 |
Jul 23 07:55:41 PM PDT 24 |
2592324273 ps |
| T1228 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.939619890 |
|
|
Jul 23 07:53:14 PM PDT 24 |
Jul 23 08:11:37 PM PDT 24 |
7691670764 ps |
| T757 |
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1670280914 |
|
|
Jul 23 08:08:51 PM PDT 24 |
Jul 23 08:16:17 PM PDT 24 |
4496596556 ps |
| T758 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.62556628 |
|
|
Jul 23 08:13:17 PM PDT 24 |
Jul 23 08:24:12 PM PDT 24 |
4371556744 ps |
| T1229 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2675823443 |
|
|
Jul 23 08:01:48 PM PDT 24 |
Jul 23 08:26:40 PM PDT 24 |
7397645429 ps |
| T736 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.234351701 |
|
|
Jul 23 08:10:22 PM PDT 24 |
Jul 23 08:21:28 PM PDT 24 |
6354342622 ps |
| T737 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.1856913235 |
|
|
Jul 23 08:10:02 PM PDT 24 |
Jul 23 08:18:53 PM PDT 24 |
5128035032 ps |
| T1230 |
/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.1380750901 |
|
|
Jul 23 08:02:26 PM PDT 24 |
Jul 23 08:06:25 PM PDT 24 |
2632640320 ps |
| T1231 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2699029296 |
|
|
Jul 23 07:51:57 PM PDT 24 |
Jul 23 08:01:22 PM PDT 24 |
7076916600 ps |
| T1232 |
/workspace/coverage/default/1.chip_sw_flash_crash_alert.3420726554 |
|
|
Jul 23 07:51:00 PM PDT 24 |
Jul 23 08:01:48 PM PDT 24 |
5487376700 ps |
| T797 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.3582660080 |
|
|
Jul 23 08:14:12 PM PDT 24 |
Jul 23 08:23:47 PM PDT 24 |
5114483328 ps |
| T1233 |
/workspace/coverage/default/1.chip_sw_otbn_randomness.3375047579 |
|
|
Jul 23 07:46:08 PM PDT 24 |
Jul 23 08:05:02 PM PDT 24 |
5172441552 ps |
| T775 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2908343959 |
|
|
Jul 23 08:12:30 PM PDT 24 |
Jul 23 08:21:16 PM PDT 24 |
3592901940 ps |
| T1234 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.1841454937 |
|
|
Jul 23 07:59:45 PM PDT 24 |
Jul 23 08:04:30 PM PDT 24 |
2980999944 ps |
| T1235 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.270858150 |
|
|
Jul 23 08:00:39 PM PDT 24 |
Jul 23 09:12:54 PM PDT 24 |
24742681723 ps |
| T1236 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.722602118 |
|
|
Jul 23 08:05:16 PM PDT 24 |
Jul 23 08:11:30 PM PDT 24 |
3760024076 ps |
| T1237 |
/workspace/coverage/default/2.chip_sw_edn_kat.3047886926 |
|
|
Jul 23 07:56:54 PM PDT 24 |
Jul 23 08:07:09 PM PDT 24 |
3366040780 ps |
| T1238 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2358883727 |
|
|
Jul 23 07:45:38 PM PDT 24 |
Jul 23 07:49:39 PM PDT 24 |
2946851954 ps |
| T105 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1890042279 |
|
|
Jul 23 07:50:48 PM PDT 24 |
Jul 23 07:58:34 PM PDT 24 |
3433491358 ps |
| T1239 |
/workspace/coverage/default/2.chip_sw_alert_handler_escalation.3615377472 |
|
|
Jul 23 07:57:11 PM PDT 24 |
Jul 23 08:07:20 PM PDT 24 |
4359515368 ps |
| T1240 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.455526440 |
|
|
Jul 23 07:34:53 PM PDT 24 |
Jul 23 07:55:54 PM PDT 24 |
6704862040 ps |
| T1241 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.2675621880 |
|
|
Jul 23 07:33:42 PM PDT 24 |
Jul 23 07:41:01 PM PDT 24 |
5730747312 ps |
| T1242 |
/workspace/coverage/default/0.chip_sw_aes_entropy.1156732962 |
|
|
Jul 23 07:36:32 PM PDT 24 |
Jul 23 07:39:56 PM PDT 24 |
2514310760 ps |
| T1243 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.881665927 |
|
|
Jul 23 07:48:14 PM PDT 24 |
Jul 23 08:51:57 PM PDT 24 |
13791928496 ps |
| T172 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2636109412 |
|
|
Jul 23 07:56:34 PM PDT 24 |
Jul 23 08:02:17 PM PDT 24 |
4125974536 ps |
| T1244 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.282601869 |
|
|
Jul 23 08:04:50 PM PDT 24 |
Jul 23 08:13:59 PM PDT 24 |
7418653215 ps |
| T1245 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.2554465424 |
|
|
Jul 23 08:02:29 PM PDT 24 |
Jul 23 08:09:09 PM PDT 24 |
5376901460 ps |
| T1246 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.1527616897 |
|
|
Jul 23 08:14:16 PM PDT 24 |
Jul 23 08:26:32 PM PDT 24 |
6025705750 ps |
| T1247 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3842936437 |
|
|
Jul 23 07:36:54 PM PDT 24 |
Jul 23 07:43:41 PM PDT 24 |
3539173776 ps |
| T1248 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2754037489 |
|
|
Jul 23 07:42:41 PM PDT 24 |
Jul 23 07:53:06 PM PDT 24 |
4233662678 ps |
| T1249 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.9418263 |
|
|
Jul 23 08:12:42 PM PDT 24 |
Jul 23 08:25:25 PM PDT 24 |
4610099718 ps |
| T746 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.1244845521 |
|
|
Jul 23 08:07:31 PM PDT 24 |
Jul 23 08:21:04 PM PDT 24 |
5535728704 ps |
| T1250 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.2482611169 |
|
|
Jul 23 07:52:23 PM PDT 24 |
Jul 23 07:57:22 PM PDT 24 |
3428429480 ps |
| T1251 |
/workspace/coverage/default/2.chip_sw_kmac_entropy.966752647 |
|
|
Jul 23 08:05:31 PM PDT 24 |
Jul 23 08:09:35 PM PDT 24 |
3272362616 ps |
| T1252 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.2355413825 |
|
|
Jul 23 07:43:04 PM PDT 24 |
Jul 23 07:47:08 PM PDT 24 |
2447696538 ps |
| T544 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2847491761 |
|
|
Jul 23 07:36:46 PM PDT 24 |
Jul 23 07:46:46 PM PDT 24 |
4840398834 ps |
| T801 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2936333726 |
|
|
Jul 23 08:06:14 PM PDT 24 |
Jul 23 08:13:30 PM PDT 24 |
3841043212 ps |
| T1253 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2382240239 |
|
|
Jul 23 07:59:42 PM PDT 24 |
Jul 23 08:03:44 PM PDT 24 |
3302279932 ps |
| T1254 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1514408419 |
|
|
Jul 23 07:55:58 PM PDT 24 |
Jul 23 09:05:36 PM PDT 24 |
19039345347 ps |
| T1255 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.2823120498 |
|
|
Jul 23 08:09:08 PM PDT 24 |
Jul 23 08:21:05 PM PDT 24 |
5222626108 ps |
| T1256 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.1925079876 |
|
|
Jul 23 08:06:00 PM PDT 24 |
Jul 23 08:24:49 PM PDT 24 |
13253466449 ps |
| T1257 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.2555190368 |
|
|
Jul 23 07:59:37 PM PDT 24 |
Jul 23 08:06:48 PM PDT 24 |
5579616092 ps |
| T133 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1751535468 |
|
|
Jul 23 08:02:27 PM PDT 24 |
Jul 23 08:13:10 PM PDT 24 |
5139503746 ps |
| T1258 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1392289045 |
|
|
Jul 23 07:46:09 PM PDT 24 |
Jul 23 07:57:00 PM PDT 24 |
4269011325 ps |
| T28 |
/workspace/coverage/default/2.chip_sw_gpio.1213640609 |
|
|
Jul 23 08:06:39 PM PDT 24 |
Jul 23 08:15:19 PM PDT 24 |
4703763448 ps |
| T1259 |
/workspace/coverage/default/1.chip_tap_straps_dev.2391537697 |
|
|
Jul 23 07:49:23 PM PDT 24 |
Jul 23 07:52:32 PM PDT 24 |
2976905772 ps |
| T236 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3437388878 |
|
|
Jul 23 07:35:07 PM PDT 24 |
Jul 23 08:42:57 PM PDT 24 |
13919820380 ps |
| T1260 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.661923344 |
|
|
Jul 23 07:37:09 PM PDT 24 |
Jul 23 07:46:52 PM PDT 24 |
5546615286 ps |
| T744 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.920726813 |
|
|
Jul 23 08:14:36 PM PDT 24 |
Jul 23 08:22:44 PM PDT 24 |
3740667008 ps |
| T1261 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.660558697 |
|
|
Jul 23 07:32:28 PM PDT 24 |
Jul 23 07:44:27 PM PDT 24 |
5752697869 ps |
| T1262 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.68152683 |
|
|
Jul 23 08:03:28 PM PDT 24 |
Jul 23 08:12:31 PM PDT 24 |
7822293628 ps |
| T1263 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.2592796407 |
|
|
Jul 23 07:40:28 PM PDT 24 |
Jul 23 07:45:54 PM PDT 24 |
5369868088 ps |
| T799 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2284944046 |
|
|
Jul 23 08:11:51 PM PDT 24 |
Jul 23 08:19:12 PM PDT 24 |
3278623048 ps |
| T1264 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.1958155061 |
|
|
Jul 23 07:46:17 PM PDT 24 |
Jul 23 07:50:40 PM PDT 24 |
3211941645 ps |
| T1265 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1862582783 |
|
|
Jul 23 08:05:22 PM PDT 24 |
Jul 23 08:12:26 PM PDT 24 |
3256917084 ps |
| T1266 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3538463858 |
|
|
Jul 23 07:34:12 PM PDT 24 |
Jul 23 08:45:26 PM PDT 24 |
21040124521 ps |
| T302 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.4208193565 |
|
|
Jul 23 08:00:46 PM PDT 24 |
Jul 23 08:05:39 PM PDT 24 |
2461176596 ps |
| T386 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.827652018 |
|
|
Jul 23 07:50:32 PM PDT 24 |
Jul 23 07:59:08 PM PDT 24 |
5739588744 ps |
| T815 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.2342418667 |
|
|
Jul 23 08:07:54 PM PDT 24 |
Jul 23 08:17:22 PM PDT 24 |
5039917160 ps |
| T1267 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1167557435 |
|
|
Jul 23 07:59:08 PM PDT 24 |
Jul 23 08:35:26 PM PDT 24 |
21780415062 ps |
| T1268 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3820506966 |
|
|
Jul 23 08:06:28 PM PDT 24 |
Jul 23 08:11:47 PM PDT 24 |
3542915846 ps |
| T1269 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3199916494 |
|
|
Jul 23 08:07:37 PM PDT 24 |
Jul 23 08:14:00 PM PDT 24 |
3509394936 ps |
| T1270 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3742273325 |
|
|
Jul 23 07:59:44 PM PDT 24 |
Jul 23 08:10:34 PM PDT 24 |
5742329796 ps |
| T1271 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1885222850 |
|
|
Jul 23 07:34:08 PM PDT 24 |
Jul 23 07:45:36 PM PDT 24 |
4399628472 ps |
| T1272 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3880555681 |
|
|
Jul 23 07:36:02 PM PDT 24 |
Jul 23 07:43:43 PM PDT 24 |
7959468856 ps |
| T727 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.3413116487 |
|
|
Jul 23 07:53:03 PM PDT 24 |
Jul 23 07:56:45 PM PDT 24 |
2476321610 ps |
| T1273 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.366852012 |
|
|
Jul 23 07:33:53 PM PDT 24 |
Jul 23 08:24:08 PM PDT 24 |
11849330166 ps |
| T1274 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3117754972 |
|
|
Jul 23 07:36:14 PM PDT 24 |
Jul 23 08:47:38 PM PDT 24 |
24943141563 ps |
| T233 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1741489527 |
|
|
Jul 23 07:35:24 PM PDT 24 |
Jul 23 08:06:07 PM PDT 24 |
8354067532 ps |
| T163 |
/workspace/coverage/default/1.chip_jtag_mem_access.73887806 |
|
|
Jul 23 07:42:49 PM PDT 24 |
Jul 23 08:09:35 PM PDT 24 |
13538066545 ps |
| T1275 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.277848627 |
|
|
Jul 23 07:36:56 PM PDT 24 |
Jul 23 07:44:41 PM PDT 24 |
4052056900 ps |
| T1276 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.3711492389 |
|
|
Jul 23 07:35:49 PM PDT 24 |
Jul 23 07:45:49 PM PDT 24 |
4315339136 ps |
| T1277 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3391391075 |
|
|
Jul 23 07:52:41 PM PDT 24 |
Jul 23 08:01:31 PM PDT 24 |
5750594082 ps |
| T1278 |
/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.2161874407 |
|
|
Jul 23 08:05:04 PM PDT 24 |
Jul 23 08:14:57 PM PDT 24 |
6245973089 ps |
| T303 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2127008430 |
|
|
Jul 23 07:37:28 PM PDT 24 |
Jul 23 07:41:34 PM PDT 24 |
2688201901 ps |
| T778 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.1249033887 |
|
|
Jul 23 08:10:59 PM PDT 24 |
Jul 23 08:21:07 PM PDT 24 |
4573330300 ps |
| T1279 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1449660934 |
|
|
Jul 23 07:45:45 PM PDT 24 |
Jul 23 08:03:02 PM PDT 24 |
10010849010 ps |
| T1280 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1320038987 |
|
|
Jul 23 07:43:55 PM PDT 24 |
Jul 23 08:59:45 PM PDT 24 |
15265037712 ps |
| T1281 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.3544441282 |
|
|
Jul 23 07:54:38 PM PDT 24 |
Jul 23 08:12:11 PM PDT 24 |
7856999635 ps |
| T1282 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3233923663 |
|
|
Jul 23 07:59:11 PM PDT 24 |
Jul 23 08:10:23 PM PDT 24 |
3660001576 ps |
| T1283 |
/workspace/coverage/default/1.chip_sw_hmac_smoketest.2893165799 |
|
|
Jul 23 07:52:40 PM PDT 24 |
Jul 23 08:00:27 PM PDT 24 |
3851155000 ps |
| T1284 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1692619090 |
|
|
Jul 23 08:13:26 PM PDT 24 |
Jul 23 08:20:04 PM PDT 24 |
3120964104 ps |
| T1285 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.4096273983 |
|
|
Jul 23 07:47:19 PM PDT 24 |
Jul 23 08:41:06 PM PDT 24 |
11874862476 ps |
| T1286 |
/workspace/coverage/default/0.chip_sw_hmac_multistream.133359429 |
|
|
Jul 23 07:35:12 PM PDT 24 |
Jul 23 08:15:50 PM PDT 24 |
9052918852 ps |
| T162 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.2730229566 |
|
|
Jul 23 08:07:07 PM PDT 24 |
Jul 23 08:18:50 PM PDT 24 |
6682489736 ps |
| T1287 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.133473904 |
|
|
Jul 23 07:42:59 PM PDT 24 |
Jul 23 07:52:16 PM PDT 24 |
4216251668 ps |
| T1288 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3396073107 |
|
|
Jul 23 07:59:58 PM PDT 24 |
Jul 23 08:04:34 PM PDT 24 |
2625039232 ps |
| T431 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2646699953 |
|
|
Jul 23 07:35:38 PM PDT 24 |
Jul 23 08:04:27 PM PDT 24 |
21662877900 ps |
| T1289 |
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1147249288 |
|
|
Jul 23 08:08:53 PM PDT 24 |
Jul 23 08:16:11 PM PDT 24 |
3322303560 ps |
| T1290 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.1706459383 |
|
|
Jul 23 07:42:56 PM PDT 24 |
Jul 23 09:27:58 PM PDT 24 |
23560919476 ps |
| T1291 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3958224073 |
|
|
Jul 23 07:36:16 PM PDT 24 |
Jul 23 07:38:15 PM PDT 24 |
2185216450 ps |
| T1292 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.976432842 |
|
|
Jul 23 07:40:46 PM PDT 24 |
Jul 23 07:44:32 PM PDT 24 |
2522471880 ps |
| T1293 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.313843484 |
|
|
Jul 23 07:37:35 PM PDT 24 |
Jul 23 07:48:53 PM PDT 24 |
4132894963 ps |
| T1294 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.591751546 |
|
|
Jul 23 07:33:11 PM PDT 24 |
Jul 23 07:46:39 PM PDT 24 |
11632599190 ps |
| T1295 |
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3985127531 |
|
|
Jul 23 08:04:00 PM PDT 24 |
Jul 23 08:13:44 PM PDT 24 |
5998245282 ps |
| T1296 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2217521194 |
|
|
Jul 23 08:04:09 PM PDT 24 |
Jul 23 08:12:51 PM PDT 24 |
3898890368 ps |
| T1297 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3910118688 |
|
|
Jul 23 07:44:08 PM PDT 24 |
Jul 23 08:40:06 PM PDT 24 |
11115580950 ps |
| T1298 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.4129799431 |
|
|
Jul 23 07:51:33 PM PDT 24 |
Jul 23 07:53:26 PM PDT 24 |
2394702697 ps |
| T381 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.490314424 |
|
|
Jul 23 07:33:24 PM PDT 24 |
Jul 23 07:46:57 PM PDT 24 |
5495703104 ps |
| T1299 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.600145900 |
|
|
Jul 23 07:59:56 PM PDT 24 |
Jul 23 08:06:06 PM PDT 24 |
2960282188 ps |
| T766 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1574242306 |
|
|
Jul 23 08:11:30 PM PDT 24 |
Jul 23 08:18:23 PM PDT 24 |
4414925160 ps |
| T1300 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.2628923441 |
|
|
Jul 23 07:35:05 PM PDT 24 |
Jul 23 07:38:31 PM PDT 24 |
2682020664 ps |
| T1301 |
/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1650663529 |
|
|
Jul 23 08:06:15 PM PDT 24 |
Jul 23 08:17:52 PM PDT 24 |
3898187448 ps |
| T1302 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.832071878 |
|
|
Jul 23 07:45:14 PM PDT 24 |
Jul 23 09:33:49 PM PDT 24 |
23541063550 ps |
| T1303 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.1906940098 |
|
|
Jul 23 07:59:50 PM PDT 24 |
Jul 23 08:21:42 PM PDT 24 |
6154665030 ps |
| T721 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.927599464 |
|
|
Jul 23 07:34:09 PM PDT 24 |
Jul 23 07:47:16 PM PDT 24 |
4607405000 ps |
| T730 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.912159652 |
|
|
Jul 23 07:39:15 PM PDT 24 |
Jul 23 08:12:33 PM PDT 24 |
11109382620 ps |
| T1304 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.2478668098 |
|
|
Jul 23 07:34:29 PM PDT 24 |
Jul 23 07:53:10 PM PDT 24 |
5924260494 ps |
| T1305 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2727508747 |
|
|
Jul 23 08:08:11 PM PDT 24 |
Jul 23 08:15:49 PM PDT 24 |
4041221500 ps |
| T1306 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1469889135 |
|
|
Jul 23 07:50:22 PM PDT 24 |
Jul 23 07:59:59 PM PDT 24 |
4217258920 ps |
| T1307 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3714766502 |
|
|
Jul 23 08:06:01 PM PDT 24 |
Jul 23 08:16:10 PM PDT 24 |
4415324794 ps |
| T164 |
/workspace/coverage/default/0.chip_jtag_csr_rw.1776495526 |
|
|
Jul 23 07:27:27 PM PDT 24 |
Jul 23 07:32:24 PM PDT 24 |
4738004920 ps |
| T1308 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.941119895 |
|
|
Jul 23 08:01:24 PM PDT 24 |
Jul 23 08:05:42 PM PDT 24 |
2573445000 ps |
| T256 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.627919597 |
|
|
Jul 23 08:13:49 PM PDT 24 |
Jul 23 08:21:00 PM PDT 24 |
4071679484 ps |
| T306 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2342609497 |
|
|
Jul 23 08:08:13 PM PDT 24 |
Jul 23 08:14:17 PM PDT 24 |
4173874752 ps |
| T307 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3190653808 |
|
|
Jul 23 08:05:00 PM PDT 24 |
Jul 23 08:20:16 PM PDT 24 |
11013197833 ps |
| T308 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.1456178108 |
|
|
Jul 23 07:56:21 PM PDT 24 |
Jul 23 08:15:10 PM PDT 24 |
5380959960 ps |
| T309 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3814019443 |
|
|
Jul 23 07:56:20 PM PDT 24 |
Jul 23 08:13:23 PM PDT 24 |
6456301011 ps |
| T310 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1070141575 |
|
|
Jul 23 07:38:08 PM PDT 24 |
Jul 23 08:09:15 PM PDT 24 |
7552439912 ps |
| T311 |
/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3960705040 |
|
|
Jul 23 07:52:40 PM PDT 24 |
Jul 23 07:56:25 PM PDT 24 |
3088047400 ps |
| T312 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2199671056 |
|
|
Jul 23 08:05:43 PM PDT 24 |
Jul 23 08:10:49 PM PDT 24 |
2617568266 ps |
| T34 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2137685829 |
|
|
Jul 23 07:44:45 PM PDT 24 |
Jul 23 07:49:28 PM PDT 24 |
3076582160 ps |
| T313 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1128199181 |
|
|
Jul 23 07:34:18 PM PDT 24 |
Jul 23 07:48:26 PM PDT 24 |
4856101276 ps |
| T314 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1588902046 |
|
|
Jul 23 07:44:54 PM PDT 24 |
Jul 23 07:54:55 PM PDT 24 |
4483131784 ps |
| T49 |
/workspace/coverage/default/1.chip_sw_alert_test.3639019530 |
|
|
Jul 23 07:47:01 PM PDT 24 |
Jul 23 07:54:04 PM PDT 24 |
3436853006 ps |
| T1309 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3297645297 |
|
|
Jul 23 07:56:39 PM PDT 24 |
Jul 23 08:17:05 PM PDT 24 |
9888320960 ps |
| T1310 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2587513843 |
|
|
Jul 23 08:08:03 PM PDT 24 |
Jul 23 09:10:47 PM PDT 24 |
14620979620 ps |
| T1311 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.994887179 |
|
|
Jul 23 07:35:11 PM PDT 24 |
Jul 23 08:14:46 PM PDT 24 |
20624594977 ps |
| T1312 |
/workspace/coverage/default/2.chip_sw_aes_idle.1541469002 |
|
|
Jul 23 07:56:01 PM PDT 24 |
Jul 23 08:01:52 PM PDT 24 |
3464093870 ps |
| T1313 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3052373106 |
|
|
Jul 23 07:33:12 PM PDT 24 |
Jul 23 07:52:32 PM PDT 24 |
10628730162 ps |
| T1314 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2547845825 |
|
|
Jul 23 07:55:56 PM PDT 24 |
Jul 23 08:03:35 PM PDT 24 |
18325381072 ps |
| T1315 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.3524981806 |
|
|
Jul 23 07:43:32 PM PDT 24 |
Jul 23 08:40:38 PM PDT 24 |
10816556158 ps |
| T1316 |
/workspace/coverage/default/2.chip_sw_uart_smoketest.747854763 |
|
|
Jul 23 08:01:44 PM PDT 24 |
Jul 23 08:06:50 PM PDT 24 |
2770855080 ps |
| T1317 |
/workspace/coverage/default/2.rom_raw_unlock.3082226164 |
|
|
Jul 23 08:01:53 PM PDT 24 |
Jul 23 08:05:35 PM PDT 24 |
4520984481 ps |
| T1318 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1031190114 |
|
|
Jul 23 08:04:16 PM PDT 24 |
Jul 23 08:17:49 PM PDT 24 |
4644231488 ps |
| T1319 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.4204624110 |
|
|
Jul 23 07:48:02 PM PDT 24 |
Jul 23 08:07:48 PM PDT 24 |
6174222280 ps |
| T1320 |
/workspace/coverage/default/0.chip_sw_flash_init.1566839134 |
|
|
Jul 23 07:35:12 PM PDT 24 |
Jul 23 08:13:56 PM PDT 24 |
25011418542 ps |
| T1321 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2852334459 |
|
|
Jul 23 08:06:22 PM PDT 24 |
Jul 23 08:12:14 PM PDT 24 |
3073314104 ps |
| T1322 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.538882794 |
|
|
Jul 23 08:01:13 PM PDT 24 |
Jul 23 08:07:54 PM PDT 24 |
4898153768 ps |
| T1323 |
/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3780122347 |
|
|
Jul 23 08:05:51 PM PDT 24 |
Jul 23 08:32:16 PM PDT 24 |
8422572840 ps |
| T1324 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.3108706401 |
|
|
Jul 23 07:53:31 PM PDT 24 |
Jul 23 08:04:12 PM PDT 24 |
4412119064 ps |
| T1325 |
/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.2583511469 |
|
|
Jul 23 07:45:34 PM PDT 24 |
Jul 23 07:55:16 PM PDT 24 |
5066833998 ps |
| T432 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1153403564 |
|
|
Jul 23 07:58:22 PM PDT 24 |
Jul 23 08:06:39 PM PDT 24 |
7298145284 ps |
| T1326 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.4099689569 |
|
|
Jul 23 07:36:41 PM PDT 24 |
Jul 23 11:00:47 PM PDT 24 |
66067756844 ps |
| T1327 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3468883586 |
|
|
Jul 23 07:33:55 PM PDT 24 |
Jul 23 07:45:13 PM PDT 24 |
4471823604 ps |
| T390 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.3087429932 |
|
|
Jul 23 08:06:10 PM PDT 24 |
Jul 23 08:18:52 PM PDT 24 |
5267425736 ps |
| T1328 |
/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.2543865094 |
|
|
Jul 23 08:08:56 PM PDT 24 |
Jul 23 08:51:23 PM PDT 24 |
13069743240 ps |
| T1329 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.1735499005 |
|
|
Jul 23 07:35:03 PM PDT 24 |
Jul 23 07:43:08 PM PDT 24 |
5590185020 ps |
| T1330 |
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.2369854734 |
|
|
Jul 23 08:05:03 PM PDT 24 |
Jul 23 09:26:49 PM PDT 24 |
21970915926 ps |
| T1331 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3715289093 |
|
|
Jul 23 07:44:10 PM PDT 24 |
Jul 23 09:30:18 PM PDT 24 |
24227924984 ps |
| T1332 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3400852970 |
|
|
Jul 23 07:48:46 PM PDT 24 |
Jul 23 08:02:53 PM PDT 24 |
7063552606 ps |
| T789 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.993754884 |
|
|
Jul 23 08:11:12 PM PDT 24 |
Jul 23 08:17:25 PM PDT 24 |
3910200160 ps |
| T1333 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1196509588 |
|
|
Jul 23 07:56:32 PM PDT 24 |
Jul 23 08:09:42 PM PDT 24 |
4982625692 ps |
| T1334 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.1752198239 |
|
|
Jul 23 07:53:08 PM PDT 24 |
Jul 23 07:57:57 PM PDT 24 |
3359678560 ps |
| T50 |
/workspace/coverage/default/0.chip_sw_alert_test.2138313108 |
|
|
Jul 23 07:32:32 PM PDT 24 |
Jul 23 07:37:14 PM PDT 24 |
2722471048 ps |
| T660 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2701410943 |
|
|
Jul 23 07:53:08 PM PDT 24 |
Jul 23 08:05:44 PM PDT 24 |
5460417848 ps |
| T1335 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.2366394635 |
|
|
Jul 23 08:04:21 PM PDT 24 |
Jul 23 08:16:57 PM PDT 24 |
4904259180 ps |
| T1336 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.36761396 |
|
|
Jul 23 07:41:31 PM PDT 24 |
Jul 23 08:48:10 PM PDT 24 |
15429554500 ps |
| T1337 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3617883153 |
|
|
Jul 23 07:52:57 PM PDT 24 |
Jul 23 08:04:15 PM PDT 24 |
5198103179 ps |
| T1338 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.185493015 |
|
|
Jul 23 07:44:31 PM PDT 24 |
Jul 23 07:50:05 PM PDT 24 |
3461813016 ps |
| T1339 |
/workspace/coverage/default/1.chip_sw_hmac_enc.2681121591 |
|
|
Jul 23 07:49:18 PM PDT 24 |
Jul 23 07:53:26 PM PDT 24 |
3209284280 ps |
| T1340 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.512119155 |
|
|
Jul 23 07:58:46 PM PDT 24 |
Jul 23 08:03:42 PM PDT 24 |
2631014732 ps |
| T1341 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.159834228 |
|
|
Jul 23 07:57:12 PM PDT 24 |
Jul 23 08:16:12 PM PDT 24 |
7147835004 ps |
| T1342 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.3972166095 |
|
|
Jul 23 07:37:07 PM PDT 24 |
Jul 23 07:43:22 PM PDT 24 |
3107876874 ps |
| T745 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3534397380 |
|
|
Jul 23 07:56:49 PM PDT 24 |
Jul 23 08:05:07 PM PDT 24 |
3882930872 ps |
| T1343 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4232502085 |
|
|
Jul 23 08:01:48 PM PDT 24 |
Jul 23 08:21:04 PM PDT 24 |
6912897746 ps |
| T1344 |
/workspace/coverage/default/1.rom_e2e_shutdown_output.2559807513 |
|
|
Jul 23 07:56:34 PM PDT 24 |
Jul 23 08:51:44 PM PDT 24 |
25428865191 ps |
| T213 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1335456611 |
|
|
Jul 23 07:35:13 PM PDT 24 |
Jul 23 09:19:55 PM PDT 24 |
44315521429 ps |