Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3685374	1			T74	2534		T75	277		T76	289
values[2]	719232	1			T74	301		T75	109		T76	61
values[3]	99868	1			T74	53		T75	43		T76	4
values[4]	54173	1			T74	70		T75	1		T254	1
values[5]	36756	1			T74	77		T254	1		T438	13
values[6]	27482	1			T74	68		T254	1		T438	13
values[7]	22201	1			T74	56		T254	1		T438	13
values[8]	19139	1			T74	55		T254	1		T438	13
values[9]	16704	1			T74	51		T254	1		T438	13
values[10]	15191	1			T74	69		T254	1		T438	13
values[11]	14216	1			T74	79		T254	1		T438	13
values[12]	13522	1			T74	87		T254	1		T438	13
values[13]	12615	1			T74	57		T254	1		T438	13
values[14]	12070	1			T74	83		T254	1		T438	14
values[15]	11722	1			T74	39		T254	1		T438	13
values[16]	11231	1			T74	30		T254	1		T438	13
values[17]	10806	1			T74	34		T254	1		T438	13
values[18]	10419	1			T74	44		T254	1		T438	13
values[19]	10151	1			T74	50		T254	1		T438	13
values[20]	9732	1			T74	53		T254	1		T438	13
values[21]	9567	1			T74	44		T254	1		T438	13
values[22]	9161	1			T74	40		T254	1		T438	13
values[23]	8756	1			T74	18		T254	1		T438	13
values[24]	8519	1			T74	48		T254	1		T438	14
values[25]	8138	1			T74	33		T254	1		T438	13
values[26]	7748	1			T74	45		T254	1		T438	13
values[27]	7309	1			T74	28		T254	1		T438	13
values[28]	6943	1			T74	36		T254	1		T438	13
values[29]	6438	1			T74	38		T254	1		T438	13
values[30]	5842	1			T74	29		T254	1		T438	13
values[31]	5557	1			T74	23		T254	1		T438	13
values[32]	5433	1			T74	36		T254	1		T438	13
values[33]	4967	1			T74	40		T254	1		T438	14
values[34]	4580	1			T74	45		T254	1		T438	13
values[35]	4234	1			T74	27		T254	1		T438	13
values[36]	4042	1			T74	30		T254	1		T438	14
values[37]	3816	1			T74	20		T254	1		T438	13
values[38]	3684	1			T74	21		T254	1		T438	14
values[39]	3519	1			T74	17		T254	1		T438	14
values[40]	3390	1			T74	4		T254	1		T438	13
values[41]	3312	1			T74	4		T254	1		T438	14
values[42]	3268	1			T74	7		T254	1		T438	13
values[43]	3083	1			T74	5		T254	1		T438	13
values[44]	3001	1			T74	6		T254	1		T438	13
values[45]	2996	1			T74	2		T254	1		T438	13
values[46]	2928	1			T74	7		T254	1		T438	13
values[47]	2894	1			T74	2		T254	1		T438	13
values[48]	2837	1			T74	4		T254	1		T438	13
values[49]	2792	1			T74	7		T254	1		T438	14
values[50]	2695	1			T74	8		T254	1		T438	14
values[51]	2640	1			T74	2		T254	1		T438	14
values[52]	2620	1			T74	1		T254	1		T438	13
values[53]	2703	1			T74	2		T254	1		T438	13
values[54]	2513	1			T74	4		T254	1		T438	14
values[55]	2514	1			T74	1		T254	1		T438	13
values[56]	2487	1			T74	1		T254	1		T438	14
values[57]	2386	1			T74	1		T254	1		T438	13
values[58]	2304	1			T74	1		T254	1		T438	13
values[59]	2347	1			T74	6		T254	1		T438	13
values[60]	2408	1			T254	1		T438	13		T908	5
values[61]	2562	1			T254	1		T438	13		T908	5
values[62]	3984	1			T254	1		T438	13		T908	5
values[63]	10892	1			T254	1		T438	14		T908	5
values[64]	219854	1			T254	196		T438	2229		T908	955

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4654886	1			T74	3855		T75	410		T76	356
values[2]	790180	1			T74	920		T75	131		T76	77
values[3]	82624	1			T74	29		T75	38		T76	10
values[4]	15312	1			T74	1		T75	6		T76	2
values[5]	5988	1			T551	1		T254	1		T438	20
values[6]	3678	1			T438	5		T539	9		T908	6
values[7]	2839	1			T539	3		T940	15		T554	4
values[8]	2346	1			T940	22		T554	5		T751	1
values[9]	1986	1			T940	17		T554	2		T751	3
values[10]	1801	1			T940	15		T554	3		T751	1
values[11]	1595	1			T940	5		T554	3		T751	3
values[12]	1513	1			T940	5		T554	8		T751	2
values[13]	1447	1			T940	5		T554	6		T751	1
values[14]	1434	1			T940	5		T554	2		T751	1
values[15]	1386	1			T940	19		T554	3		T751	2
values[16]	1184	1			T940	20		T554	3		T751	1
values[17]	1130	1			T940	13		T554	5		T751	3
values[18]	1018	1			T940	4		T554	5		T751	1
values[19]	1006	1			T940	2		T554	5		T751	2
values[20]	1031	1			T940	3		T554	2		T751	1
values[21]	1026	1			T940	4		T554	10		T751	1
values[22]	898	1			T940	4		T554	4		T751	1
values[23]	834	1			T940	6		T554	5		T751	1
values[24]	778	1			T940	1		T554	5		T751	3
values[25]	770	1			T554	3		T751	1		T586	7
values[26]	776	1			T554	3		T751	3		T586	17
values[27]	787	1			T554	5		T751	1		T586	22
values[28]	739	1			T554	2		T751	4		T586	14
values[29]	692	1			T554	2		T751	4		T586	2
values[30]	629	1			T554	2		T751	2		T470	5
values[31]	637	1			T554	4		T751	2		T470	2
values[32]	596	1			T554	7		T751	1		T470	1
values[33]	557	1			T554	5		T751	1		T470	2
values[34]	535	1			T554	3		T751	2		T470	1
values[35]	522	1			T554	2		T751	1		T470	5
values[36]	530	1			T554	3		T751	1		T470	1
values[37]	500	1			T554	4		T751	3		T470	2
values[38]	524	1			T554	3		T751	1		T470	1
values[39]	478	1			T554	2		T751	1		T470	2
values[40]	522	1			T554	4		T751	2		T470	2
values[41]	475	1			T554	4		T751	4		T470	1
values[42]	511	1			T554	5		T751	6		T470	1
values[43]	466	1			T554	8		T751	2		T470	1
values[44]	434	1			T554	4		T751	3		T470	1
values[45]	429	1			T554	2		T751	2		T470	2
values[46]	426	1			T554	2		T751	1		T470	1
values[47]	414	1			T554	2		T751	1		T470	2
values[48]	447	1			T554	6		T751	5		T470	3
values[49]	450	1			T554	7		T751	1		T470	1
values[50]	424	1			T554	5		T751	2		T470	1
values[51]	433	1			T554	5		T751	2		T470	1
values[52]	409	1			T554	4		T751	1		T470	5
values[53]	417	1			T554	3		T751	2		T470	2
values[54]	415	1			T554	5		T751	1		T470	2
values[55]	442	1			T554	5		T751	4		T470	3
values[56]	405	1			T554	5		T751	1		T470	1
values[57]	403	1			T554	3		T751	4		T470	1
values[58]	392	1			T554	5		T751	1		T470	1
values[59]	389	1			T554	5		T751	1		T470	1
values[60]	376	1			T554	3		T751	1		T470	1
values[61]	426	1			T554	2		T751	2		T470	5
values[62]	633	1			T554	3		T751	1		T470	3
values[63]	2804	1			T554	20		T751	14		T470	42
values[64]	27276	1			T554	281		T751	97		T470	113

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	553335	1			T74	19		T75	4		T76	4
values[2]	2620276	1			T74	2556		T75	389		T76	135
values[3]	1166256	1			T74	221		T75	153		T76	298
values[4]	142073	1			T74	63		T75	8		T76	20
values[5]	73295	1			T74	55		T75	1		T254	1
values[6]	48012	1			T74	61		T254	1		T438	13
values[7]	35013	1			T74	67		T254	1		T438	13
values[8]	27742	1			T74	54		T254	1		T438	13
values[9]	23110	1			T74	62		T254	1		T438	13
values[10]	20130	1			T74	62		T254	1		T438	13
values[11]	18388	1			T74	45		T254	1		T438	13
values[12]	17005	1			T74	58		T254	1		T438	13
values[13]	16057	1			T74	75		T254	1		T438	13
values[14]	15117	1			T74	54		T254	1		T438	13
values[15]	14506	1			T74	51		T254	1		T438	13
values[16]	13999	1			T74	54		T254	1		T438	13
values[17]	13199	1			T74	76		T254	1		T438	13
values[18]	12210	1			T74	65		T254	1		T438	13
values[19]	11963	1			T74	58		T254	1		T438	13
values[20]	11401	1			T74	46		T254	1		T438	13
values[21]	10924	1			T74	58		T254	1		T438	13
values[22]	10494	1			T74	76		T254	1		T438	14
values[23]	9779	1			T74	39		T254	1		T438	13
values[24]	9280	1			T74	49		T254	1		T438	13
values[25]	9174	1			T74	74		T254	1		T438	13
values[26]	9062	1			T74	61		T254	1		T438	14
values[27]	8446	1			T74	45		T254	1		T438	13
values[28]	7945	1			T74	52		T254	1		T438	13
values[29]	7415	1			T74	71		T254	1		T438	13
values[30]	7045	1			T74	75		T254	1		T438	13
values[31]	6419	1			T74	51		T254	1		T438	13
values[32]	5917	1			T74	31		T254	1		T438	13
values[33]	5421	1			T74	15		T254	1		T438	13
values[34]	5099	1			T74	11		T254	1		T438	13
values[35]	4658	1			T74	18		T254	1		T438	13
values[36]	4423	1			T74	22		T254	1		T438	13
values[37]	4200	1			T74	22		T254	1		T438	13
values[38]	4147	1			T74	31		T254	1		T438	13
values[39]	3934	1			T74	17		T254	1		T438	13
values[40]	3742	1			T74	16		T254	1		T438	13
values[41]	3673	1			T74	12		T254	1		T438	14
values[42]	3556	1			T74	14		T254	1		T438	13
values[43]	3369	1			T74	18		T254	1		T438	13
values[44]	3239	1			T74	4		T254	1		T438	13
values[45]	3282	1			T74	4		T254	2		T438	13
values[46]	3226	1			T74	6		T254	1		T438	13
values[47]	3162	1			T74	6		T254	1		T438	13
values[48]	3094	1			T74	7		T254	1		T438	13
values[49]	2988	1			T74	4		T254	1		T438	13
values[50]	3027	1			T74	3		T254	1		T438	13
values[51]	2921	1			T74	3		T254	1		T438	13
values[52]	2976	1			T74	10		T254	1		T438	13
values[53]	2954	1			T74	2		T254	1		T438	13
values[54]	2884	1			T74	1		T254	1		T438	13
values[55]	2875	1			T74	1		T254	1		T438	13
values[56]	2839	1			T74	8		T254	1		T438	13
values[57]	2702	1			T74	5		T254	1		T438	13
values[58]	2725	1			T254	1		T438	13		T908	5
values[59]	2569	1			T254	1		T438	13		T908	5
values[60]	2536	1			T254	1		T438	13		T908	5
values[61]	2756	1			T254	1		T438	13		T908	5
values[62]	3631	1			T254	1		T438	14		T908	5
values[63]	9049	1			T254	1		T438	13		T908	6
values[64]	209969	1			T254	218		T438	2537		T908	1031