Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1980836	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

37858854

1

T1

7547

T2

7024

T3

5742

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	27918355	1			T1	3442		T2	2945		T3	2395
values[0x0]	10419001	1			T1	4105		T2	4079		T3	3347
values[0x1]	1502334	1			T1	371		T2	189		T3	361

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	639591	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39200099

1

T1

7918

T2

7213

T3

6103

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18738583	1			T1	3959		T2	3607		T3	3052
valid_sources[0x01]	18737264	1			T1	3959		T2	3606		T3	3051
valid_sources[0x02]	37979	1			T52	4		T197	2		T395	110
valid_sources[0x03]	37521	1			T68	2		T197	3		T395	145
valid_sources[0x04]	38796	1			T395	119		T143	107		T144	133
valid_sources[0x05]	37542	1			T395	93		T143	78		T144	116
valid_sources[0x06]	37944	1			T52	5		T197	1		T395	130
valid_sources[0x07]	37893	1			T68	1		T198	5		T395	130
valid_sources[0x08]	38367	1			T395	115		T143	87		T144	159
valid_sources[0x09]	37547	1			T68	6		T52	1		T197	1
valid_sources[0x0a]	37642	1			T68	2		T395	102		T143	72
valid_sources[0x0b]	45418	1			T52	3		T197	2		T395	85
valid_sources[0x0c]	38572	1			T395	142		T143	85		T144	199
valid_sources[0x0d]	37755	1			T197	2		T395	145		T143	30
valid_sources[0x0e]	37217	1			T77	39		T395	138		T143	61
valid_sources[0x0f]	38644	1			T197	1		T395	123		T143	113
valid_sources[0x10]	38486	1			T197	1		T395	146		T143	96
valid_sources[0x11]	37463	1			T395	144		T143	91		T144	191
valid_sources[0x12]	37578	1			T68	1		T197	4		T395	131
valid_sources[0x13]	38099	1			T68	1		T197	2		T395	106
valid_sources[0x14]	38089	1			T52	1		T395	148		T143	130
valid_sources[0x15]	37976	1			T52	3		T395	148		T143	46
valid_sources[0x16]	37786	1			T198	4		T395	129		T143	63
valid_sources[0x17]	37226	1			T395	118		T143	86		T144	155
valid_sources[0x18]	37678	1			T68	1		T395	140		T143	87
valid_sources[0x19]	37246	1			T395	149		T143	82		T144	186
valid_sources[0x1a]	37843	1			T68	2		T197	1		T395	115
valid_sources[0x1b]	38613	1			T395	99		T143	96		T144	93
valid_sources[0x1c]	37318	1			T68	1		T395	138		T143	90
valid_sources[0x1d]	37425	1			T395	121		T143	72		T144	165
valid_sources[0x1e]	43779	1			T198	7		T52	1		T395	151
valid_sources[0x1f]	38012	1			T68	1		T197	2		T395	123
valid_sources[0x20]	37749	1			T395	124		T143	124		T144	143

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27223809

1

T1

3442

T2

2945

T3

2395

values[0x0]

all_enables

biggest_size

10364660

1

T1

4105

T2

4079

T3

3347

values[0x1]

all_enables

biggest_size

270385

1

T68

14

T77

17

T78

21

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2788972	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

442591

1

T74

622

T75

61

T76

58

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1094872	1			T74	1507		T75	151		T76	126
values[0x0]	1042642	1			T74	1538		T75	136		T76	123
values[0x1]	1094049	1			T74	1538		T75	143		T76	105

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2159585	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1071978

1

T74

1473

T75

145

T76

119

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50458	1			T74	76		T79	1		T80	3
valid_sources[0x01]	51542	1			T74	74		T75	6		T79	1
valid_sources[0x02]	51138	1			T74	70		T75	6		T80	2
valid_sources[0x03]	50351	1			T74	38		T75	3		T76	8
valid_sources[0x04]	50483	1			T74	73		T75	8		T79	1
valid_sources[0x05]	51173	1			T74	70		T75	7		T76	3
valid_sources[0x06]	51159	1			T74	65		T75	2		T76	9
valid_sources[0x07]	50306	1			T74	97		T75	9		T76	6
valid_sources[0x08]	50266	1			T74	68		T75	15		T76	8
valid_sources[0x09]	50320	1			T74	89		T75	3		T76	9
valid_sources[0x0a]	50659	1			T74	71		T75	24		T551	1
valid_sources[0x0b]	50172	1			T74	83		T79	3		T80	1
valid_sources[0x0c]	51308	1			T74	84		T75	18		T76	2
valid_sources[0x0d]	49164	1			T74	106		T75	2		T76	6
valid_sources[0x0e]	50772	1			T74	66		T75	6		T76	2
valid_sources[0x0f]	51063	1			T74	94		T75	3		T76	17
valid_sources[0x10]	51496	1			T74	35		T76	16		T253	3
valid_sources[0x11]	51008	1			T74	61		T75	4		T79	1
valid_sources[0x12]	50048	1			T74	64		T75	4		T76	4
valid_sources[0x13]	51348	1			T74	53		T75	5		T79	7
valid_sources[0x14]	50570	1			T74	93		T75	7		T76	20
valid_sources[0x15]	50147	1			T74	98		T75	16		T76	10
valid_sources[0x16]	50358	1			T74	95		T75	4		T76	3
valid_sources[0x17]	51836	1			T74	92		T76	5		T79	1
valid_sources[0x18]	49873	1			T74	51		T75	3		T76	6
valid_sources[0x19]	50479	1			T74	48		T75	5		T79	1
valid_sources[0x1a]	50308	1			T74	99		T75	17		T76	3
valid_sources[0x1b]	50974	1			T74	51		T75	8		T76	3
valid_sources[0x1c]	50823	1			T74	63		T75	18		T76	2
valid_sources[0x1d]	50220	1			T74	122		T75	7		T79	3
valid_sources[0x1e]	50248	1			T74	51		T75	10		T76	4
valid_sources[0x1f]	49340	1			T74	91		T75	4		T76	2
valid_sources[0x20]	49970	1			T74	42		T75	5		T76	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46235

1

T74

54

T75

11

T76

4

values[0x0]

all_enables

biggest_size

349404

1

T74

516

T75

46

T76

48

values[0x1]

all_enables

biggest_size

46952

1

T74

52

T75

4

T76

6

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2971333	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

482924

1

T74

683

T75

91

T76

83

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1182014	1			T74	1665		T75	184		T76	145
values[0x0]	1087836	1			T74	1520		T75	206		T76	139
values[0x1]	1184407	1			T74	1620		T75	195		T76	161

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2278069	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1176188

1

T74

1638

T75

200

T76

169

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53746	1			T74	83		T75	5		T76	8
valid_sources[0x01]	54581	1			T74	85		T75	2		T76	7
valid_sources[0x02]	52960	1			T74	80		T75	13		T76	9
valid_sources[0x03]	55199	1			T74	84		T75	15		T76	6
valid_sources[0x04]	55337	1			T74	78		T75	11		T76	9
valid_sources[0x05]	54566	1			T74	83		T75	3		T76	7
valid_sources[0x06]	53946	1			T74	57		T75	1		T76	7
valid_sources[0x07]	54621	1			T74	76		T75	2		T76	5
valid_sources[0x08]	53730	1			T74	79		T76	12		T80	3
valid_sources[0x09]	53630	1			T74	77		T75	15		T76	3
valid_sources[0x0a]	54548	1			T74	74		T75	17		T76	9
valid_sources[0x0b]	53349	1			T74	66		T75	9		T76	8
valid_sources[0x0c]	53916	1			T74	75		T75	6		T76	7
valid_sources[0x0d]	53632	1			T74	91		T75	6		T76	7
valid_sources[0x0e]	53740	1			T74	66		T75	1		T76	10
valid_sources[0x0f]	53448	1			T74	61		T75	6		T76	7
valid_sources[0x10]	54226	1			T74	90		T75	16		T79	1
valid_sources[0x11]	54806	1			T74	76		T75	8		T76	11
valid_sources[0x12]	54334	1			T74	89		T75	7		T76	1
valid_sources[0x13]	54147	1			T74	80		T75	17		T76	12
valid_sources[0x14]	54219	1			T74	69		T75	4		T76	16
valid_sources[0x15]	55090	1			T74	55		T75	4		T76	11
valid_sources[0x16]	53575	1			T74	83		T76	5		T79	1
valid_sources[0x17]	53857	1			T74	72		T75	11		T76	2
valid_sources[0x18]	54552	1			T74	71		T75	10		T76	3
valid_sources[0x19]	53457	1			T74	70		T75	17		T76	7
valid_sources[0x1a]	54242	1			T74	72		T75	14		T76	6
valid_sources[0x1b]	54032	1			T74	76		T75	6		T76	4
valid_sources[0x1c]	54168	1			T74	71		T75	11		T76	9
valid_sources[0x1d]	54224	1			T74	64		T75	2		T76	9
valid_sources[0x1e]	53253	1			T74	88		T75	9		T76	10
valid_sources[0x1f]	53360	1			T74	101		T75	13		T76	6
valid_sources[0x20]	53811	1			T74	88		T75	5		T76	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

50814

1

T74

74

T75

7

T76

11

values[0x0]

all_enables

biggest_size

381443

1

T74

527

T75

72

T76

66

values[0x1]

all_enables

biggest_size

50667

1

T74

82

T75

12

T76

6

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2817809	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

445514

1

T74

661

T75

76

T76

59

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1105686	1			T74	1618		T75	178		T76	158
values[0x0]	1053059	1			T74	1561		T75	176		T76	140
values[0x1]	1104578	1			T74	1565		T75	201		T76	159

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2182333	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1080990

1

T74

1546

T75

168

T76

159

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51304	1			T74	134		T75	10		T76	2
valid_sources[0x01]	51879	1			T74	23		T75	9		T76	4
valid_sources[0x02]	50730	1			T74	75		T75	7		T76	7
valid_sources[0x03]	51130	1			T74	37		T75	9		T76	12
valid_sources[0x04]	51722	1			T74	36		T75	8		T76	7
valid_sources[0x05]	51322	1			T74	30		T75	12		T76	2
valid_sources[0x06]	51541	1			T74	27		T75	12		T76	1
valid_sources[0x07]	50856	1			T74	43		T75	6		T76	10
valid_sources[0x08]	51277	1			T74	106		T75	13		T76	5
valid_sources[0x09]	50469	1			T74	32		T75	14		T76	6
valid_sources[0x0a]	51314	1			T74	140		T75	12		T76	6
valid_sources[0x0b]	51064	1			T74	129		T75	8		T76	11
valid_sources[0x0c]	50292	1			T74	114		T75	9		T76	5
valid_sources[0x0d]	49950	1			T74	40		T75	15		T76	6
valid_sources[0x0e]	50696	1			T74	18		T75	5		T76	13
valid_sources[0x0f]	51661	1			T74	34		T75	2		T76	6
valid_sources[0x10]	50302	1			T74	16		T75	4		T76	5
valid_sources[0x11]	52101	1			T74	25		T75	5		T76	10
valid_sources[0x12]	50760	1			T74	135		T75	13		T76	4
valid_sources[0x13]	51098	1			T74	163		T75	11		T76	12
valid_sources[0x14]	50260	1			T74	42		T75	4		T76	10
valid_sources[0x15]	51983	1			T74	33		T75	9		T76	3
valid_sources[0x16]	50633	1			T74	199		T75	12		T76	8
valid_sources[0x17]	51009	1			T74	14		T75	5		T76	11
valid_sources[0x18]	51391	1			T74	22		T75	9		T76	8
valid_sources[0x19]	51150	1			T74	43		T75	10		T76	6
valid_sources[0x1a]	51411	1			T74	116		T75	10		T76	9
valid_sources[0x1b]	50777	1			T74	31		T75	5		T76	3
valid_sources[0x1c]	51090	1			T74	39		T75	13		T76	12
valid_sources[0x1d]	49816	1			T74	30		T75	9		T76	9
valid_sources[0x1e]	50617	1			T74	108		T75	9		T76	9
valid_sources[0x1f]	49902	1			T74	27		T75	8		T76	6
valid_sources[0x20]	51046	1			T74	45		T75	9		T76	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46703

1

T74

74

T75

10

T76

11

values[0x0]

all_enables

biggest_size

351886

1

T74

516

T75

62

T76

43

values[0x1]

all_enables

biggest_size

46925

1

T74

71

T75

4

T76

5