Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522617944	60566530	0	0
DepthKnown_A	522617944	522509949	0	0
RvalidKnown_A	522617944	522509949	0	0
WreadyKnown_A	522617944	522509949	0	0
gen_passthru_fifo.paramCheckPass	1022	1022	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	60566530	0	0
T1	144170	19527	0	0
T2	249538	207340	0	0
T3	102822	13156	0	0
T33	376906	54582	0	0
T34	210117	11758	0	0
T35	661977	93429	0	0
T60	219243	20287	0	0
T86	571518	51715	0	0
T87	302857	36139	0	0
T88	153079	19216	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	522509949	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	522509949	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	522509949	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522617944	46754476	0	0
DepthKnown_A	522617944	522509949	0	0
RvalidKnown_A	522617944	522509949	0	0
WreadyKnown_A	522617944	522509949	0	0
gen_passthru_fifo.paramCheckPass	1022	1022	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	46754476	0	0
T1	144170	14341	0	0
T2	249538	102861	0	0
T3	102822	10042	0	0
T33	376906	46242	0	0
T34	210117	7773	0	0
T35	661977	86519	0	0
T60	219243	16525	0	0
T86	571518	45771	0	0
T87	302857	25602	0	0
T88	153079	16683	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	522509949	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	522509949	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	522509949	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522617944	44423606	0	0
DepthKnown_A	522617944	522509949	0	0
RvalidKnown_A	522617944	522509949	0	0
WreadyKnown_A	522617944	522509949	0	0
gen_passthru_fifo.paramCheckPass	1022	1022	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	44423606	0	0
T1	144170	8195	0	0
T2	249538	8662	0	0
T3	102822	6254	0	0
T33	376906	40611	0	0
T34	210117	6090	0	0
T35	661977	82004	0	0
T60	219243	12555	0	0
T86	571518	60122	0	0
T87	302857	15611	0	0
T88	153079	6192	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	522509949	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	522509949	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	522509949	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522617944	37505106	0	0
DepthKnown_A	522617944	522509949	0	0
RvalidKnown_A	522617944	522509949	0	0
WreadyKnown_A	522617944	522509949	0	0
gen_passthru_fifo.paramCheckPass	1022	1022	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	37505106	0	0
T1	144170	7918	0	0
T2	249538	7213	0	0
T3	102822	6103	0	0
T33	376906	40132	0	0
T34	210117	5838	0	0
T35	661977	81590	0	0
T60	219243	12310	0	0
T86	571518	59795	0	0
T87	302857	15086	0	0
T88	153079	6015	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	522509949	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	522509949	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	522509949	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	604130077	93519	0	0
DepthKnown_A	604130077	604006200	0	0
RvalidKnown_A	604130077	604006200	0	0
WreadyKnown_A	604130077	604006200	0	0
gen_passthru_fifo.paramCheckPass	2932	2932	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604130077	93519	0	0
T1	144170	26	0	0
T2	249538	27	0	0
T3	102822	20	0	0
T33	376906	75	0	0
T34	210117	29	0	0
T35	661977	39	0	0
T60	219243	30	0	0
T86	571518	249	0	0
T87	302857	94	0	0
T88	153079	48	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604130077	604006200	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604130077	604006200	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604130077	604006200	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2932	2932	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	604130077	96426	0	0
DepthKnown_A	604130077	604006200	0	0
RvalidKnown_A	604130077	604006200	0	0
WreadyKnown_A	604130077	604006200	0	0
gen_passthru_fifo.paramCheckPass	2932	2932	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604130077	96426	0	0
T1	144170	26	0	0
T2	249538	27	0	0
T3	102822	20	0	0
T33	376906	75	0	0
T34	210117	29	0	0
T35	661977	39	0	0
T60	219243	30	0	0
T86	571518	249	0	0
T87	302857	94	0	0
T88	153079	48	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604130077	604006200	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604130077	604006200	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604130077	604006200	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2932	2932	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	604130077	52182	0	0
DepthKnown_A	604130077	604006200	0	0
RvalidKnown_A	604130077	604006200	0	0
WreadyKnown_A	604130077	604006200	0	0
gen_passthru_fifo.paramCheckPass	2932	2932	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604130077	52182	0	0
T1	144170	23	0	0
T2	249538	26	0	0
T3	102822	19	0	0
T33	376906	73	0	0
T34	210117	25	0	0
T35	661977	37	0	0
T60	219243	28	0	0
T86	571518	246	0	0
T87	302857	82	0	0
T88	153079	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604130077	604006200	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604130077	604006200	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604130077	604006200	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2932	2932	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	604130077	52181	0	0
DepthKnown_A	604130077	604006200	0	0
RvalidKnown_A	604130077	604006200	0	0
WreadyKnown_A	604130077	604006200	0	0
gen_passthru_fifo.paramCheckPass	2932	2932	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604130077	52181	0	0
T1	144170	23	0	0
T2	249538	26	0	0
T3	102822	19	0	0
T33	376906	73	0	0
T34	210117	25	0	0
T35	661977	37	0	0
T60	219243	28	0	0
T86	571518	246	0	0
T87	302857	82	0	0
T88	153079	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604130077	604006200	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604130077	604006200	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604130077	604006200	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2932	2932	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	604130077	41337	0	0
DepthKnown_A	604130077	604006200	0	0
RvalidKnown_A	604130077	604006200	0	0
WreadyKnown_A	604130077	604006200	0	0
gen_passthru_fifo.paramCheckPass	2932	2932	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604130077	41337	0	0
T1	144170	3	0	0
T2	249538	1	0	0
T3	102822	1	0	0
T33	376906	2	0	0
T34	210117	4	0	0
T35	661977	2	0	0
T60	219243	2	0	0
T86	571518	3	0	0
T87	302857	12	0	0
T88	153079	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604130077	604006200	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604130077	604006200	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604130077	604006200	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2932	2932	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	604130077	44245	0	0
DepthKnown_A	604130077	604006200	0	0
RvalidKnown_A	604130077	604006200	0	0
WreadyKnown_A	604130077	604006200	0	0
gen_passthru_fifo.paramCheckPass	2932	2932	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604130077	44245	0	0
T1	144170	3	0	0
T2	249538	1	0	0
T3	102822	1	0	0
T33	376906	2	0	0
T34	210117	4	0	0
T35	661977	2	0	0
T60	219243	2	0	0
T86	571518	3	0	0
T87	302857	12	0	0
T88	153079	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604130077	604006200	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604130077	604006200	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604130077	604006200	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2932	2932	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0