Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T34,T5,T294	Yes	T34,T5,T294	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T34,T5,T294	Yes	T34,T5,T294	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T67,*T68,*T69	Yes	T67,T68,T69	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T68,T77,T78	Yes	T68,T77,T78	INPUT
tl_i.a_valid	Yes	Yes	T34,T5,T294	Yes	T34,T5,T294	INPUT
tl_o.a_ready	Yes	Yes	T5,T294,T213	Yes	T5,T294,T213	OUTPUT
tl_o.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T213,T48	Yes	T5,T213,T48	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T294,T213	Yes	T5,T294,T213	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T294,T213	Yes	T5,T294,T213	OUTPUT
tl_o.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T260,*T262,*T74	Yes	T260,T262,T74	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T294,*T213	Yes	T5,T294,T213	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T294,T213	Yes	T5,T294,T213	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T81,T543,T772	Yes	T81,T543,T772	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T81,T84,T85	Yes	T81,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T81,T84,T85	Yes	T81,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T81,T543,T772	Yes	T81,T543,T772	OUTPUT
cio_rx_i	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T5,T213,T48	Yes	T5,T213,T48	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T5,T213,T214	Yes	T5,T213,T214	OUTPUT
intr_tx_empty_o	Yes	Yes	T5,T213,T214	Yes	T5,T213,T214	OUTPUT
intr_rx_watermark_o	Yes	Yes	T5,T213,T214	Yes	T5,T213,T214	OUTPUT
intr_tx_done_o	Yes	Yes	T5,T294,T213	Yes	T5,T294,T213	OUTPUT
intr_rx_overflow_o	Yes	Yes	T5,T294,T213	Yes	T5,T294,T213	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T327,T331,T325	Yes	T327,T331,T325	OUTPUT
intr_rx_break_err_o	Yes	Yes	T327,T331,T325	Yes	T327,T331,T325	OUTPUT
intr_rx_timeout_o	Yes	Yes	T327,T331,T325	Yes	T327,T331,T325	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T327,T331,T325	Yes	T327,T331,T325	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T34,T294,T48	Yes	T34,T294,T48	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T34,T294,T48	Yes	T34,T294,T48	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T67,*T68,*T69	Yes	T67,T68,T69	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T68,T77,T78	Yes	T68,T77,T78	INPUT
tl_i.a_valid	Yes	Yes	T34,T294,T48	Yes	T34,T294,T48	INPUT
tl_o.a_ready	Yes	Yes	T294,T48,T49	Yes	T294,T48,T49	OUTPUT
tl_o.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T48,T49,T45	Yes	T48,T49,T45	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T294,T48,T49	Yes	T294,T48,T49	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T294,T48,T49	Yes	T294,T48,T49	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T260,*T262,*T75	Yes	T260,T262,T75	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T294,*T48,*T49	Yes	T294,T48,T49	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T294,T48,T49	Yes	T294,T48,T49	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T81,T94,T770	Yes	T81,T94,T770	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T81,T84,T85	Yes	T81,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T81,T84,T85	Yes	T81,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T81,T94,T770	Yes	T81,T94,T770	OUTPUT
cio_rx_i	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T48,T49,T45	Yes	T48,T49,T45	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T315,T316,T301	Yes	T315,T316,T301	OUTPUT
intr_tx_empty_o	Yes	Yes	T315,T301,T327	Yes	T315,T301,T327	OUTPUT
intr_rx_watermark_o	Yes	Yes	T315,T301,T327	Yes	T315,T301,T327	OUTPUT
intr_tx_done_o	Yes	Yes	T294,T342,T315	Yes	T294,T342,T315	OUTPUT
intr_rx_overflow_o	Yes	Yes	T294,T342,T315	Yes	T294,T342,T315	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T327,T331,T325	Yes	T327,T331,T325	OUTPUT
intr_rx_break_err_o	Yes	Yes	T327,T331,T325	Yes	T327,T331,T325	OUTPUT
intr_rx_timeout_o	Yes	Yes	T327,T331,T325	Yes	T327,T331,T325	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T327,T331,T325	Yes	T327,T331,T325	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T213,T214,T338	Yes	T213,T214,T338	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T213,T214,T338	Yes	T213,T214,T338	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T67,*T68,*T69	Yes	T67,T68,T69	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T68,T77,T78	Yes	T68,T77,T78	INPUT
tl_i.a_valid	Yes	Yes	T213,T214,T338	Yes	T213,T214,T338	INPUT
tl_o.a_ready	Yes	Yes	T213,T214,T338	Yes	T213,T214,T338	OUTPUT
tl_o.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T213,T214,T338	Yes	T213,T214,T338	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T213,T214,T338	Yes	T213,T214,T338	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T213,T214,T338	Yes	T213,T214,T338	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T75,*T76,*T79	Yes	T75,T76,T79	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T213,*T214,*T338	Yes	T213,T214,T338	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T213,T214,T338	Yes	T213,T214,T338	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T81,T771,T84	Yes	T81,T771,T84	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T81,T84,T85	Yes	T81,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T81,T84,T85	Yes	T81,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T81,T771,T84	Yes	T81,T771,T84	OUTPUT
cio_rx_i	Yes	Yes	T213,T214,T338	Yes	T9,T213,T214	INPUT
cio_tx_o	Yes	Yes	T213,T214,T338	Yes	T213,T214,T338	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T213,T214,T338	Yes	T213,T214,T338	OUTPUT
intr_tx_empty_o	Yes	Yes	T213,T214,T338	Yes	T213,T214,T338	OUTPUT
intr_rx_watermark_o	Yes	Yes	T213,T214,T338	Yes	T213,T214,T338	OUTPUT
intr_tx_done_o	Yes	Yes	T213,T214,T338	Yes	T213,T214,T338	OUTPUT
intr_rx_overflow_o	Yes	Yes	T213,T214,T338	Yes	T213,T214,T338	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T327,T331,T325	Yes	T327,T331,T325	OUTPUT
intr_rx_break_err_o	Yes	Yes	T327,T331,T325	Yes	T327,T331,T325	OUTPUT
intr_rx_timeout_o	Yes	Yes	T327,T331,T325	Yes	T327,T331,T325	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T327,T331,T325	Yes	T327,T331,T325	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T147,T339	Yes	T5,T147,T339	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T147,T339	Yes	T5,T147,T339	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T67,*T68,*T69	Yes	T67,T68,T69	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T68,T77,T78	Yes	T68,T77,T78	INPUT
tl_i.a_valid	Yes	Yes	T5,T147,T339	Yes	T5,T147,T339	INPUT
tl_o.a_ready	Yes	Yes	T5,T147,T339	Yes	T5,T147,T339	OUTPUT
tl_o.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T147,T339	Yes	T5,T147,T339	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T147,T339	Yes	T5,T147,T339	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T147,T339	Yes	T5,T147,T339	OUTPUT
tl_o.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T147,*T339	Yes	T5,T147,T339	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T147,T339	Yes	T5,T147,T339	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T81,T84,T85	Yes	T81,T84,T85	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T81,T84,T85	Yes	T81,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T81,T84,T85	Yes	T81,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T81,T84,T85	Yes	T81,T84,T85	OUTPUT
cio_rx_i	Yes	Yes	T5,T147,T339	Yes	T5,T147,T339	INPUT
cio_tx_o	Yes	Yes	T5,T147,T339	Yes	T5,T147,T339	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T5,T147,T339	Yes	T5,T147,T339	OUTPUT
intr_tx_empty_o	Yes	Yes	T5,T147,T339	Yes	T5,T147,T339	OUTPUT
intr_rx_watermark_o	Yes	Yes	T5,T147,T339	Yes	T5,T147,T339	OUTPUT
intr_tx_done_o	Yes	Yes	T5,T147,T339	Yes	T5,T147,T339	OUTPUT
intr_rx_overflow_o	Yes	Yes	T5,T147,T339	Yes	T5,T147,T339	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T327,T331,T325	Yes	T327,T331,T325	OUTPUT
intr_rx_break_err_o	Yes	Yes	T327,T331,T325	Yes	T327,T331,T325	OUTPUT
intr_rx_timeout_o	Yes	Yes	T327,T331,T325	Yes	T327,T331,T325	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T327,T331,T325	Yes	T327,T331,T325	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T15,T326,T327	Yes	T15,T326,T327	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T15,T326,T327	Yes	T15,T326,T327	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T67,*T68,*T69	Yes	T67,T68,T69	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T68,T77,T78	Yes	T68,T77,T78	INPUT
tl_i.a_valid	Yes	Yes	T15,T326,T327	Yes	T15,T326,T327	INPUT
tl_o.a_ready	Yes	Yes	T15,T326,T327	Yes	T15,T326,T327	OUTPUT
tl_o.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T15,T326,T327	Yes	T15,T326,T327	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T15,T326,T327	Yes	T15,T326,T327	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T15,T326,T327	Yes	T15,T326,T327	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T75,*T76,*T79	Yes	T75,T76,T79	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T15,*T326,*T327	Yes	T15,T326,T327	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T15,T326,T327	Yes	T15,T326,T327	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T81,T543,T772	Yes	T81,T543,T772	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T81,T84,T85	Yes	T81,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T81,T84,T85	Yes	T81,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T81,T543,T772	Yes	T81,T543,T772	OUTPUT
cio_rx_i	Yes	Yes	T15,T326,T369	Yes	T15,T326,T369	INPUT
cio_tx_o	Yes	Yes	T15,T326,T369	Yes	T15,T326,T369	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T15,T326,T327	Yes	T15,T326,T327	OUTPUT
intr_tx_empty_o	Yes	Yes	T15,T326,T327	Yes	T15,T326,T327	OUTPUT
intr_rx_watermark_o	Yes	Yes	T15,T326,T327	Yes	T15,T326,T327	OUTPUT
intr_tx_done_o	Yes	Yes	T15,T326,T327	Yes	T15,T326,T327	OUTPUT
intr_rx_overflow_o	Yes	Yes	T15,T326,T327	Yes	T15,T326,T327	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T327,T331,T325	Yes	T327,T331,T325	OUTPUT
intr_rx_break_err_o	Yes	Yes	T327,T331,T325	Yes	T327,T331,T325	OUTPUT
intr_rx_timeout_o	Yes	Yes	T327,T331,T325	Yes	T327,T331,T325	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T327,T331,T325	Yes	T327,T331,T325	OUTPUT

*Tests covering at least one bit in the range