Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T75,T76,T80	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T79,T253,T254	Yes	T79,T253,T254	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T218,T67,T219	Yes	T218,T67,T219	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T218,T67,T219	Yes	T218,T67,T219	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T68,T77,T78	Yes	T68,T77,T78	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T77,T198,T74	Yes	T77,T198,T74	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T77,T198,T74	Yes	T77,T198,T74	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T4,T218,T67	Yes	T4,T218,T67	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T67,T68,T69	Yes	T67,T68,T69	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T67,T68,T69	Yes	T67,T68,T69	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T67,T68,T69	Yes	T67,T68,T69	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T68,T69,T62	Yes	T68,T69,T62	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T67,T68,T69	Yes	T67,T68,T69	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T68,T62,T77	Yes	T68,T62,T77	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T67,*T68,*T69	Yes	T67,T68,T69	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T67,T68,T69	Yes	T67,T68,T69	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T75,T76,T80	Yes	T74,T75,T76	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T75,*T76,*T79	Yes	T75,T76,T79	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T67,T260,T261	Yes	T67,T260,T261	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T67,T260,T261	Yes	T67,T260,T261	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T67,T260,T261	Yes	T67,T260,T261	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T67,T260,T261	Yes	T67,T260,T261	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T67,T260,T261	Yes	T67,T260,T261	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T67,*T260,*T261	Yes	T67,T260,T261	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T67,T260,T261	Yes	T67,T260,T261	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T33,T34,T35	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T67,T260,T261	Yes	T67,T260,T261	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T67,T260,T261	Yes	T67,T260,T261	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T33,T34,T35	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T67,*T260,*T261	Yes	T67,T260,T261	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T33,T34,T35	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T67,T260,T261	Yes	T67,T260,T261	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T8,T65,T48	Yes	T8,T65,T48	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T48,T413,T49	Yes	T48,T413,T49	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T50,T51,T249	Yes	T50,T51,T249	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T218,T278,T414	Yes	T218,T278,T414	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T218,T278,T414	Yes	T218,T278,T414	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T50,T51,T249	Yes	T50,T51,T249	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T218,T278,T414	Yes	T218,T278,T414	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T218,T278,T414	Yes	T218,T278,T414	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T218,T278,T414	Yes	T218,T278,T414	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T278,T414,T415	Yes	T278,T414,T415	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T74,T75,T76	Yes	T50,T51,T249	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T278,T414,T415	Yes	T278,T414,T50	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T218,*T278,*T414	Yes	T218,T278,T414	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T218,T278,T414	Yes	T218,T278,T414	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T67,*T68,*T69	Yes	T67,T68,T69	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T68,T77,T78	Yes	T68,T77,T78	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T218,T419,T243	Yes	T218,T419,T243	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T68,*T69,*T260	Yes	T67,T68,T69	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T12,T13,T397	Yes	T12,T13,T397	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T12,T13,T397	Yes	T12,T13,T397	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T12,T13,T397	Yes	T12,T13,T397	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T12,T13,T397	Yes	T12,T13,T397	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T12,T13,T397	Yes	T12,T13,T397	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T12,T13,T397	Yes	T12,T13,T397	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T79	Yes	T75,T76,T79	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T12,T13,T194	Yes	T12,T13,T194	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T12,T13,T397	Yes	T12,T13,T397	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T12,T13,T397	Yes	T12,T13,T397	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T75,T76,T80	Yes	T75,T76,T80	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T12,T13,T397	Yes	T12,T13,T397	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T12,T13,T397	Yes	T12,T13,T397	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T12,T13,T397	Yes	T12,T13,T397	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T75,T76,T79	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T75,T79,T80	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T74,T75,T76	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T12,*T13,*T397	Yes	T12,T13,T397	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T12,T13,T397	Yes	T12,T13,T397	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T397,T316,T407	Yes	T397,T316,T407	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T397,T153,T408	Yes	T397,T153,T408	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T397,T316,T407	Yes	T397,T316,T407	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T397,T316,T407	Yes	T397,T316,T407	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T397,T153,T408	Yes	T397,T153,T408	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T397,T316,T407	Yes	T397,T316,T407	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T79	Yes	T75,T76,T79	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T397,T316,T407	Yes	T397,T316,T407	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T397,T316,T407	Yes	T397,T316,T407	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T75,T79,T80	Yes	T75,T79,T80	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T397,T153,T408	Yes	T397,T153,T408	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T397,T316,T407	Yes	T397,T316,T407	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T397,T153,T408	Yes	T397,T153,T408	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T75,*T76,*T79	Yes	T75,T76,T79	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T397,*T316,*T407	Yes	T397,T316,T407	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T397,T316,T407	Yes	T397,T316,T407	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T18,T397,T19	Yes	T18,T397,T19	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T18,T397,T19	Yes	T18,T397,T19	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T18,T397,T19	Yes	T18,T397,T19	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T18,T397,T19	Yes	T18,T397,T19	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T18,T397,T19	Yes	T18,T397,T19	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T18,T397,T19	Yes	T18,T397,T19	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T79	Yes	T75,T76,T79	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T18,T397,T19	Yes	T18,T397,T19	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T18,T397,T19	Yes	T18,T397,T19	INPUT
tl_usbdev_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T397,T316,T24	Yes	T397,T316,T24	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T397,T316,T24	Yes	T397,T316,T24	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T18,T397,T19	Yes	T18,T397,T19	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T75,*T76,*T79	Yes	T75,T76,T79	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T18,*T397,*T19	Yes	T18,T397,T19	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T18,T397,T19	Yes	T18,T397,T19	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T198,*T75,*T76	Yes	T198,T75,T76	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T33,T34,T35	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T33,T34,T35	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T198,*T75,*T76	Yes	T198,T75,T76	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T198,T75,T76	Yes	T198,T75,T76	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T198,T75,T76	Yes	T198,T75,T76	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T198,T75,T76	Yes	T198,T75,T76	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T198,T75,T76	Yes	T198,T75,T76	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T198,T75,T76	Yes	T198,T75,T76	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T198,T75,T76	Yes	T198,T75,T76	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T198,T75,T76	Yes	T198,T75,T76	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T198,T75,T76	Yes	T198,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T198,T75,T76	Yes	T198,T75,T76	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T198,T75,T76	Yes	T198,T75,T76	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T198,T75,T76	Yes	T198,T75,T76	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T198,T75,T76	Yes	T198,T75,T76	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T198,*T75,*T76	Yes	T198,T75,T79	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T198,T75,T76	Yes	T198,T75,T76	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T33,T34	Yes	T1,T33,T34	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T33,T34,T35	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T3,T33,T34	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T3,T86,T48	Yes	T3,T86,T48	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T86,T48	Yes	T3,T86,T48	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T3,T86,T247	Yes	T3,T86,T247	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T3,T86,T48	Yes	T3,T86,T48	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T3,T86,T247	Yes	T3,T86,T247	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T198,*T75,*T76	Yes	T198,T75,T76	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T3,T86,T272	Yes	T3,T86,T272	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T3,T86,T247	Yes	T3,T86,T247	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T3,T86,T247	Yes	T3,T86,T247	INPUT
tl_hmac_i.d_error	Yes	Yes	T75,T76,T80	Yes	T75,T76,T80	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T3,T86,T247	Yes	T3,T86,T247	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T86,T247	Yes	T3,T86,T247	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T3,T86,T48	Yes	T3,T86,T48	INPUT
tl_hmac_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T198,*T75,*T76	Yes	T198,T75,T76	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T3,*T86,*T48	Yes	T3,T86,T48	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T3,T86,T247	Yes	T3,T86,T247	INPUT
tl_kmac_o.d_ready	Yes	Yes	T2,T33,T34	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T33,T35,T6	Yes	T33,T35,T6	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T33,T35	Yes	T2,T33,T35	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T2,T33,T35	Yes	T2,T33,T35	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T33,T35,T6	Yes	T33,T35,T6	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T2,T33,T35	Yes	T2,T33,T35	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T198,*T52,*T75	Yes	T198,T52,T75	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T108,T223,T449	Yes	T108,T223,T449	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T2,T33,T35	Yes	T2,T33,T35	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T2,T33,T35	Yes	T2,T33,T35	INPUT
tl_kmac_i.d_error	Yes	Yes	T74,T75,T76	Yes	T75,T76,T79	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T2,T33,T35	Yes	T2,T33,T35	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T33,T35	Yes	T2,T33,T35	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T2,T33,T35	Yes	T6,T450,T108	INPUT
tl_kmac_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T75,T76,T79	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T198,*T52,*T74	Yes	T198,T52,T75	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T74,T75,T76	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T2,*T33,*T35	Yes	T6,T108,T220	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T2,T33,T35	Yes	T2,T33,T35	INPUT
tl_aes_o.d_ready	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T33,T797,T68	Yes	T33,T797,T68	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T33,T797,T68	Yes	T33,T797,T68	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T33,T247,T263	Yes	T33,T247,T263	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T33,T797,T68	Yes	T33,T797,T68	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T33,T247,T263	Yes	T33,T247,T263	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T68,*T198,*T52	Yes	T68,T198,T52	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T33,T247,T263	Yes	T33,T247,T263	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T33,T247,T263	Yes	T33,T247,T263	INPUT
tl_aes_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T33,T247,T263	Yes	T33,T247,T263	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T33,T263,T797	Yes	T33,T263,T797	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T33,T247,T263	Yes	T33,T247,T263	INPUT
tl_aes_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T68,*T198,*T52	Yes	T68,T198,T52	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T33,*T247,*T263	Yes	T33,T247,T263	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T33,T247,T263	Yes	T33,T247,T263	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T198,*T75,*T76	Yes	T198,T75,T76	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T33,T35,T6	Yes	T33,T35,T6	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T198,*T75,*T76	Yes	T198,T75,T76	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T33,*T35,*T6	Yes	T33,T35,T6	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T33,T35,T6	Yes	T33,T35,T6	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T68,*T198,*T52	Yes	T68,T198,T52	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T33,T35,T6	Yes	T33,T35,T6	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T68,*T198,*T52	Yes	T68,T198,T52	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T33,*T35,*T6	Yes	T33,T35,T6	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T33,T35,T6	Yes	T33,T35,T6	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T33,T35,T6	Yes	T33,T35,T6	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T198,*T75,*T76	Yes	T198,T75,T76	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T33,T35,T6	Yes	T33,T35,T6	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T198,*T75,*T76	Yes	T198,T75,T76	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T33,*T35,*T6	Yes	T33,T35,T6	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T33,T35,T6	Yes	T33,T35,T6	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T33,T35,T6	Yes	T33,T35,T6	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T33,T35,T6	Yes	T33,T35,T6	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T33,T35,T6	Yes	T33,T35,T6	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T33,T35,T6	Yes	T33,T35,T6	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T198,*T75,*T76	Yes	T198,T75,T76	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T33,T35,T6	Yes	T33,T35,T6	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T33,T35,T6	Yes	T33,T35,T6	INPUT
tl_edn1_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T33,T35,T6	Yes	T33,T35,T6	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T33,T35,T6	Yes	T33,T35,T6	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T33,T35,T6	Yes	T33,T35,T6	INPUT
tl_edn1_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T198,*T75,*T76	Yes	T198,T75,T76	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T33,*T35,*T6	Yes	T33,T35,T6	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T33,T35,T6	Yes	T33,T35,T6	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T1,T33,T34	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T1,*T9,*T4	Yes	T1,T9,T4	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T1,T9,T4	Yes	T1,T9,T4	INPUT
tl_otbn_o.d_ready	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T48,T263,T329	Yes	T48,T263,T329	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T247,T48,T263	Yes	T247,T48,T263	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T247,T48,T263	Yes	T247,T48,T263	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T48,T263,T329	Yes	T48,T263,T329	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T247,T48,T263	Yes	T247,T48,T263	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T77,*T78,*T52	Yes	T77,T78,T52	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T247,T48,T263	Yes	T247,T48,T263	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T247,T48,T263	Yes	T247,T48,T263	INPUT
tl_otbn_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T48,T263,T329	Yes	T48,T263,T329	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T48,T263,T329	Yes	T48,T263,T329	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T48,T263,T329	Yes	T48,T263,T329	INPUT
tl_otbn_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T77,*T78,*T52	Yes	T77,T78,T52	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T48,*T263,*T329	Yes	T48,T263,T329	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T48,T263,T329	Yes	T48,T263,T329	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T2,T33,T34	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T2,T33,T34	Yes	T2,T33,T34	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T33,T34	Yes	T2,T33,T34	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T2,T33,T34	Yes	T2,T33,T34	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T33,T34,T35	Yes	T33,T34,T35	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T2,T33,T34	Yes	T2,T33,T34	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T198,*T74,*T75	Yes	T198,T74,T75	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T2,T33,T34	Yes	T2,T33,T34	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T2,T33,T34	Yes	T2,T33,T34	INPUT
tl_keymgr_i.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T33,T34,T35	Yes	T33,T34,T35	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T33,T34,T35	Yes	T33,T34,T35	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T33,T34,T35	Yes	T33,T34,T35	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T198,*T74,*T75	Yes	T198,T74,T75	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T33,*T34,*T35	Yes	T2,T33,T34	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T2,T33,T34	Yes	T2,T33,T34	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T260,*T261,*T262	Yes	T260,T261,T262	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T1,T86,T87	Yes	T1,T86,T87	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T1,T86,T87	Yes	T1,T86,T87	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T75,*T76,*T79	Yes	T260,T261,T262	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T33,T34,T35	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T119,T67,T48	Yes	T119,T67,T48	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T119,T67,T48	Yes	T119,T67,T48	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T119,T67,T48	Yes	T119,T67,T48	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T119,T48,T49	Yes	T119,T48,T49	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T119,T67,T48	Yes	T119,T67,T48	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T442,*T74,*T75	Yes	T442,T74,T75	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T119,T67,T48	Yes	T119,T67,T48	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T119,T67,T48	Yes	T119,T67,T48	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T181,T309,T310	Yes	T181,T309,T310	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T119,T45,T46	Yes	T119,T67,T48	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T119,T45,T46	Yes	T119,T67,T48	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T442,T74,T75	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T119,*T177,*T178	Yes	T119,T111,T177	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T119,T67,T48	Yes	T119,T67,T48	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T33,T34,T35	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range