Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T179,T180,T304
0	1	Covered	T179,T180,T304
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T179,T180,T304
1	Covered	T179,T180,T304

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T179,T180,T304
1	Covered	T179,T180,T304

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T179,T180,T304
1	1	Covered	T179,T180,T304

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T179,T180,T304
1	0	Covered	T179,T180,T304
1	1	Covered	T179,T180,T304

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T179,T180,T304

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T179,T180,T304
0	Covered	T179,T180,T304

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T179,T180,T304
0	Covered	T179,T180,T304

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1045235888	1026786130	0	0
CheckNGreaterZero_A	2044	2044	0	0
GntImpliesReady_A	1045235888	8384	0	0
GntImpliesValid_A	1045235888	8384	0	0
GrantKnown_A	1045235888	1026786130	0	0
IdxKnown_A	1045235888	1026786130	0	0
IndexIsCorrect_A	1045235888	8384	0	0
NoReadyValidNoGrant_A	1045235888	0	0	0
Priority_A	1045235888	8384	0	0
ReadyAndValidImplyGrant_A	1045235888	8384	0	0
ReqAndReadyImplyGrant_A	1045235888	8384	0	0
ReqImpliesValid_A	1045235888	8384	0	0
ValidKnown_A	1045235888	1026786130	0	0
gen_data_port_assertion.DataFlow_A	1045235888	8384	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045235888	1026786130	0	0
T1	288340	288224	0	0
T2	499076	498966	0	0
T3	205644	205542	0	0
T33	753812	753586	0	0
T34	420234	419986	0	0
T35	1323954	1323742	0	0
T60	438486	438274	0	0
T86	1143036	1142934	0	0
T87	605714	605262	0	0
T88	306158	306042	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2044	2044	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T33	2	2	0	0
T34	2	2	0	0
T35	2	2	0	0
T60	2	2	0	0
T86	2	2	0	0
T87	2	2	0	0
T88	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045235888	8384	0	0
T20	951912	0	0	0
T27	263968	0	0	0
T70	466964	0	0	0
T137	637466	0	0	0
T177	413244	0	0	0
T179	170202	2794	0	0
T180	0	2798	0	0
T234	1904110	0	0	0
T304	0	2792	0	0
T306	1186998	0	0	0
T307	529364	0	0	0
T308	584708	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045235888	8384	0	0
T20	951912	0	0	0
T27	263968	0	0	0
T70	466964	0	0	0
T137	637466	0	0	0
T177	413244	0	0	0
T179	170202	2794	0	0
T180	0	2798	0	0
T234	1904110	0	0	0
T304	0	2792	0	0
T306	1186998	0	0	0
T307	529364	0	0	0
T308	584708	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045235888	1026786130	0	0
T1	288340	288224	0	0
T2	499076	498966	0	0
T3	205644	205542	0	0
T33	753812	753586	0	0
T34	420234	419986	0	0
T35	1323954	1323742	0	0
T60	438486	438274	0	0
T86	1143036	1142934	0	0
T87	605714	605262	0	0
T88	306158	306042	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045235888	1026786130	0	0
T1	288340	288224	0	0
T2	499076	498966	0	0
T3	205644	205542	0	0
T33	753812	753586	0	0
T34	420234	419986	0	0
T35	1323954	1323742	0	0
T60	438486	438274	0	0
T86	1143036	1142934	0	0
T87	605714	605262	0	0
T88	306158	306042	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045235888	8384	0	0
T20	951912	0	0	0
T27	263968	0	0	0
T70	466964	0	0	0
T137	637466	0	0	0
T177	413244	0	0	0
T179	170202	2794	0	0
T180	0	2798	0	0
T234	1904110	0	0	0
T304	0	2792	0	0
T306	1186998	0	0	0
T307	529364	0	0	0
T308	584708	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045235888	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045235888	8384	0	0
T20	951912	0	0	0
T27	263968	0	0	0
T70	466964	0	0	0
T137	637466	0	0	0
T177	413244	0	0	0
T179	170202	2794	0	0
T180	0	2798	0	0
T234	1904110	0	0	0
T304	0	2792	0	0
T306	1186998	0	0	0
T307	529364	0	0	0
T308	584708	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045235888	8384	0	0
T20	951912	0	0	0
T27	263968	0	0	0
T70	466964	0	0	0
T137	637466	0	0	0
T177	413244	0	0	0
T179	170202	2794	0	0
T180	0	2798	0	0
T234	1904110	0	0	0
T304	0	2792	0	0
T306	1186998	0	0	0
T307	529364	0	0	0
T308	584708	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045235888	8384	0	0
T20	951912	0	0	0
T27	263968	0	0	0
T70	466964	0	0	0
T137	637466	0	0	0
T177	413244	0	0	0
T179	170202	2794	0	0
T180	0	2798	0	0
T234	1904110	0	0	0
T304	0	2792	0	0
T306	1186998	0	0	0
T307	529364	0	0	0
T308	584708	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045235888	8384	0	0
T20	951912	0	0	0
T27	263968	0	0	0
T70	466964	0	0	0
T137	637466	0	0	0
T177	413244	0	0	0
T179	170202	2794	0	0
T180	0	2798	0	0
T234	1904110	0	0	0
T304	0	2792	0	0
T306	1186998	0	0	0
T307	529364	0	0	0
T308	584708	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045235888	1026786130	0	0
T1	288340	288224	0	0
T2	499076	498966	0	0
T3	205644	205542	0	0
T33	753812	753586	0	0
T34	420234	419986	0	0
T35	1323954	1323742	0	0
T60	438486	438274	0	0
T86	1143036	1142934	0	0
T87	605714	605262	0	0
T88	306158	306042	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045235888	8384	0	0
T20	951912	0	0	0
T27	263968	0	0	0
T70	466964	0	0	0
T137	637466	0	0	0
T177	413244	0	0	0
T179	170202	2794	0	0
T180	0	2798	0	0
T234	1904110	0	0	0
T304	0	2792	0	0
T306	1186998	0	0	0
T307	529364	0	0	0
T308	584708	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T179,T180,T304
0	1	Covered	T179,T180,T304
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T179,T180,T304
1	Covered	T179,T180,T304

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T179,T180,T304
1	Covered	T179,T180,T304

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T179,T180,T304
1	1	Covered	T179,T180,T304

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T179,T180,T304
1	0	Covered	T179,T180,T304
1	1	Covered	T179,T180,T304

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T179,T180,T304

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T179,T180,T304
0	Covered	T179,T180,T304

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T179,T180,T304
0	Covered	T179,T180,T304

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	522617944	513393065	0	0
CheckNGreaterZero_A	1022	1022	0	0
GntImpliesReady_A	522617944	5192	0	0
GntImpliesValid_A	522617944	5192	0	0
GrantKnown_A	522617944	513393065	0	0
IdxKnown_A	522617944	513393065	0	0
IndexIsCorrect_A	522617944	5192	0	0
NoReadyValidNoGrant_A	522617944	0	0	0
Priority_A	522617944	5192	0	0
ReadyAndValidImplyGrant_A	522617944	5192	0	0
ReqAndReadyImplyGrant_A	522617944	5192	0	0
ReqImpliesValid_A	522617944	5192	0	0
ValidKnown_A	522617944	513393065	0	0
gen_data_port_assertion.DataFlow_A	522617944	5192	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	513393065	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	5192	0	0
T20	475956	0	0	0
T27	131984	0	0	0
T70	233482	0	0	0
T137	318733	0	0	0
T177	206622	0	0	0
T179	85101	1730	0	0
T180	0	1734	0	0
T234	952055	0	0	0
T304	0	1728	0	0
T306	593499	0	0	0
T307	264682	0	0	0
T308	292354	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	5192	0	0
T20	475956	0	0	0
T27	131984	0	0	0
T70	233482	0	0	0
T137	318733	0	0	0
T177	206622	0	0	0
T179	85101	1730	0	0
T180	0	1734	0	0
T234	952055	0	0	0
T304	0	1728	0	0
T306	593499	0	0	0
T307	264682	0	0	0
T308	292354	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	513393065	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	513393065	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	5192	0	0
T20	475956	0	0	0
T27	131984	0	0	0
T70	233482	0	0	0
T137	318733	0	0	0
T177	206622	0	0	0
T179	85101	1730	0	0
T180	0	1734	0	0
T234	952055	0	0	0
T304	0	1728	0	0
T306	593499	0	0	0
T307	264682	0	0	0
T308	292354	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	5192	0	0
T20	475956	0	0	0
T27	131984	0	0	0
T70	233482	0	0	0
T137	318733	0	0	0
T177	206622	0	0	0
T179	85101	1730	0	0
T180	0	1734	0	0
T234	952055	0	0	0
T304	0	1728	0	0
T306	593499	0	0	0
T307	264682	0	0	0
T308	292354	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	5192	0	0
T20	475956	0	0	0
T27	131984	0	0	0
T70	233482	0	0	0
T137	318733	0	0	0
T177	206622	0	0	0
T179	85101	1730	0	0
T180	0	1734	0	0
T234	952055	0	0	0
T304	0	1728	0	0
T306	593499	0	0	0
T307	264682	0	0	0
T308	292354	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	5192	0	0
T20	475956	0	0	0
T27	131984	0	0	0
T70	233482	0	0	0
T137	318733	0	0	0
T177	206622	0	0	0
T179	85101	1730	0	0
T180	0	1734	0	0
T234	952055	0	0	0
T304	0	1728	0	0
T306	593499	0	0	0
T307	264682	0	0	0
T308	292354	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	5192	0	0
T20	475956	0	0	0
T27	131984	0	0	0
T70	233482	0	0	0
T137	318733	0	0	0
T177	206622	0	0	0
T179	85101	1730	0	0
T180	0	1734	0	0
T234	952055	0	0	0
T304	0	1728	0	0
T306	593499	0	0	0
T307	264682	0	0	0
T308	292354	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	513393065	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	5192	0	0
T20	475956	0	0	0
T27	131984	0	0	0
T70	233482	0	0	0
T137	318733	0	0	0
T177	206622	0	0	0
T179	85101	1730	0	0
T180	0	1734	0	0
T234	952055	0	0	0
T304	0	1728	0	0
T306	593499	0	0	0
T307	264682	0	0	0
T308	292354	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T179,T180,T304
0	1	Covered	T179,T180,T304
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T179,T180,T304
1	Covered	T179,T180,T304

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T179,T180,T304
1	Covered	T179,T180,T304

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T179,T180,T304
1	1	Covered	T179,T180,T304

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T179,T180,T304
1	0	Covered	T179,T180,T304
1	1	Covered	T179,T180,T304

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T179,T180,T304

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T179,T180,T304
0	Covered	T179,T180,T304

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T179,T180,T304
0	Covered	T179,T180,T304

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	522617944	513393065	0	0
CheckNGreaterZero_A	1022	1022	0	0
GntImpliesReady_A	522617944	3192	0	0
GntImpliesValid_A	522617944	3192	0	0
GrantKnown_A	522617944	513393065	0	0
IdxKnown_A	522617944	513393065	0	0
IndexIsCorrect_A	522617944	3192	0	0
NoReadyValidNoGrant_A	522617944	0	0	0
Priority_A	522617944	3192	0	0
ReadyAndValidImplyGrant_A	522617944	3192	0	0
ReqAndReadyImplyGrant_A	522617944	3192	0	0
ReqImpliesValid_A	522617944	3192	0	0
ValidKnown_A	522617944	513393065	0	0
gen_data_port_assertion.DataFlow_A	522617944	3192	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	513393065	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T35	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	3192	0	0
T20	475956	0	0	0
T27	131984	0	0	0
T70	233482	0	0	0
T137	318733	0	0	0
T177	206622	0	0	0
T179	85101	1064	0	0
T180	0	1064	0	0
T234	952055	0	0	0
T304	0	1064	0	0
T306	593499	0	0	0
T307	264682	0	0	0
T308	292354	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	3192	0	0
T20	475956	0	0	0
T27	131984	0	0	0
T70	233482	0	0	0
T137	318733	0	0	0
T177	206622	0	0	0
T179	85101	1064	0	0
T180	0	1064	0	0
T234	952055	0	0	0
T304	0	1064	0	0
T306	593499	0	0	0
T307	264682	0	0	0
T308	292354	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	513393065	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	513393065	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	3192	0	0
T20	475956	0	0	0
T27	131984	0	0	0
T70	233482	0	0	0
T137	318733	0	0	0
T177	206622	0	0	0
T179	85101	1064	0	0
T180	0	1064	0	0
T234	952055	0	0	0
T304	0	1064	0	0
T306	593499	0	0	0
T307	264682	0	0	0
T308	292354	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	3192	0	0
T20	475956	0	0	0
T27	131984	0	0	0
T70	233482	0	0	0
T137	318733	0	0	0
T177	206622	0	0	0
T179	85101	1064	0	0
T180	0	1064	0	0
T234	952055	0	0	0
T304	0	1064	0	0
T306	593499	0	0	0
T307	264682	0	0	0
T308	292354	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	3192	0	0
T20	475956	0	0	0
T27	131984	0	0	0
T70	233482	0	0	0
T137	318733	0	0	0
T177	206622	0	0	0
T179	85101	1064	0	0
T180	0	1064	0	0
T234	952055	0	0	0
T304	0	1064	0	0
T306	593499	0	0	0
T307	264682	0	0	0
T308	292354	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	3192	0	0
T20	475956	0	0	0
T27	131984	0	0	0
T70	233482	0	0	0
T137	318733	0	0	0
T177	206622	0	0	0
T179	85101	1064	0	0
T180	0	1064	0	0
T234	952055	0	0	0
T304	0	1064	0	0
T306	593499	0	0	0
T307	264682	0	0	0
T308	292354	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	3192	0	0
T20	475956	0	0	0
T27	131984	0	0	0
T70	233482	0	0	0
T137	318733	0	0	0
T177	206622	0	0	0
T179	85101	1064	0	0
T180	0	1064	0	0
T234	952055	0	0	0
T304	0	1064	0	0
T306	593499	0	0	0
T307	264682	0	0	0
T308	292354	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	513393065	0	0
T1	144170	144112	0	0
T2	249538	249483	0	0
T3	102822	102771	0	0
T33	376906	376793	0	0
T34	210117	209993	0	0
T35	661977	661871	0	0
T60	219243	219137	0	0
T86	571518	571467	0	0
T87	302857	302631	0	0
T88	153079	153021	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522617944	3192	0	0
T20	475956	0	0	0
T27	131984	0	0	0
T70	233482	0	0	0
T137	318733	0	0	0
T177	206622	0	0	0
T179	85101	1064	0	0
T180	0	1064	0	0
T234	952055	0	0	0
T304	0	1064	0	0
T306	593499	0	0	0
T307	264682	0	0	0
T308	292354	0	0	0