| T951 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3051124757 |
|
|
Jul 26 07:51:07 PM PDT 24 |
Jul 26 08:54:31 PM PDT 24 |
14753179138 ps |
| T952 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.214731681 |
|
|
Jul 26 07:47:04 PM PDT 24 |
Jul 26 07:54:53 PM PDT 24 |
4634611644 ps |
| T822 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.4040637374 |
|
|
Jul 26 08:08:26 PM PDT 24 |
Jul 26 08:16:47 PM PDT 24 |
4647044130 ps |
| T155 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.4052986319 |
|
|
Jul 26 08:01:01 PM PDT 24 |
Jul 26 09:04:21 PM PDT 24 |
19102906697 ps |
| T953 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2564962151 |
|
|
Jul 26 07:48:56 PM PDT 24 |
Jul 26 07:53:30 PM PDT 24 |
2552556688 ps |
| T785 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.4245206610 |
|
|
Jul 26 07:48:36 PM PDT 24 |
Jul 26 07:54:47 PM PDT 24 |
3833597320 ps |
| T741 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1392113669 |
|
|
Jul 26 08:11:19 PM PDT 24 |
Jul 26 08:18:15 PM PDT 24 |
3489600748 ps |
| T24 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.1252252562 |
|
|
Jul 26 07:42:31 PM PDT 24 |
Jul 26 07:52:38 PM PDT 24 |
3845676776 ps |
| T954 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2695837058 |
|
|
Jul 26 07:52:45 PM PDT 24 |
Jul 26 08:01:16 PM PDT 24 |
5586792080 ps |
| T955 |
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.562751352 |
|
|
Jul 26 08:10:31 PM PDT 24 |
Jul 26 08:16:48 PM PDT 24 |
3035359390 ps |
| T156 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2728832756 |
|
|
Jul 26 07:50:13 PM PDT 24 |
Jul 26 08:58:26 PM PDT 24 |
16952005992 ps |
| T333 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.4261148565 |
|
|
Jul 26 07:43:23 PM PDT 24 |
Jul 26 07:51:17 PM PDT 24 |
7203729500 ps |
| T291 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.37102213 |
|
|
Jul 26 07:42:53 PM PDT 24 |
Jul 26 07:50:45 PM PDT 24 |
4156737160 ps |
| T956 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1858881445 |
|
|
Jul 26 07:45:39 PM PDT 24 |
Jul 26 08:36:46 PM PDT 24 |
28349652450 ps |
| T74 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1964251664 |
|
|
Jul 26 07:43:55 PM PDT 24 |
Jul 26 07:52:54 PM PDT 24 |
4880500700 ps |
| T957 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1482798186 |
|
|
Jul 26 08:07:59 PM PDT 24 |
Jul 26 08:20:50 PM PDT 24 |
4171545248 ps |
| T167 |
/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2990807191 |
|
|
Jul 26 07:50:14 PM PDT 24 |
Jul 26 11:20:06 PM PDT 24 |
254645552322 ps |
| T958 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.3575224562 |
|
|
Jul 26 07:48:47 PM PDT 24 |
Jul 26 08:59:02 PM PDT 24 |
14763652620 ps |
| T959 |
/workspace/coverage/default/2.chip_sw_hmac_multistream.3796384268 |
|
|
Jul 26 08:03:08 PM PDT 24 |
Jul 26 08:28:18 PM PDT 24 |
7449287132 ps |
| T157 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.549054507 |
|
|
Jul 26 07:43:55 PM PDT 24 |
Jul 26 08:57:15 PM PDT 24 |
24901133140 ps |
| T960 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.619997029 |
|
|
Jul 26 07:46:09 PM PDT 24 |
Jul 26 08:06:46 PM PDT 24 |
5190592990 ps |
| T426 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.1398129442 |
|
|
Jul 26 08:11:19 PM PDT 24 |
Jul 26 08:21:35 PM PDT 24 |
5385562704 ps |
| T961 |
/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1063868857 |
|
|
Jul 26 07:45:22 PM PDT 24 |
Jul 26 07:49:07 PM PDT 24 |
3233788952 ps |
| T169 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.105640255 |
|
|
Jul 26 08:11:54 PM PDT 24 |
Jul 26 08:22:36 PM PDT 24 |
5628419724 ps |
| T838 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.100316835 |
|
|
Jul 26 08:17:00 PM PDT 24 |
Jul 26 08:28:30 PM PDT 24 |
5193954240 ps |
| T962 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.728821970 |
|
|
Jul 26 07:59:59 PM PDT 24 |
Jul 26 08:08:59 PM PDT 24 |
6499911240 ps |
| T243 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.395018361 |
|
|
Jul 26 08:01:36 PM PDT 24 |
Jul 26 08:35:20 PM PDT 24 |
9411265128 ps |
| T13 |
/workspace/coverage/default/1.chip_sw_power_virus.1185422705 |
|
|
Jul 26 07:57:58 PM PDT 24 |
Jul 26 08:25:33 PM PDT 24 |
5819280384 ps |
| T451 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.422146340 |
|
|
Jul 26 07:49:39 PM PDT 24 |
Jul 26 08:16:03 PM PDT 24 |
7541510000 ps |
| T963 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3334062807 |
|
|
Jul 26 08:05:55 PM PDT 24 |
Jul 26 08:15:01 PM PDT 24 |
5299438556 ps |
| T779 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2171505559 |
|
|
Jul 26 08:10:20 PM PDT 24 |
Jul 26 08:16:43 PM PDT 24 |
3995708530 ps |
| T139 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2147464425 |
|
|
Jul 26 08:07:28 PM PDT 24 |
Jul 26 08:23:12 PM PDT 24 |
5149805512 ps |
| T742 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.3531840484 |
|
|
Jul 26 08:03:25 PM PDT 24 |
Jul 26 08:14:08 PM PDT 24 |
7206224750 ps |
| T964 |
/workspace/coverage/default/2.chip_sival_flash_info_access.105140713 |
|
|
Jul 26 07:55:23 PM PDT 24 |
Jul 26 08:00:31 PM PDT 24 |
3568005816 ps |
| T836 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1839130816 |
|
|
Jul 26 08:14:42 PM PDT 24 |
Jul 26 08:26:46 PM PDT 24 |
5059282040 ps |
| T786 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.3130800513 |
|
|
Jul 26 07:45:13 PM PDT 24 |
Jul 26 08:26:55 PM PDT 24 |
9919023170 ps |
| T809 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2315142407 |
|
|
Jul 26 08:09:20 PM PDT 24 |
Jul 26 08:16:39 PM PDT 24 |
3649869784 ps |
| T75 |
/workspace/coverage/default/0.chip_jtag_mem_access.3734884599 |
|
|
Jul 26 07:35:37 PM PDT 24 |
Jul 26 07:59:34 PM PDT 24 |
14077341696 ps |
| T965 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.2279069509 |
|
|
Jul 26 07:56:00 PM PDT 24 |
Jul 26 09:00:35 PM PDT 24 |
15156425901 ps |
| T966 |
/workspace/coverage/default/1.chip_sw_hmac_multistream.3178407742 |
|
|
Jul 26 07:50:30 PM PDT 24 |
Jul 26 08:20:10 PM PDT 24 |
7100777512 ps |
| T967 |
/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3242531428 |
|
|
Jul 26 08:08:26 PM PDT 24 |
Jul 26 08:48:53 PM PDT 24 |
11589339551 ps |
| T32 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3384952694 |
|
|
Jul 26 07:46:43 PM PDT 24 |
Jul 26 07:53:02 PM PDT 24 |
3045833322 ps |
| T134 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.4271165214 |
|
|
Jul 26 07:50:32 PM PDT 24 |
Jul 26 08:03:32 PM PDT 24 |
5878945724 ps |
| T968 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3981126778 |
|
|
Jul 26 08:03:00 PM PDT 24 |
Jul 26 08:21:09 PM PDT 24 |
6661654280 ps |
| T969 |
/workspace/coverage/default/0.chip_sw_hmac_oneshot.492595805 |
|
|
Jul 26 07:45:11 PM PDT 24 |
Jul 26 07:50:15 PM PDT 24 |
3196012440 ps |
| T970 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2625243480 |
|
|
Jul 26 07:45:08 PM PDT 24 |
Jul 26 07:49:04 PM PDT 24 |
2476396180 ps |
| T971 |
/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1684026492 |
|
|
Jul 26 08:08:42 PM PDT 24 |
Jul 26 08:16:39 PM PDT 24 |
4456383896 ps |
| T755 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.629382551 |
|
|
Jul 26 08:08:48 PM PDT 24 |
Jul 26 08:22:10 PM PDT 24 |
6564658604 ps |
| T158 |
/workspace/coverage/default/0.rom_raw_unlock.106085952 |
|
|
Jul 26 07:50:14 PM PDT 24 |
Jul 26 07:54:54 PM PDT 24 |
5128922498 ps |
| T972 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3071992482 |
|
|
Jul 26 07:45:14 PM PDT 24 |
Jul 26 08:44:41 PM PDT 24 |
38622656316 ps |
| T110 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3533279241 |
|
|
Jul 26 07:46:49 PM PDT 24 |
Jul 26 07:50:59 PM PDT 24 |
4208112076 ps |
| T973 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.137059847 |
|
|
Jul 26 07:49:25 PM PDT 24 |
Jul 26 07:53:29 PM PDT 24 |
3178932512 ps |
| T209 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2728100260 |
|
|
Jul 26 07:47:46 PM PDT 24 |
Jul 26 07:59:29 PM PDT 24 |
4796885091 ps |
| T974 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.1591617030 |
|
|
Jul 26 08:01:00 PM PDT 24 |
Jul 26 08:20:28 PM PDT 24 |
5833576032 ps |
| T975 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4122838980 |
|
|
Jul 26 07:48:05 PM PDT 24 |
Jul 26 07:58:28 PM PDT 24 |
3775557856 ps |
| T976 |
/workspace/coverage/default/2.chip_sw_aes_entropy.1669458871 |
|
|
Jul 26 08:01:30 PM PDT 24 |
Jul 26 08:05:18 PM PDT 24 |
2636326400 ps |
| T192 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.217614023 |
|
|
Jul 26 07:49:05 PM PDT 24 |
Jul 26 07:56:41 PM PDT 24 |
3722717330 ps |
| T977 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.795407706 |
|
|
Jul 26 08:00:34 PM PDT 24 |
Jul 26 08:30:28 PM PDT 24 |
7107484872 ps |
| T193 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2471638167 |
|
|
Jul 26 08:02:19 PM PDT 24 |
Jul 26 08:15:47 PM PDT 24 |
6989200980 ps |
| T177 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.724769701 |
|
|
Jul 26 07:47:43 PM PDT 24 |
Jul 26 07:51:27 PM PDT 24 |
2923980523 ps |
| T815 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.3218140874 |
|
|
Jul 26 08:14:24 PM PDT 24 |
Jul 26 08:24:22 PM PDT 24 |
6350247166 ps |
| T8 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3264989156 |
|
|
Jul 26 07:58:02 PM PDT 24 |
Jul 26 08:02:25 PM PDT 24 |
3387105729 ps |
| T978 |
/workspace/coverage/default/2.chip_sw_aes_enc.1134386215 |
|
|
Jul 26 08:00:57 PM PDT 24 |
Jul 26 08:05:22 PM PDT 24 |
2587945000 ps |
| T979 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2004412632 |
|
|
Jul 26 08:08:59 PM PDT 24 |
Jul 26 08:23:05 PM PDT 24 |
10442270736 ps |
| T980 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.71038864 |
|
|
Jul 26 07:44:41 PM PDT 24 |
Jul 26 08:31:48 PM PDT 24 |
13038535567 ps |
| T981 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.4291855614 |
|
|
Jul 26 07:45:53 PM PDT 24 |
Jul 26 08:10:16 PM PDT 24 |
8104645732 ps |
| T37 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3590166948 |
|
|
Jul 26 07:46:49 PM PDT 24 |
Jul 26 07:56:42 PM PDT 24 |
6423895504 ps |
| T217 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1848930509 |
|
|
Jul 26 07:41:40 PM PDT 24 |
Jul 26 11:34:47 PM PDT 24 |
79352195139 ps |
| T412 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.3430056972 |
|
|
Jul 26 07:43:26 PM PDT 24 |
Jul 26 07:48:02 PM PDT 24 |
3544914186 ps |
| T982 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3109822394 |
|
|
Jul 26 07:48:10 PM PDT 24 |
Jul 26 07:52:03 PM PDT 24 |
3306899802 ps |
| T983 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.1462406883 |
|
|
Jul 26 08:09:45 PM PDT 24 |
Jul 26 09:19:42 PM PDT 24 |
15178666718 ps |
| T984 |
/workspace/coverage/default/2.chip_sw_uart_smoketest.3146233718 |
|
|
Jul 26 08:05:09 PM PDT 24 |
Jul 26 08:10:44 PM PDT 24 |
2585248940 ps |
| T283 |
/workspace/coverage/default/1.rom_e2e_shutdown_output.3572831390 |
|
|
Jul 26 07:58:53 PM PDT 24 |
Jul 26 08:53:57 PM PDT 24 |
24353428939 ps |
| T985 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.1807540504 |
|
|
Jul 26 08:06:41 PM PDT 24 |
Jul 26 08:12:49 PM PDT 24 |
3020036100 ps |
| T182 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.568946497 |
|
|
Jul 26 08:03:29 PM PDT 24 |
Jul 26 08:13:46 PM PDT 24 |
5271406834 ps |
| T135 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.66893339 |
|
|
Jul 26 07:45:55 PM PDT 24 |
Jul 26 07:54:02 PM PDT 24 |
5047877992 ps |
| T179 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.1876081945 |
|
|
Jul 26 08:06:49 PM PDT 24 |
Jul 26 08:15:20 PM PDT 24 |
4746705972 ps |
| T743 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.2172776199 |
|
|
Jul 26 08:13:45 PM PDT 24 |
Jul 26 08:26:38 PM PDT 24 |
5826868432 ps |
| T986 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.2656239295 |
|
|
Jul 26 07:44:17 PM PDT 24 |
Jul 26 07:48:53 PM PDT 24 |
2125936574 ps |
| T987 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.4220243599 |
|
|
Jul 26 07:46:14 PM PDT 24 |
Jul 26 08:05:54 PM PDT 24 |
8482341660 ps |
| T25 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.1892805285 |
|
|
Jul 26 07:43:01 PM PDT 24 |
Jul 26 08:57:18 PM PDT 24 |
19360931732 ps |
| T988 |
/workspace/coverage/default/0.chip_sw_aes_enc.503460205 |
|
|
Jul 26 07:46:15 PM PDT 24 |
Jul 26 07:51:51 PM PDT 24 |
3337728162 ps |
| T363 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.2432166259 |
|
|
Jul 26 07:48:35 PM PDT 24 |
Jul 26 07:54:23 PM PDT 24 |
3655601828 ps |
| T273 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.217029321 |
|
|
Jul 26 07:46:38 PM PDT 24 |
Jul 26 08:21:37 PM PDT 24 |
11424598006 ps |
| T989 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.1045124156 |
|
|
Jul 26 07:55:06 PM PDT 24 |
Jul 26 07:59:05 PM PDT 24 |
2164364500 ps |
| T367 |
/workspace/coverage/default/1.chip_sw_hmac_enc.827610477 |
|
|
Jul 26 07:48:55 PM PDT 24 |
Jul 26 07:55:25 PM PDT 24 |
3485664032 ps |
| T377 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1491347815 |
|
|
Jul 26 07:44:50 PM PDT 24 |
Jul 26 07:54:16 PM PDT 24 |
19088557872 ps |
| T990 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3884660249 |
|
|
Jul 26 07:42:24 PM PDT 24 |
Jul 26 07:52:16 PM PDT 24 |
4566725056 ps |
| T991 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.1692267156 |
|
|
Jul 26 08:08:45 PM PDT 24 |
Jul 26 09:10:55 PM PDT 24 |
15032006410 ps |
| T98 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2477608062 |
|
|
Jul 26 07:44:07 PM PDT 24 |
Jul 26 07:51:12 PM PDT 24 |
7084419698 ps |
| T749 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3544942234 |
|
|
Jul 26 08:14:40 PM PDT 24 |
Jul 26 08:21:10 PM PDT 24 |
3482060220 ps |
| T992 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1395112297 |
|
|
Jul 26 07:55:08 PM PDT 24 |
Jul 26 07:58:46 PM PDT 24 |
2788897049 ps |
| T140 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1052199788 |
|
|
Jul 26 08:10:23 PM PDT 24 |
Jul 26 08:27:42 PM PDT 24 |
7628197364 ps |
| T993 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx.75760706 |
|
|
Jul 26 08:05:55 PM PDT 24 |
Jul 26 08:16:40 PM PDT 24 |
4461735336 ps |
| T994 |
/workspace/coverage/default/2.chip_sw_example_concurrency.935120500 |
|
|
Jul 26 07:56:11 PM PDT 24 |
Jul 26 08:01:03 PM PDT 24 |
3328691224 ps |
| T995 |
/workspace/coverage/default/0.chip_sw_aes_idle.172075636 |
|
|
Jul 26 07:44:27 PM PDT 24 |
Jul 26 07:48:04 PM PDT 24 |
3312044960 ps |
| T996 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.821491162 |
|
|
Jul 26 07:56:53 PM PDT 24 |
Jul 26 08:09:55 PM PDT 24 |
4286334424 ps |
| T64 |
/workspace/coverage/default/3.chip_tap_straps_testunlock0.1516178660 |
|
|
Jul 26 08:05:08 PM PDT 24 |
Jul 26 08:15:49 PM PDT 24 |
5738493239 ps |
| T200 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3446582649 |
|
|
Jul 26 07:42:31 PM PDT 24 |
Jul 26 09:10:09 PM PDT 24 |
43195856465 ps |
| T762 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.4111644034 |
|
|
Jul 26 07:43:56 PM PDT 24 |
Jul 26 07:53:37 PM PDT 24 |
3918627452 ps |
| T57 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1797093697 |
|
|
Jul 26 07:56:59 PM PDT 24 |
Jul 26 08:03:07 PM PDT 24 |
5735570064 ps |
| T163 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.3968200095 |
|
|
Jul 26 08:02:43 PM PDT 24 |
Jul 26 08:13:01 PM PDT 24 |
4056272566 ps |
| T257 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.3986305040 |
|
|
Jul 26 08:08:36 PM PDT 24 |
Jul 26 08:15:35 PM PDT 24 |
5781729280 ps |
| T997 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.284202132 |
|
|
Jul 26 08:07:16 PM PDT 24 |
Jul 26 08:17:23 PM PDT 24 |
7132170896 ps |
| T386 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.2987287141 |
|
|
Jul 26 08:10:18 PM PDT 24 |
Jul 26 08:23:31 PM PDT 24 |
6034140054 ps |
| T388 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3422216975 |
|
|
Jul 26 08:07:40 PM PDT 24 |
Jul 26 08:15:42 PM PDT 24 |
4146076272 ps |
| T389 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2883176632 |
|
|
Jul 26 08:06:46 PM PDT 24 |
Jul 26 08:15:48 PM PDT 24 |
4244699822 ps |
| T390 |
/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.1219082645 |
|
|
Jul 26 07:56:18 PM PDT 24 |
Jul 26 08:00:30 PM PDT 24 |
2504448232 ps |
| T391 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.2036210273 |
|
|
Jul 26 07:52:12 PM PDT 24 |
Jul 26 07:55:28 PM PDT 24 |
2929620104 ps |
| T201 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3807595590 |
|
|
Jul 26 07:57:17 PM PDT 24 |
Jul 26 09:42:09 PM PDT 24 |
43667041983 ps |
| T392 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.346114955 |
|
|
Jul 26 07:44:48 PM PDT 24 |
Jul 26 07:51:28 PM PDT 24 |
4551301256 ps |
| T393 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.1070800906 |
|
|
Jul 26 07:55:54 PM PDT 24 |
Jul 26 08:00:26 PM PDT 24 |
2445876984 ps |
| T394 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.444407270 |
|
|
Jul 26 08:10:43 PM PDT 24 |
Jul 26 08:24:51 PM PDT 24 |
5798905402 ps |
| T65 |
/workspace/coverage/default/4.chip_tap_straps_rma.1188730675 |
|
|
Jul 26 08:05:50 PM PDT 24 |
Jul 26 08:13:53 PM PDT 24 |
4950692244 ps |
| T787 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.1094899873 |
|
|
Jul 26 07:54:45 PM PDT 24 |
Jul 26 08:35:40 PM PDT 24 |
10424038584 ps |
| T267 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.2123960253 |
|
|
Jul 26 08:13:36 PM PDT 24 |
Jul 26 08:22:29 PM PDT 24 |
4091186440 ps |
| T317 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3622684885 |
|
|
Jul 26 07:49:32 PM PDT 24 |
Jul 26 08:10:54 PM PDT 24 |
9166665114 ps |
| T284 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3065193950 |
|
|
Jul 26 07:55:56 PM PDT 24 |
Jul 26 09:44:26 PM PDT 24 |
22541335320 ps |
| T998 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2473506673 |
|
|
Jul 26 08:05:44 PM PDT 24 |
Jul 26 08:22:14 PM PDT 24 |
9500883727 ps |
| T287 |
/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2013576636 |
|
|
Jul 26 08:02:05 PM PDT 24 |
Jul 26 08:11:41 PM PDT 24 |
9942300113 ps |
| T999 |
/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2209147253 |
|
|
Jul 26 07:55:39 PM PDT 24 |
Jul 26 07:59:10 PM PDT 24 |
3061776472 ps |
| T771 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3785373893 |
|
|
Jul 26 08:06:42 PM PDT 24 |
Jul 26 08:13:58 PM PDT 24 |
3739916786 ps |
| T285 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3026456967 |
|
|
Jul 26 07:51:45 PM PDT 24 |
Jul 26 08:53:30 PM PDT 24 |
14793750788 ps |
| T194 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1714896662 |
|
|
Jul 26 07:47:41 PM PDT 24 |
Jul 26 07:59:54 PM PDT 24 |
5268687794 ps |
| T1000 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.893988306 |
|
|
Jul 26 07:48:17 PM PDT 24 |
Jul 26 07:59:26 PM PDT 24 |
4461592302 ps |
| T1001 |
/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.942472902 |
|
|
Jul 26 08:05:40 PM PDT 24 |
Jul 26 09:09:09 PM PDT 24 |
16238538850 ps |
| T1002 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.1777459736 |
|
|
Jul 26 08:05:08 PM PDT 24 |
Jul 26 08:14:44 PM PDT 24 |
3806598904 ps |
| T1003 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod.4156344400 |
|
|
Jul 26 07:57:38 PM PDT 24 |
Jul 26 08:57:10 PM PDT 24 |
15526049935 ps |
| T165 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2910125751 |
|
|
Jul 26 07:42:50 PM PDT 24 |
Jul 26 07:56:52 PM PDT 24 |
6134454922 ps |
| T706 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.4000745464 |
|
|
Jul 26 08:00:11 PM PDT 24 |
Jul 26 08:01:56 PM PDT 24 |
1923944352 ps |
| T1004 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access.402939818 |
|
|
Jul 26 07:59:00 PM PDT 24 |
Jul 26 08:15:43 PM PDT 24 |
5743199116 ps |
| T1005 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1022932198 |
|
|
Jul 26 07:51:22 PM PDT 24 |
Jul 26 08:02:39 PM PDT 24 |
4541735722 ps |
| T338 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3984974420 |
|
|
Jul 26 07:56:38 PM PDT 24 |
Jul 26 08:06:51 PM PDT 24 |
4002655372 ps |
| T1006 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.465634594 |
|
|
Jul 26 07:51:11 PM PDT 24 |
Jul 26 08:03:12 PM PDT 24 |
4208824120 ps |
| T159 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3347611356 |
|
|
Jul 26 07:44:23 PM PDT 24 |
Jul 26 10:36:08 PM PDT 24 |
57721612264 ps |
| T1007 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.258181037 |
|
|
Jul 26 07:48:40 PM PDT 24 |
Jul 26 08:07:56 PM PDT 24 |
7767399712 ps |
| T1008 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2469171887 |
|
|
Jul 26 08:03:59 PM PDT 24 |
Jul 26 08:17:37 PM PDT 24 |
3596926040 ps |
| T1009 |
/workspace/coverage/default/1.chip_tap_straps_dev.1542751493 |
|
|
Jul 26 07:51:04 PM PDT 24 |
Jul 26 07:56:32 PM PDT 24 |
4419626368 ps |
| T1010 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.3263062 |
|
|
Jul 26 07:52:54 PM PDT 24 |
Jul 26 09:01:27 PM PDT 24 |
26197753236 ps |
| T1011 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1469463419 |
|
|
Jul 26 08:04:26 PM PDT 24 |
Jul 26 09:04:52 PM PDT 24 |
25158302734 ps |
| T1012 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3138168298 |
|
|
Jul 26 07:58:51 PM PDT 24 |
Jul 26 08:04:37 PM PDT 24 |
4144924672 ps |
| T1013 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1992287567 |
|
|
Jul 26 07:44:41 PM PDT 24 |
Jul 26 08:01:20 PM PDT 24 |
7758144709 ps |
| T1014 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.375658450 |
|
|
Jul 26 07:51:49 PM PDT 24 |
Jul 26 08:03:31 PM PDT 24 |
4647559668 ps |
| T292 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3910700363 |
|
|
Jul 26 07:43:27 PM PDT 24 |
Jul 26 07:53:46 PM PDT 24 |
4702923211 ps |
| T1015 |
/workspace/coverage/default/1.rom_keymgr_functest.3443223566 |
|
|
Jul 26 07:54:59 PM PDT 24 |
Jul 26 08:06:14 PM PDT 24 |
5603817244 ps |
| T1016 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2072546945 |
|
|
Jul 26 08:10:06 PM PDT 24 |
Jul 26 08:20:07 PM PDT 24 |
4135777290 ps |
| T1017 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2987254668 |
|
|
Jul 26 07:42:34 PM PDT 24 |
Jul 26 07:46:56 PM PDT 24 |
3084316443 ps |
| T1018 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.207092332 |
|
|
Jul 26 07:45:34 PM PDT 24 |
Jul 26 08:48:29 PM PDT 24 |
45044283320 ps |
| T1019 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3896657092 |
|
|
Jul 26 07:44:35 PM PDT 24 |
Jul 26 08:09:10 PM PDT 24 |
7970968850 ps |
| T1020 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1739404007 |
|
|
Jul 26 08:02:55 PM PDT 24 |
Jul 26 08:13:17 PM PDT 24 |
7272222679 ps |
| T1021 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.3675796500 |
|
|
Jul 26 07:47:33 PM PDT 24 |
Jul 26 07:52:20 PM PDT 24 |
2563262764 ps |
| T1022 |
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2536196646 |
|
|
Jul 26 08:06:20 PM PDT 24 |
Jul 26 09:23:13 PM PDT 24 |
18296454400 ps |
| T249 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.316462604 |
|
|
Jul 26 07:42:15 PM PDT 24 |
Jul 26 09:21:43 PM PDT 24 |
48523592425 ps |
| T1023 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1645973920 |
|
|
Jul 26 07:53:07 PM PDT 24 |
Jul 26 09:02:14 PM PDT 24 |
24347775211 ps |
| T148 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.3151839963 |
|
|
Jul 26 07:47:27 PM PDT 24 |
Jul 26 07:53:23 PM PDT 24 |
3596880040 ps |
| T1024 |
/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.533188615 |
|
|
Jul 26 08:08:52 PM PDT 24 |
Jul 26 08:49:43 PM PDT 24 |
13063714552 ps |
| T783 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1183761480 |
|
|
Jul 26 07:48:34 PM PDT 24 |
Jul 26 07:56:51 PM PDT 24 |
4424860722 ps |
| T438 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.286890741 |
|
|
Jul 26 08:05:03 PM PDT 24 |
Jul 26 08:11:11 PM PDT 24 |
3787106720 ps |
| T383 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2858794087 |
|
|
Jul 26 07:43:43 PM PDT 24 |
Jul 26 07:50:52 PM PDT 24 |
5961177704 ps |
| T173 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.21717762 |
|
|
Jul 26 08:15:15 PM PDT 24 |
Jul 26 08:22:37 PM PDT 24 |
4115867736 ps |
| T409 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2645520681 |
|
|
Jul 26 08:11:56 PM PDT 24 |
Jul 26 08:19:47 PM PDT 24 |
3427710300 ps |
| T707 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.4272384292 |
|
|
Jul 26 07:45:30 PM PDT 24 |
Jul 26 07:47:10 PM PDT 24 |
2928760630 ps |
| T752 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.3809060557 |
|
|
Jul 26 08:07:16 PM PDT 24 |
Jul 26 08:15:11 PM PDT 24 |
4397700296 ps |
| T313 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.4207178315 |
|
|
Jul 26 08:05:22 PM PDT 24 |
Jul 26 08:09:32 PM PDT 24 |
2702976044 ps |
| T149 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.388130988 |
|
|
Jul 26 07:49:52 PM PDT 24 |
Jul 26 07:58:30 PM PDT 24 |
7669725125 ps |
| T355 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.458969709 |
|
|
Jul 26 07:42:37 PM PDT 24 |
Jul 26 07:54:52 PM PDT 24 |
4469975640 ps |
| T1025 |
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1321346292 |
|
|
Jul 26 08:08:02 PM PDT 24 |
Jul 26 08:15:21 PM PDT 24 |
5751227161 ps |
| T777 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1921691237 |
|
|
Jul 26 08:14:37 PM PDT 24 |
Jul 26 08:21:00 PM PDT 24 |
3240945570 ps |
| T1026 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.4168401188 |
|
|
Jul 26 07:51:06 PM PDT 24 |
Jul 26 08:45:07 PM PDT 24 |
29245523758 ps |
| T1027 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx.4031222469 |
|
|
Jul 26 07:48:14 PM PDT 24 |
Jul 26 07:57:26 PM PDT 24 |
4467837652 ps |
| T1028 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1054225992 |
|
|
Jul 26 08:07:46 PM PDT 24 |
Jul 26 08:31:09 PM PDT 24 |
12710919143 ps |
| T1029 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2316175766 |
|
|
Jul 26 07:59:10 PM PDT 24 |
Jul 26 08:27:42 PM PDT 24 |
9692542638 ps |
| T788 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1490544018 |
|
|
Jul 26 08:14:56 PM PDT 24 |
Jul 26 08:21:30 PM PDT 24 |
3324379064 ps |
| T22 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.3149075687 |
|
|
Jul 26 07:42:57 PM PDT 24 |
Jul 26 08:11:56 PM PDT 24 |
25264042344 ps |
| T222 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3707023097 |
|
|
Jul 26 07:46:35 PM PDT 24 |
Jul 26 07:56:21 PM PDT 24 |
4905127231 ps |
| T1030 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.8822995 |
|
|
Jul 26 07:59:22 PM PDT 24 |
Jul 26 08:06:10 PM PDT 24 |
4686349584 ps |
| T1031 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3136704171 |
|
|
Jul 26 07:44:52 PM PDT 24 |
Jul 26 07:54:46 PM PDT 24 |
5274563160 ps |
| T410 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2802940288 |
|
|
Jul 26 08:13:37 PM PDT 24 |
Jul 26 08:21:12 PM PDT 24 |
4356491976 ps |
| T385 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1295913926 |
|
|
Jul 26 08:15:21 PM PDT 24 |
Jul 26 08:21:45 PM PDT 24 |
4126132070 ps |
| T115 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1964682240 |
|
|
Jul 26 07:53:41 PM PDT 24 |
Jul 26 08:44:03 PM PDT 24 |
14724938539 ps |
| T1032 |
/workspace/coverage/default/1.chip_sw_example_concurrency.916343234 |
|
|
Jul 26 07:44:25 PM PDT 24 |
Jul 26 07:47:54 PM PDT 24 |
2835970064 ps |
| T1033 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4219832596 |
|
|
Jul 26 08:03:19 PM PDT 24 |
Jul 26 08:16:32 PM PDT 24 |
5160710008 ps |
| T368 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1538890548 |
|
|
Jul 26 07:43:15 PM PDT 24 |
Jul 26 07:47:37 PM PDT 24 |
3120746476 ps |
| T1034 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2109723873 |
|
|
Jul 26 07:51:19 PM PDT 24 |
Jul 26 08:01:48 PM PDT 24 |
3961581310 ps |
| T427 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.974951152 |
|
|
Jul 26 08:17:45 PM PDT 24 |
Jul 26 08:30:20 PM PDT 24 |
5670702052 ps |
| T387 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.98941573 |
|
|
Jul 26 08:11:07 PM PDT 24 |
Jul 26 08:21:41 PM PDT 24 |
4651712190 ps |
| T528 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1685846115 |
|
|
Jul 26 08:02:19 PM PDT 24 |
Jul 26 08:35:17 PM PDT 24 |
11987594691 ps |
| T1035 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2553122310 |
|
|
Jul 26 07:53:13 PM PDT 24 |
Jul 26 09:06:39 PM PDT 24 |
14308341303 ps |
| T1036 |
/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.870421603 |
|
|
Jul 26 07:45:15 PM PDT 24 |
Jul 26 07:54:22 PM PDT 24 |
4633058754 ps |
| T1037 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.2530657773 |
|
|
Jul 26 07:55:59 PM PDT 24 |
Jul 26 08:00:13 PM PDT 24 |
2584295176 ps |
| T1038 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3354387194 |
|
|
Jul 26 08:06:47 PM PDT 24 |
Jul 26 08:17:17 PM PDT 24 |
4115310580 ps |
| T1039 |
/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.2511643653 |
|
|
Jul 26 08:13:02 PM PDT 24 |
Jul 26 08:23:48 PM PDT 24 |
6990695602 ps |
| T289 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.3521174094 |
|
|
Jul 26 07:56:48 PM PDT 24 |
Jul 26 08:12:41 PM PDT 24 |
5176799964 ps |
| T1040 |
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3574607421 |
|
|
Jul 26 08:09:20 PM PDT 24 |
Jul 26 09:19:45 PM PDT 24 |
18101890024 ps |
| T1041 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3869243388 |
|
|
Jul 26 07:42:15 PM PDT 24 |
Jul 26 07:56:56 PM PDT 24 |
10141252942 ps |
| T1042 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1126445318 |
|
|
Jul 26 07:48:30 PM PDT 24 |
Jul 26 08:49:45 PM PDT 24 |
14516481628 ps |
| T1043 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3766649156 |
|
|
Jul 26 08:04:30 PM PDT 24 |
Jul 26 08:15:51 PM PDT 24 |
4396054296 ps |
| T1044 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1868647942 |
|
|
Jul 26 08:00:48 PM PDT 24 |
Jul 26 08:26:49 PM PDT 24 |
8272971412 ps |
| T99 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2217941864 |
|
|
Jul 26 07:48:02 PM PDT 24 |
Jul 26 08:13:12 PM PDT 24 |
22405056312 ps |
| T1045 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2620459426 |
|
|
Jul 26 07:51:31 PM PDT 24 |
Jul 26 09:04:29 PM PDT 24 |
14249668499 ps |
| T1046 |
/workspace/coverage/default/1.rom_e2e_self_hash.794753449 |
|
|
Jul 26 08:00:45 PM PDT 24 |
Jul 26 09:48:08 PM PDT 24 |
27050163400 ps |
| T1047 |
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2173181546 |
|
|
Jul 26 07:57:40 PM PDT 24 |
Jul 26 08:15:03 PM PDT 24 |
9704342504 ps |
| T23 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1089228345 |
|
|
Jul 26 08:01:32 PM PDT 24 |
Jul 26 09:11:27 PM PDT 24 |
20177426988 ps |
| T1048 |
/workspace/coverage/default/0.rom_e2e_smoke.3448682073 |
|
|
Jul 26 07:48:20 PM PDT 24 |
Jul 26 09:00:01 PM PDT 24 |
15542374752 ps |
| T693 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.2484331852 |
|
|
Jul 26 08:15:34 PM PDT 24 |
Jul 26 08:25:48 PM PDT 24 |
4422475064 ps |
| T1049 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3284707686 |
|
|
Jul 26 07:50:25 PM PDT 24 |
Jul 26 08:05:23 PM PDT 24 |
7764369992 ps |
| T153 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.2151122402 |
|
|
Jul 26 07:42:23 PM PDT 24 |
Jul 26 08:38:40 PM PDT 24 |
12083288802 ps |
| T1050 |
/workspace/coverage/default/2.rom_e2e_static_critical.2348732943 |
|
|
Jul 26 08:10:14 PM PDT 24 |
Jul 26 09:25:50 PM PDT 24 |
17695456956 ps |
| T1051 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2206999720 |
|
|
Jul 26 08:07:16 PM PDT 24 |
Jul 26 08:18:09 PM PDT 24 |
8075983506 ps |
| T782 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2900603000 |
|
|
Jul 26 08:08:05 PM PDT 24 |
Jul 26 08:15:41 PM PDT 24 |
4114012888 ps |
| T1052 |
/workspace/coverage/default/3.chip_tap_straps_prod.4059681085 |
|
|
Jul 26 08:05:40 PM PDT 24 |
Jul 26 08:08:28 PM PDT 24 |
3364833827 ps |
| T396 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1690722697 |
|
|
Jul 26 08:12:46 PM PDT 24 |
Jul 26 08:19:37 PM PDT 24 |
3789184712 ps |
| T781 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.2607431531 |
|
|
Jul 26 07:51:49 PM PDT 24 |
Jul 26 08:15:19 PM PDT 24 |
7744135770 ps |
| T756 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.3990094082 |
|
|
Jul 26 08:13:24 PM PDT 24 |
Jul 26 08:23:18 PM PDT 24 |
5491482100 ps |
| T1053 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3040367665 |
|
|
Jul 26 08:03:47 PM PDT 24 |
Jul 26 08:24:56 PM PDT 24 |
6487058756 ps |
| T1054 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2258541999 |
|
|
Jul 26 07:47:57 PM PDT 24 |
Jul 26 08:40:50 PM PDT 24 |
13481769164 ps |
| T1055 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.958490605 |
|
|
Jul 26 08:02:39 PM PDT 24 |
Jul 26 08:58:30 PM PDT 24 |
27021147020 ps |
| T1056 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.693552269 |
|
|
Jul 26 07:43:25 PM PDT 24 |
Jul 26 07:52:27 PM PDT 24 |
4922426220 ps |
| T276 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2034374448 |
|
|
Jul 26 07:43:24 PM PDT 24 |
Jul 26 07:55:05 PM PDT 24 |
5601465154 ps |
| T51 |
/workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.2836546197 |
|
|
Jul 26 07:49:55 PM PDT 24 |
Jul 26 07:54:30 PM PDT 24 |
3465828321 ps |
| T766 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2978222786 |
|
|
Jul 26 08:14:21 PM PDT 24 |
Jul 26 08:22:47 PM PDT 24 |
4326700260 ps |
| T1057 |
/workspace/coverage/default/2.chip_sw_csrng_kat_test.2605431167 |
|
|
Jul 26 08:00:57 PM PDT 24 |
Jul 26 08:05:12 PM PDT 24 |
3695546850 ps |
| T1058 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.3309227507 |
|
|
Jul 26 08:07:19 PM PDT 24 |
Jul 26 08:17:11 PM PDT 24 |
6179195145 ps |
| T1059 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2449201177 |
|
|
Jul 26 07:54:16 PM PDT 24 |
Jul 26 08:00:22 PM PDT 24 |
3786276752 ps |
| T1060 |
/workspace/coverage/default/0.chip_sw_flash_crash_alert.2386428793 |
|
|
Jul 26 07:44:29 PM PDT 24 |
Jul 26 07:55:22 PM PDT 24 |
6069811976 ps |
| T293 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.1720940021 |
|
|
Jul 26 07:43:30 PM PDT 24 |
Jul 26 07:55:52 PM PDT 24 |
5597096248 ps |
| T277 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.2520495166 |
|
|
Jul 26 08:12:27 PM PDT 24 |
Jul 26 08:26:07 PM PDT 24 |
6155880660 ps |
| T1061 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.1745583144 |
|
|
Jul 26 08:05:11 PM PDT 24 |
Jul 26 08:09:27 PM PDT 24 |
3212842568 ps |
| T425 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.3912903546 |
|
|
Jul 26 07:45:35 PM PDT 24 |
Jul 26 07:48:09 PM PDT 24 |
2639100834 ps |
| T446 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.3341331983 |
|
|
Jul 26 08:14:24 PM PDT 24 |
Jul 26 08:24:45 PM PDT 24 |
5405865588 ps |
| T1062 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1106773414 |
|
|
Jul 26 07:47:23 PM PDT 24 |
Jul 26 07:54:23 PM PDT 24 |
5873493028 ps |
| T358 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1091531564 |
|
|
Jul 26 07:55:43 PM PDT 24 |
Jul 26 08:07:53 PM PDT 24 |
4647653915 ps |
| T1063 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3911024821 |
|
|
Jul 26 08:05:59 PM PDT 24 |
Jul 26 08:33:59 PM PDT 24 |
8082352307 ps |
| T254 |
/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3453122043 |
|
|
Jul 26 07:53:44 PM PDT 24 |
Jul 26 08:38:11 PM PDT 24 |
24490312055 ps |
| T116 |
/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.876563468 |
|
|
Jul 26 08:04:45 PM PDT 24 |
Jul 26 08:44:38 PM PDT 24 |
18404623506 ps |
| T384 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4222356175 |
|
|
Jul 26 08:02:15 PM PDT 24 |
Jul 26 08:10:42 PM PDT 24 |
6938232000 ps |
| T1064 |
/workspace/coverage/default/1.chip_sw_kmac_idle.2318727205 |
|
|
Jul 26 07:52:08 PM PDT 24 |
Jul 26 07:55:37 PM PDT 24 |
3119444632 ps |
| T773 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.671910378 |
|
|
Jul 26 08:13:46 PM PDT 24 |
Jul 26 08:24:14 PM PDT 24 |
4603324904 ps |
| T445 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3600570513 |
|
|
Jul 26 08:02:07 PM PDT 24 |
Jul 26 08:09:14 PM PDT 24 |
3636572320 ps |
| T737 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1260415568 |
|
|
Jul 26 08:14:52 PM PDT 24 |
Jul 26 08:21:19 PM PDT 24 |
4011402308 ps |
| T812 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1044573015 |
|
|
Jul 26 08:11:16 PM PDT 24 |
Jul 26 08:18:48 PM PDT 24 |
3628771556 ps |
| T1065 |
/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.1323001782 |
|
|
Jul 26 07:45:30 PM PDT 24 |
Jul 26 07:52:21 PM PDT 24 |
3564682192 ps |
| T1066 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1844100023 |
|
|
Jul 26 08:13:30 PM PDT 24 |
Jul 26 08:19:57 PM PDT 24 |
3636745880 ps |
| T1067 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.4290321246 |
|
|
Jul 26 08:02:32 PM PDT 24 |
Jul 26 09:03:59 PM PDT 24 |
15866230158 ps |
| T233 |
/workspace/coverage/default/1.chip_sw_gpio_smoketest.3145480499 |
|
|
Jul 26 07:55:23 PM PDT 24 |
Jul 26 07:59:02 PM PDT 24 |
2313864315 ps |
| T718 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.4006393521 |
|
|
Jul 26 07:47:05 PM PDT 24 |
Jul 26 07:52:22 PM PDT 24 |
3141220344 ps |
| T210 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.532176491 |
|
|
Jul 26 07:57:43 PM PDT 24 |
Jul 26 08:07:04 PM PDT 24 |
4218790260 ps |
| T170 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1219527638 |
|
|
Jul 26 08:10:39 PM PDT 24 |
Jul 26 08:19:11 PM PDT 24 |
3006798988 ps |
| T1068 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.4115386859 |
|
|
Jul 26 08:02:13 PM PDT 24 |
Jul 26 08:16:15 PM PDT 24 |
7826791576 ps |
| T1069 |
/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2162638750 |
|
|
Jul 26 07:48:00 PM PDT 24 |
Jul 26 07:51:57 PM PDT 24 |
2176669248 ps |