| T1070 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1717713614 |
|
|
Jul 26 07:52:19 PM PDT 24 |
Jul 26 08:12:08 PM PDT 24 |
7482236808 ps |
| T1071 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3824754236 |
|
|
Jul 26 07:44:46 PM PDT 24 |
Jul 26 07:48:36 PM PDT 24 |
2678317640 ps |
| T708 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3834451441 |
|
|
Jul 26 07:46:57 PM PDT 24 |
Jul 26 07:48:45 PM PDT 24 |
2698032261 ps |
| T810 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.405288730 |
|
|
Jul 26 08:15:37 PM PDT 24 |
Jul 26 08:24:52 PM PDT 24 |
3681004400 ps |
| T1072 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3178639973 |
|
|
Jul 26 07:52:43 PM PDT 24 |
Jul 26 07:57:56 PM PDT 24 |
3303365299 ps |
| T1073 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.1826547466 |
|
|
Jul 26 07:43:50 PM PDT 24 |
Jul 26 07:48:24 PM PDT 24 |
2915494260 ps |
| T757 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3012702626 |
|
|
Jul 26 08:05:49 PM PDT 24 |
Jul 26 08:13:24 PM PDT 24 |
3799646084 ps |
| T274 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1718980214 |
|
|
Jul 26 07:52:01 PM PDT 24 |
Jul 26 07:58:50 PM PDT 24 |
4773183840 ps |
| T336 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.2965659041 |
|
|
Jul 26 07:46:26 PM PDT 24 |
Jul 26 08:02:02 PM PDT 24 |
4772272536 ps |
| T1074 |
/workspace/coverage/default/0.chip_sw_example_concurrency.3878152861 |
|
|
Jul 26 07:41:54 PM PDT 24 |
Jul 26 07:45:30 PM PDT 24 |
2688767576 ps |
| T1075 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3216144914 |
|
|
Jul 26 07:46:03 PM PDT 24 |
Jul 26 07:54:29 PM PDT 24 |
3617163096 ps |
| T1076 |
/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.3357778555 |
|
|
Jul 26 07:57:21 PM PDT 24 |
Jul 26 08:01:00 PM PDT 24 |
2246094000 ps |
| T47 |
/workspace/coverage/default/1.chip_sw_alert_test.2105827872 |
|
|
Jul 26 07:47:57 PM PDT 24 |
Jul 26 07:52:02 PM PDT 24 |
3003294708 ps |
| T1077 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.972265857 |
|
|
Jul 26 07:45:21 PM PDT 24 |
Jul 26 07:54:19 PM PDT 24 |
3518120392 ps |
| T1078 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3155339265 |
|
|
Jul 26 08:05:17 PM PDT 24 |
Jul 26 08:09:29 PM PDT 24 |
2587420478 ps |
| T160 |
/workspace/coverage/default/1.rom_raw_unlock.1072823580 |
|
|
Jul 26 07:55:19 PM PDT 24 |
Jul 26 07:59:23 PM PDT 24 |
3998340775 ps |
| T793 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.3469526923 |
|
|
Jul 26 08:10:28 PM PDT 24 |
Jul 26 08:23:49 PM PDT 24 |
5040680164 ps |
| T1079 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.3681898800 |
|
|
Jul 26 07:51:38 PM PDT 24 |
Jul 26 07:58:04 PM PDT 24 |
5375913714 ps |
| T775 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.937974515 |
|
|
Jul 26 08:14:35 PM PDT 24 |
Jul 26 08:20:25 PM PDT 24 |
3049477242 ps |
| T719 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.825909534 |
|
|
Jul 26 08:00:24 PM PDT 24 |
Jul 26 08:05:26 PM PDT 24 |
3285799156 ps |
| T1080 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.86702662 |
|
|
Jul 26 07:45:18 PM PDT 24 |
Jul 26 08:26:08 PM PDT 24 |
24815398875 ps |
| T1081 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.4003489582 |
|
|
Jul 26 08:06:41 PM PDT 24 |
Jul 26 08:49:53 PM PDT 24 |
12261117000 ps |
| T829 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.278604320 |
|
|
Jul 26 08:09:33 PM PDT 24 |
Jul 26 08:15:14 PM PDT 24 |
3594704208 ps |
| T832 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2494066540 |
|
|
Jul 26 08:15:34 PM PDT 24 |
Jul 26 08:24:16 PM PDT 24 |
5596838170 ps |
| T1082 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.3592509797 |
|
|
Jul 26 07:53:00 PM PDT 24 |
Jul 26 08:01:44 PM PDT 24 |
4146873120 ps |
| T1083 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.647851017 |
|
|
Jul 26 07:47:09 PM PDT 24 |
Jul 26 08:50:23 PM PDT 24 |
19212111319 ps |
| T1084 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.135283518 |
|
|
Jul 26 08:04:12 PM PDT 24 |
Jul 26 08:27:48 PM PDT 24 |
5172628348 ps |
| T1085 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.1198572239 |
|
|
Jul 26 08:05:15 PM PDT 24 |
Jul 26 08:11:44 PM PDT 24 |
2848826680 ps |
| T145 |
/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.1389337910 |
|
|
Jul 26 07:47:27 PM PDT 24 |
Jul 26 08:30:47 PM PDT 24 |
17618133559 ps |
| T359 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.974922194 |
|
|
Jul 26 08:02:56 PM PDT 24 |
Jul 26 08:14:13 PM PDT 24 |
4966163261 ps |
| T529 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.615985294 |
|
|
Jul 26 07:50:53 PM PDT 24 |
Jul 26 08:17:16 PM PDT 24 |
11976578715 ps |
| T76 |
/workspace/coverage/default/0.chip_jtag_csr_rw.3016107431 |
|
|
Jul 26 07:35:43 PM PDT 24 |
Jul 26 07:39:51 PM PDT 24 |
4034319384 ps |
| T378 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.877474127 |
|
|
Jul 26 07:44:57 PM PDT 24 |
Jul 26 07:56:04 PM PDT 24 |
4105841496 ps |
| T1086 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3981424864 |
|
|
Jul 26 07:59:08 PM PDT 24 |
Jul 26 08:13:02 PM PDT 24 |
9441005368 ps |
| T1087 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.2827405162 |
|
|
Jul 26 07:42:34 PM PDT 24 |
Jul 26 07:46:36 PM PDT 24 |
2667429320 ps |
| T251 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.4038213221 |
|
|
Jul 26 07:46:18 PM PDT 24 |
Jul 26 08:13:30 PM PDT 24 |
19573779138 ps |
| T1088 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2073462278 |
|
|
Jul 26 07:52:31 PM PDT 24 |
Jul 26 09:06:10 PM PDT 24 |
14713822462 ps |
| T450 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2270869248 |
|
|
Jul 26 08:01:36 PM PDT 24 |
Jul 26 08:31:23 PM PDT 24 |
7774456880 ps |
| T1089 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.3762471456 |
|
|
Jul 26 07:52:50 PM PDT 24 |
Jul 26 07:58:00 PM PDT 24 |
3496461088 ps |
| T226 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3729453215 |
|
|
Jul 26 08:00:21 PM PDT 24 |
Jul 26 08:31:42 PM PDT 24 |
7925328096 ps |
| T814 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3774594737 |
|
|
Jul 26 08:07:35 PM PDT 24 |
Jul 26 08:14:34 PM PDT 24 |
4105600200 ps |
| T1090 |
/workspace/coverage/default/4.chip_tap_straps_dev.223532132 |
|
|
Jul 26 08:05:53 PM PDT 24 |
Jul 26 08:28:00 PM PDT 24 |
11284486155 ps |
| T709 |
/workspace/coverage/default/0.rom_volatile_raw_unlock.906840068 |
|
|
Jul 26 07:46:12 PM PDT 24 |
Jul 26 07:47:53 PM PDT 24 |
2812752896 ps |
| T264 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.2869245161 |
|
|
Jul 26 07:42:38 PM PDT 24 |
Jul 26 07:49:39 PM PDT 24 |
4057523862 ps |
| T1091 |
/workspace/coverage/default/1.chip_sw_edn_auto_mode.2916279374 |
|
|
Jul 26 07:51:06 PM PDT 24 |
Jul 26 08:09:25 PM PDT 24 |
4419996634 ps |
| T1092 |
/workspace/coverage/default/2.chip_sw_aes_idle.1742144645 |
|
|
Jul 26 08:01:41 PM PDT 24 |
Jul 26 08:06:19 PM PDT 24 |
3130741512 ps |
| T1093 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.1522915356 |
|
|
Jul 26 08:00:42 PM PDT 24 |
Jul 26 08:05:52 PM PDT 24 |
3375606572 ps |
| T802 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.2586117544 |
|
|
Jul 26 08:09:13 PM PDT 24 |
Jul 26 08:23:04 PM PDT 24 |
6294218074 ps |
| T218 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.4193030312 |
|
|
Jul 26 07:56:39 PM PDT 24 |
Jul 26 11:57:22 PM PDT 24 |
78008748219 ps |
| T713 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.234839507 |
|
|
Jul 26 08:10:52 PM PDT 24 |
Jul 26 08:19:25 PM PDT 24 |
5112876040 ps |
| T1094 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.1792565159 |
|
|
Jul 26 08:03:09 PM PDT 24 |
Jul 26 08:10:19 PM PDT 24 |
3154670048 ps |
| T1095 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2648990438 |
|
|
Jul 26 07:52:08 PM PDT 24 |
Jul 26 07:59:44 PM PDT 24 |
18946331926 ps |
| T100 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.3283494091 |
|
|
Jul 26 07:42:22 PM PDT 24 |
Jul 26 07:49:02 PM PDT 24 |
5169959742 ps |
| T1096 |
/workspace/coverage/default/0.chip_sival_flash_info_access.2533990774 |
|
|
Jul 26 07:41:21 PM PDT 24 |
Jul 26 07:46:44 PM PDT 24 |
3514334488 ps |
| T1097 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.3569617448 |
|
|
Jul 26 08:15:32 PM PDT 24 |
Jul 26 08:28:15 PM PDT 24 |
5298884124 ps |
| T1098 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.868364361 |
|
|
Jul 26 07:44:52 PM PDT 24 |
Jul 26 09:15:08 PM PDT 24 |
45381703782 ps |
| T689 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.175012963 |
|
|
Jul 26 07:49:22 PM PDT 24 |
Jul 26 07:58:36 PM PDT 24 |
2878286400 ps |
| T246 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3375761896 |
|
|
Jul 26 07:44:26 PM PDT 24 |
Jul 26 08:54:06 PM PDT 24 |
13271079000 ps |
| T26 |
/workspace/coverage/default/0.chip_sw_gpio.1577522591 |
|
|
Jul 26 07:43:28 PM PDT 24 |
Jul 26 07:52:44 PM PDT 24 |
4244841404 ps |
| T1099 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.4190306004 |
|
|
Jul 26 08:11:05 PM PDT 24 |
Jul 26 09:11:30 PM PDT 24 |
14588536412 ps |
| T81 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.2786339280 |
|
|
Jul 26 08:00:08 PM PDT 24 |
Jul 26 08:04:43 PM PDT 24 |
3297161152 ps |
| T1100 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.618840264 |
|
|
Jul 26 07:47:47 PM PDT 24 |
Jul 26 08:12:38 PM PDT 24 |
11653942836 ps |
| T1101 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.1440189081 |
|
|
Jul 26 07:41:43 PM PDT 24 |
Jul 26 07:57:46 PM PDT 24 |
5145226796 ps |
| T1102 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.625399091 |
|
|
Jul 26 07:45:25 PM PDT 24 |
Jul 26 07:49:36 PM PDT 24 |
3457226223 ps |
| T1103 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2721467535 |
|
|
Jul 26 07:47:21 PM PDT 24 |
Jul 26 08:58:06 PM PDT 24 |
17936385792 ps |
| T1104 |
/workspace/coverage/default/0.chip_sw_hmac_enc.1354496943 |
|
|
Jul 26 07:42:42 PM PDT 24 |
Jul 26 07:46:46 PM PDT 24 |
3007077094 ps |
| T1105 |
/workspace/coverage/default/0.rom_keymgr_functest.1428002803 |
|
|
Jul 26 07:46:22 PM PDT 24 |
Jul 26 07:55:22 PM PDT 24 |
4637368152 ps |
| T1106 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1740822414 |
|
|
Jul 26 07:58:52 PM PDT 24 |
Jul 26 08:19:18 PM PDT 24 |
17072662920 ps |
| T223 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3034274078 |
|
|
Jul 26 08:00:15 PM PDT 24 |
Jul 26 08:29:56 PM PDT 24 |
23412952472 ps |
| T1107 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3498874829 |
|
|
Jul 26 07:46:13 PM PDT 24 |
Jul 26 08:07:07 PM PDT 24 |
6836002877 ps |
| T1108 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.682923996 |
|
|
Jul 26 08:13:11 PM PDT 24 |
Jul 26 08:18:47 PM PDT 24 |
3245611670 ps |
| T1109 |
/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1788964094 |
|
|
Jul 26 07:47:59 PM PDT 24 |
Jul 26 07:58:33 PM PDT 24 |
5474123170 ps |
| T268 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.1219244044 |
|
|
Jul 26 08:03:08 PM PDT 24 |
Jul 26 08:07:17 PM PDT 24 |
2694198780 ps |
| T345 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.3624621832 |
|
|
Jul 26 07:49:13 PM PDT 24 |
Jul 26 08:16:30 PM PDT 24 |
6504497498 ps |
| T1110 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1551703474 |
|
|
Jul 26 08:04:08 PM PDT 24 |
Jul 26 08:12:31 PM PDT 24 |
6719874388 ps |
| T1111 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1673149273 |
|
|
Jul 26 07:54:08 PM PDT 24 |
Jul 26 08:13:09 PM PDT 24 |
7949387494 ps |
| T1112 |
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1955419574 |
|
|
Jul 26 08:15:25 PM PDT 24 |
Jul 26 08:22:29 PM PDT 24 |
3848319174 ps |
| T791 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.121396226 |
|
|
Jul 26 08:12:15 PM PDT 24 |
Jul 26 08:22:40 PM PDT 24 |
5487970586 ps |
| T795 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.3654564489 |
|
|
Jul 26 08:12:34 PM PDT 24 |
Jul 26 08:22:08 PM PDT 24 |
5833228216 ps |
| T1113 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.4016749499 |
|
|
Jul 26 07:50:29 PM PDT 24 |
Jul 26 08:40:56 PM PDT 24 |
11449456720 ps |
| T1114 |
/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.434092246 |
|
|
Jul 26 07:57:04 PM PDT 24 |
Jul 26 08:05:52 PM PDT 24 |
3294721492 ps |
| T1115 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3201941553 |
|
|
Jul 26 07:46:01 PM PDT 24 |
Jul 26 09:46:51 PM PDT 24 |
29504849076 ps |
| T823 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.3930960840 |
|
|
Jul 26 08:11:25 PM PDT 24 |
Jul 26 08:21:06 PM PDT 24 |
5013042800 ps |
| T1116 |
/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2927225890 |
|
|
Jul 26 07:55:55 PM PDT 24 |
Jul 26 08:06:45 PM PDT 24 |
4638594640 ps |
| T1117 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2473258415 |
|
|
Jul 26 07:49:23 PM PDT 24 |
Jul 26 08:25:04 PM PDT 24 |
9718283396 ps |
| T252 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.325505578 |
|
|
Jul 26 07:46:53 PM PDT 24 |
Jul 26 09:18:30 PM PDT 24 |
46916376088 ps |
| T1118 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.779003557 |
|
|
Jul 26 07:46:38 PM PDT 24 |
Jul 26 07:56:40 PM PDT 24 |
5200016676 ps |
| T1119 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.3964482841 |
|
|
Jul 26 07:44:23 PM PDT 24 |
Jul 26 07:57:25 PM PDT 24 |
6727776264 ps |
| T1120 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1499541281 |
|
|
Jul 26 08:03:45 PM PDT 24 |
Jul 26 08:11:23 PM PDT 24 |
3445646538 ps |
| T269 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.1952859977 |
|
|
Jul 26 07:53:41 PM PDT 24 |
Jul 26 08:01:14 PM PDT 24 |
3998784598 ps |
| T792 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.3519024812 |
|
|
Jul 26 08:09:40 PM PDT 24 |
Jul 26 08:19:50 PM PDT 24 |
4886430488 ps |
| T1121 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.1927154467 |
|
|
Jul 26 07:46:22 PM PDT 24 |
Jul 26 08:05:01 PM PDT 24 |
7989451710 ps |
| T1122 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.4205330814 |
|
|
Jul 26 08:09:34 PM PDT 24 |
Jul 26 09:07:53 PM PDT 24 |
14192973682 ps |
| T784 |
/workspace/coverage/default/1.chip_sw_edn_kat.739998195 |
|
|
Jul 26 07:48:26 PM PDT 24 |
Jul 26 08:00:50 PM PDT 24 |
3236660260 ps |
| T1123 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2734199115 |
|
|
Jul 26 08:07:00 PM PDT 24 |
Jul 26 08:54:09 PM PDT 24 |
12809049664 ps |
| T1124 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3299787678 |
|
|
Jul 26 07:57:50 PM PDT 24 |
Jul 26 08:25:25 PM PDT 24 |
8472792000 ps |
| T1125 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2625040854 |
|
|
Jul 26 08:02:07 PM PDT 24 |
Jul 26 08:23:23 PM PDT 24 |
7629768836 ps |
| T111 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2391030932 |
|
|
Jul 26 07:52:50 PM PDT 24 |
Jul 26 08:02:20 PM PDT 24 |
4391650360 ps |
| T1126 |
/workspace/coverage/default/2.rom_e2e_smoke.1457237217 |
|
|
Jul 26 08:09:18 PM PDT 24 |
Jul 26 09:13:18 PM PDT 24 |
14366863636 ps |
| T82 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2541295045 |
|
|
Jul 26 08:00:45 PM PDT 24 |
Jul 26 08:18:52 PM PDT 24 |
10301183550 ps |
| T1127 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.3482372649 |
|
|
Jul 26 07:51:01 PM PDT 24 |
Jul 26 08:23:02 PM PDT 24 |
9882543600 ps |
| T1128 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.3224023824 |
|
|
Jul 26 07:53:13 PM PDT 24 |
Jul 26 09:51:01 PM PDT 24 |
23343348936 ps |
| T290 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.521398461 |
|
|
Jul 26 07:47:35 PM PDT 24 |
Jul 26 08:03:14 PM PDT 24 |
5577146824 ps |
| T780 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.2391185040 |
|
|
Jul 26 08:13:31 PM PDT 24 |
Jul 26 08:24:21 PM PDT 24 |
6327730400 ps |
| T350 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2334464922 |
|
|
Jul 26 07:48:09 PM PDT 24 |
Jul 26 08:01:57 PM PDT 24 |
5691217514 ps |
| T1129 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.3589665885 |
|
|
Jul 26 07:44:43 PM PDT 24 |
Jul 26 08:04:31 PM PDT 24 |
9452119964 ps |
| T1130 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.789846194 |
|
|
Jul 26 08:08:00 PM PDT 24 |
Jul 26 08:17:21 PM PDT 24 |
3764630642 ps |
| T1131 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.4018034702 |
|
|
Jul 26 08:09:23 PM PDT 24 |
Jul 26 09:12:29 PM PDT 24 |
14967548462 ps |
| T1132 |
/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.3700874784 |
|
|
Jul 26 08:02:21 PM PDT 24 |
Jul 26 08:06:00 PM PDT 24 |
2932540020 ps |
| T747 |
/workspace/coverage/default/2.rom_raw_unlock.4065266940 |
|
|
Jul 26 08:05:33 PM PDT 24 |
Jul 26 08:10:41 PM PDT 24 |
6940121870 ps |
| T247 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.3012390733 |
|
|
Jul 26 07:49:52 PM PDT 24 |
Jul 26 09:03:13 PM PDT 24 |
17420321270 ps |
| T830 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.623948515 |
|
|
Jul 26 08:14:18 PM PDT 24 |
Jul 26 08:19:46 PM PDT 24 |
3807590664 ps |
| T351 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1514016749 |
|
|
Jul 26 07:44:31 PM PDT 24 |
Jul 26 07:59:13 PM PDT 24 |
4894185160 ps |
| T1133 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.1414795503 |
|
|
Jul 26 08:11:03 PM PDT 24 |
Jul 26 08:19:07 PM PDT 24 |
4247369408 ps |
| T250 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3976662043 |
|
|
Jul 26 07:59:20 PM PDT 24 |
Jul 26 09:29:12 PM PDT 24 |
49427287710 ps |
| T1134 |
/workspace/coverage/default/0.chip_sw_uart_smoketest.4211357344 |
|
|
Jul 26 07:48:38 PM PDT 24 |
Jul 26 07:53:23 PM PDT 24 |
3386150780 ps |
| T33 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3556455461 |
|
|
Jul 26 07:57:27 PM PDT 24 |
Jul 26 08:02:26 PM PDT 24 |
3198141440 ps |
| T704 |
/workspace/coverage/default/2.chip_tap_straps_dev.2089308688 |
|
|
Jul 26 08:02:17 PM PDT 24 |
Jul 26 08:20:05 PM PDT 24 |
10303148862 ps |
| T799 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.1625623556 |
|
|
Jul 26 07:55:57 PM PDT 24 |
Jul 26 08:07:29 PM PDT 24 |
6094562120 ps |
| T253 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.775385440 |
|
|
Jul 26 07:59:34 PM PDT 24 |
Jul 26 09:42:23 PM PDT 24 |
48514823880 ps |
| T1135 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.877330982 |
|
|
Jul 26 07:43:12 PM PDT 24 |
Jul 26 08:24:40 PM PDT 24 |
25059390745 ps |
| T1136 |
/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.778504550 |
|
|
Jul 26 08:01:24 PM PDT 24 |
Jul 26 08:15:50 PM PDT 24 |
7633419570 ps |
| T1137 |
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.2677177039 |
|
|
Jul 26 08:08:11 PM PDT 24 |
Jul 26 08:51:53 PM PDT 24 |
9339691370 ps |
| T364 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.2433559036 |
|
|
Jul 26 07:56:27 PM PDT 24 |
Jul 26 08:01:29 PM PDT 24 |
2704124228 ps |
| T840 |
/workspace/coverage/default/29.chip_sw_all_escalation_resets.2948016020 |
|
|
Jul 26 08:10:34 PM PDT 24 |
Jul 26 08:22:30 PM PDT 24 |
5092061340 ps |
| T1138 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1391683933 |
|
|
Jul 26 08:15:03 PM PDT 24 |
Jul 26 08:20:54 PM PDT 24 |
3876906680 ps |
| T1139 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.95406795 |
|
|
Jul 26 07:58:26 PM PDT 24 |
Jul 26 08:11:30 PM PDT 24 |
4945460705 ps |
| T845 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.1160298039 |
|
|
Jul 26 08:10:27 PM PDT 24 |
Jul 26 08:22:05 PM PDT 24 |
5289300120 ps |
| T1140 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.626072972 |
|
|
Jul 26 08:10:32 PM PDT 24 |
Jul 26 08:20:00 PM PDT 24 |
4977599812 ps |
| T837 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.453591539 |
|
|
Jul 26 08:09:39 PM PDT 24 |
Jul 26 08:18:57 PM PDT 24 |
4056761920 ps |
| T710 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.2030226856 |
|
|
Jul 26 07:55:46 PM PDT 24 |
Jul 26 07:57:42 PM PDT 24 |
2181271053 ps |
| T69 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.865441503 |
|
|
Jul 26 07:43:47 PM PDT 24 |
Jul 26 07:48:18 PM PDT 24 |
2753921470 ps |
| T701 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3257465508 |
|
|
Jul 26 07:52:34 PM PDT 24 |
Jul 26 08:02:11 PM PDT 24 |
5447838209 ps |
| T835 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.3253001103 |
|
|
Jul 26 08:14:52 PM PDT 24 |
Jul 26 08:24:06 PM PDT 24 |
4604473400 ps |
| T1141 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.2970865866 |
|
|
Jul 26 07:50:15 PM PDT 24 |
Jul 26 07:57:33 PM PDT 24 |
4532067444 ps |
| T381 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.744606450 |
|
|
Jul 26 07:48:49 PM PDT 24 |
Jul 26 10:58:02 PM PDT 24 |
60038396529 ps |
| T1142 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.1080143041 |
|
|
Jul 26 07:48:17 PM PDT 24 |
Jul 26 07:52:30 PM PDT 24 |
2647047336 ps |
| T1143 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3697118173 |
|
|
Jul 26 07:44:20 PM PDT 24 |
Jul 26 08:01:03 PM PDT 24 |
9101286319 ps |
| T1144 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.769955941 |
|
|
Jul 26 07:52:06 PM PDT 24 |
Jul 26 09:42:05 PM PDT 24 |
23356173366 ps |
| T1145 |
/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.2733809264 |
|
|
Jul 26 08:10:57 PM PDT 24 |
Jul 26 08:56:28 PM PDT 24 |
13211942220 ps |
| T83 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2869877241 |
|
|
Jul 26 07:49:12 PM PDT 24 |
Jul 26 08:22:31 PM PDT 24 |
13075900064 ps |
| T1146 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1998735023 |
|
|
Jul 26 07:47:44 PM PDT 24 |
Jul 26 11:52:04 PM PDT 24 |
78316085125 ps |
| T1147 |
/workspace/coverage/default/2.chip_sw_alert_handler_escalation.4097532120 |
|
|
Jul 26 08:00:02 PM PDT 24 |
Jul 26 08:08:33 PM PDT 24 |
5850231724 ps |
| T1148 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2089898999 |
|
|
Jul 26 07:47:03 PM PDT 24 |
Jul 26 08:44:25 PM PDT 24 |
20978648246 ps |
| T1149 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.3949175144 |
|
|
Jul 26 07:56:53 PM PDT 24 |
Jul 26 08:04:05 PM PDT 24 |
2982697744 ps |
| T175 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.996649784 |
|
|
Jul 26 07:42:17 PM PDT 24 |
Jul 26 07:47:26 PM PDT 24 |
3052490036 ps |
| T1150 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3402297482 |
|
|
Jul 26 07:54:05 PM PDT 24 |
Jul 26 08:07:50 PM PDT 24 |
6476401320 ps |
| T331 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2558601124 |
|
|
Jul 26 07:43:14 PM PDT 24 |
Jul 26 08:08:16 PM PDT 24 |
11933143856 ps |
| T1151 |
/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.639568197 |
|
|
Jul 26 07:51:57 PM PDT 24 |
Jul 26 07:58:08 PM PDT 24 |
4088169028 ps |
| T1152 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1700755972 |
|
|
Jul 26 07:58:32 PM PDT 24 |
Jul 26 08:09:16 PM PDT 24 |
7188575924 ps |
| T1153 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.996171799 |
|
|
Jul 26 07:46:53 PM PDT 24 |
Jul 26 09:01:09 PM PDT 24 |
15255524680 ps |
| T1154 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3191207155 |
|
|
Jul 26 07:45:39 PM PDT 24 |
Jul 26 07:53:08 PM PDT 24 |
7299214660 ps |
| T1155 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2415481314 |
|
|
Jul 26 08:03:33 PM PDT 24 |
Jul 26 08:22:49 PM PDT 24 |
7202112524 ps |
| T1156 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1507794098 |
|
|
Jul 26 07:53:59 PM PDT 24 |
Jul 26 08:01:00 PM PDT 24 |
3956968840 ps |
| T530 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2491196039 |
|
|
Jul 26 07:42:49 PM PDT 24 |
Jul 26 08:02:34 PM PDT 24 |
11993890121 ps |
| T56 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1207724059 |
|
|
Jul 26 07:49:16 PM PDT 24 |
Jul 26 07:58:14 PM PDT 24 |
6449470160 ps |
| T1157 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.2412404009 |
|
|
Jul 26 08:14:08 PM PDT 24 |
Jul 26 08:25:48 PM PDT 24 |
5316974320 ps |
| T54 |
/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.2804633843 |
|
|
Jul 26 07:46:54 PM PDT 24 |
Jul 26 07:51:31 PM PDT 24 |
3708754491 ps |
| T1158 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.3805654808 |
|
|
Jul 26 07:48:36 PM PDT 24 |
Jul 26 07:54:05 PM PDT 24 |
3664297088 ps |
| T1159 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.113629617 |
|
|
Jul 26 08:06:31 PM PDT 24 |
Jul 26 08:47:46 PM PDT 24 |
11363871464 ps |
| T1160 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.3504589987 |
|
|
Jul 26 07:43:20 PM PDT 24 |
Jul 26 09:11:07 PM PDT 24 |
28143655624 ps |
| T826 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.1263403213 |
|
|
Jul 26 08:11:45 PM PDT 24 |
Jul 26 08:23:01 PM PDT 24 |
5725851392 ps |
| T224 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.98016829 |
|
|
Jul 26 08:05:43 PM PDT 24 |
Jul 26 08:16:31 PM PDT 24 |
5370985356 ps |
| T164 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.3061842307 |
|
|
Jul 26 07:50:49 PM PDT 24 |
Jul 26 08:02:20 PM PDT 24 |
4090863428 ps |
| T806 |
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.47086251 |
|
|
Jul 26 08:10:16 PM PDT 24 |
Jul 26 08:17:55 PM PDT 24 |
3975148888 ps |
| T1161 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.985309699 |
|
|
Jul 26 07:50:53 PM PDT 24 |
Jul 26 08:56:14 PM PDT 24 |
15532800460 ps |
| T1162 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.944126812 |
|
|
Jul 26 07:49:08 PM PDT 24 |
Jul 26 07:58:55 PM PDT 24 |
7177480398 ps |
| T817 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.1766612968 |
|
|
Jul 26 08:09:17 PM PDT 24 |
Jul 26 08:21:33 PM PDT 24 |
5763632896 ps |
| T55 |
/workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.3469573537 |
|
|
Jul 26 07:56:47 PM PDT 24 |
Jul 26 08:01:18 PM PDT 24 |
3973805891 ps |
| T1163 |
/workspace/coverage/default/0.chip_sw_otbn_randomness.2411286467 |
|
|
Jul 26 07:43:24 PM PDT 24 |
Jul 26 08:00:38 PM PDT 24 |
6156397516 ps |
| T1164 |
/workspace/coverage/default/4.chip_tap_straps_prod.1303181398 |
|
|
Jul 26 08:05:18 PM PDT 24 |
Jul 26 08:07:27 PM PDT 24 |
3092988703 ps |
| T1165 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.843162888 |
|
|
Jul 26 08:09:09 PM PDT 24 |
Jul 26 08:17:17 PM PDT 24 |
3556621272 ps |
| T1166 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2122829655 |
|
|
Jul 26 07:53:38 PM PDT 24 |
Jul 26 09:09:27 PM PDT 24 |
15118968984 ps |
| T1167 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1682056778 |
|
|
Jul 26 07:43:33 PM PDT 24 |
Jul 26 07:50:52 PM PDT 24 |
5668377592 ps |
| T1168 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2457731773 |
|
|
Jul 26 07:50:51 PM PDT 24 |
Jul 26 08:01:27 PM PDT 24 |
4023020732 ps |
| T1169 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3335405915 |
|
|
Jul 26 07:49:19 PM PDT 24 |
Jul 26 08:53:07 PM PDT 24 |
15079465870 ps |
| T343 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1295227570 |
|
|
Jul 26 07:51:28 PM PDT 24 |
Jul 26 08:27:36 PM PDT 24 |
14749217352 ps |
| T50 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.1681608371 |
|
|
Jul 26 07:41:53 PM PDT 24 |
Jul 26 07:45:24 PM PDT 24 |
3196995208 ps |
| T1170 |
/workspace/coverage/default/1.chip_sw_inject_scramble_seed.4156767798 |
|
|
Jul 26 07:47:20 PM PDT 24 |
Jul 26 11:00:57 PM PDT 24 |
63956260732 ps |
| T1171 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3643532244 |
|
|
Jul 26 08:06:35 PM PDT 24 |
Jul 26 09:00:06 PM PDT 24 |
17091538948 ps |
| T1172 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.1690364353 |
|
|
Jul 26 07:56:31 PM PDT 24 |
Jul 26 11:07:04 PM PDT 24 |
65233031807 ps |
| T339 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.806197287 |
|
|
Jul 26 07:50:24 PM PDT 24 |
Jul 26 08:10:48 PM PDT 24 |
6455539180 ps |
| T1173 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.518653921 |
|
|
Jul 26 07:43:46 PM PDT 24 |
Jul 26 08:26:39 PM PDT 24 |
31673790392 ps |
| T183 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.3096114877 |
|
|
Jul 26 07:51:01 PM PDT 24 |
Jul 26 08:01:53 PM PDT 24 |
4976949120 ps |
| T38 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.838089013 |
|
|
Jul 26 07:45:33 PM PDT 24 |
Jul 26 07:51:59 PM PDT 24 |
3634828648 ps |
| T1174 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.2458305478 |
|
|
Jul 26 08:11:01 PM PDT 24 |
Jul 26 08:21:09 PM PDT 24 |
4306917796 ps |
| T1175 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.2024174302 |
|
|
Jul 26 07:58:41 PM PDT 24 |
Jul 26 08:02:56 PM PDT 24 |
2268434819 ps |
| T1176 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter.583803669 |
|
|
Jul 26 07:52:55 PM PDT 24 |
Jul 26 07:55:50 PM PDT 24 |
2555002538 ps |
| T255 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.3646046817 |
|
|
Jul 26 07:47:53 PM PDT 24 |
Jul 26 09:23:48 PM PDT 24 |
49807316942 ps |
| T211 |
/workspace/coverage/default/0.chip_sw_power_virus.1504437665 |
|
|
Jul 26 07:50:37 PM PDT 24 |
Jul 26 08:15:55 PM PDT 24 |
6232962908 ps |
| T9 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1325672635 |
|
|
Jul 26 07:50:16 PM PDT 24 |
Jul 26 07:53:59 PM PDT 24 |
2789094957 ps |
| T27 |
/workspace/coverage/default/1.chip_sw_gpio.3258408594 |
|
|
Jul 26 07:47:59 PM PDT 24 |
Jul 26 07:56:55 PM PDT 24 |
3954395074 ps |
| T1177 |
/workspace/coverage/default/1.chip_sw_kmac_app_rom.2031321831 |
|
|
Jul 26 07:50:45 PM PDT 24 |
Jul 26 07:56:45 PM PDT 24 |
3094136760 ps |
| T320 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.4098062106 |
|
|
Jul 26 08:09:44 PM PDT 24 |
Jul 26 08:21:27 PM PDT 24 |
4178793368 ps |
| T322 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3875754729 |
|
|
Jul 26 07:54:20 PM PDT 24 |
Jul 26 07:59:16 PM PDT 24 |
3076837274 ps |
| T323 |
/workspace/coverage/default/0.chip_sw_example_rom.2703797450 |
|
|
Jul 26 07:40:52 PM PDT 24 |
Jul 26 07:43:03 PM PDT 24 |
2783419528 ps |
| T248 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3767720260 |
|
|
Jul 26 08:01:13 PM PDT 24 |
Jul 26 09:07:38 PM PDT 24 |
14973210234 ps |
| T324 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.2462075774 |
|
|
Jul 26 07:58:00 PM PDT 24 |
Jul 26 08:12:42 PM PDT 24 |
4639050360 ps |
| T325 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.1096051813 |
|
|
Jul 26 07:47:32 PM PDT 24 |
Jul 26 07:59:28 PM PDT 24 |
5277190832 ps |
| T326 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.839715252 |
|
|
Jul 26 07:42:36 PM PDT 24 |
Jul 26 07:51:45 PM PDT 24 |
3862912310 ps |
| T327 |
/workspace/coverage/default/2.chip_sw_kmac_idle.3619026131 |
|
|
Jul 26 08:02:11 PM PDT 24 |
Jul 26 08:06:40 PM PDT 24 |
3026698108 ps |
| T328 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2137739026 |
|
|
Jul 26 08:12:32 PM PDT 24 |
Jul 26 08:19:24 PM PDT 24 |
4007907520 ps |
| T329 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.4265599905 |
|
|
Jul 26 07:45:54 PM PDT 24 |
Jul 26 07:55:20 PM PDT 24 |
4044723648 ps |
| T294 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3690281132 |
|
|
Jul 26 08:04:15 PM PDT 24 |
Jul 26 08:12:30 PM PDT 24 |
4500599686 ps |
| T1178 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.2578464669 |
|
|
Jul 26 07:43:24 PM PDT 24 |
Jul 26 07:48:28 PM PDT 24 |
3306414130 ps |
| T1179 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3080659684 |
|
|
Jul 26 08:09:33 PM PDT 24 |
Jul 26 08:20:47 PM PDT 24 |
4036002712 ps |
| T1180 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1124699283 |
|
|
Jul 26 07:52:27 PM PDT 24 |
Jul 26 08:31:34 PM PDT 24 |
11322258256 ps |
| T761 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.279249284 |
|
|
Jul 26 07:46:08 PM PDT 24 |
Jul 26 08:22:03 PM PDT 24 |
11015451369 ps |
| T424 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2944281342 |
|
|
Jul 26 08:05:51 PM PDT 24 |
Jul 26 08:17:24 PM PDT 24 |
5391120920 ps |
| T304 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.3179566006 |
|
|
Jul 26 08:14:26 PM PDT 24 |
Jul 26 08:25:10 PM PDT 24 |
5247535336 ps |
| T1181 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.3182698361 |
|
|
Jul 26 08:09:55 PM PDT 24 |
Jul 26 08:19:48 PM PDT 24 |
5168946854 ps |
| T1182 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3488799411 |
|
|
Jul 26 07:43:36 PM PDT 24 |
Jul 26 07:58:59 PM PDT 24 |
6515268372 ps |
| T305 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.3837194015 |
|
|
Jul 26 08:16:14 PM PDT 24 |
Jul 26 08:27:29 PM PDT 24 |
4957542872 ps |
| T379 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2987160746 |
|
|
Jul 26 08:03:25 PM PDT 24 |
Jul 26 08:08:36 PM PDT 24 |
3303204070 ps |
| T1183 |
/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2920322537 |
|
|
Jul 26 08:08:15 PM PDT 24 |
Jul 26 08:40:00 PM PDT 24 |
8373352152 ps |
| T146 |
/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.4182942407 |
|
|
Jul 26 07:54:15 PM PDT 24 |
Jul 26 08:40:24 PM PDT 24 |
17898735747 ps |
| T1184 |
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.1362183040 |
|
|
Jul 26 08:05:50 PM PDT 24 |
Jul 26 08:16:20 PM PDT 24 |
4340638792 ps |
| T794 |
/workspace/coverage/default/97.chip_sw_all_escalation_resets.403455886 |
|
|
Jul 26 08:16:10 PM PDT 24 |
Jul 26 08:25:45 PM PDT 24 |
5792757228 ps |
| T1185 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.2166996869 |
|
|
Jul 26 07:49:58 PM PDT 24 |
Jul 26 07:53:17 PM PDT 24 |
2745595917 ps |
| T212 |
/workspace/coverage/default/2.chip_sw_power_virus.3725076538 |
|
|
Jul 26 08:06:03 PM PDT 24 |
Jul 26 08:22:08 PM PDT 24 |
6151843032 ps |
| T1186 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.3668297910 |
|
|
Jul 26 08:01:52 PM PDT 24 |
Jul 26 08:22:13 PM PDT 24 |
8041847040 ps |
| T1187 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3392549097 |
|
|
Jul 26 08:05:15 PM PDT 24 |
Jul 26 08:13:18 PM PDT 24 |
4156999878 ps |
| T1188 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2713581780 |
|
|
Jul 26 07:58:24 PM PDT 24 |
Jul 26 08:09:27 PM PDT 24 |
4074758038 ps |
| T256 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3365280265 |
|
|
Jul 26 07:58:11 PM PDT 24 |
Jul 26 08:05:32 PM PDT 24 |
4038937896 ps |
| T112 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1896287347 |
|
|
Jul 26 07:52:21 PM PDT 24 |
Jul 26 08:24:29 PM PDT 24 |
22676043976 ps |
| T1189 |
/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.316087917 |
|
|
Jul 26 08:13:01 PM PDT 24 |
Jul 26 08:40:09 PM PDT 24 |
8428192972 ps |
| T1190 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1695293421 |
|
|
Jul 26 07:49:04 PM PDT 24 |
Jul 26 07:59:37 PM PDT 24 |
6986154584 ps |
| T39 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.1062565471 |
|
|
Jul 26 07:43:50 PM PDT 24 |
Jul 26 07:50:11 PM PDT 24 |
3865135496 ps |
| T1191 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.2268956474 |
|
|
Jul 26 07:46:00 PM PDT 24 |
Jul 26 07:50:31 PM PDT 24 |
3111999088 ps |
| T1192 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.496510254 |
|
|
Jul 26 08:04:00 PM PDT 24 |
Jul 26 08:08:38 PM PDT 24 |
3293595383 ps |
| T1193 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.1097498546 |
|
|
Jul 26 07:54:45 PM PDT 24 |
Jul 26 08:01:21 PM PDT 24 |
5799520312 ps |
| T1194 |
/workspace/coverage/default/1.rom_e2e_smoke.3728929138 |
|
|
Jul 26 07:58:36 PM PDT 24 |
Jul 26 09:02:28 PM PDT 24 |
15198858296 ps |
| T1195 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.2865646637 |
|
|
Jul 26 07:43:51 PM PDT 24 |
Jul 26 07:49:49 PM PDT 24 |
3956417888 ps |
| T711 |
/workspace/coverage/default/2.rom_volatile_raw_unlock.3344490683 |
|
|
Jul 26 08:06:25 PM PDT 24 |
Jul 26 08:08:26 PM PDT 24 |
2854067729 ps |
| T712 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2584132708 |
|
|
Jul 26 07:42:05 PM PDT 24 |
Jul 26 07:43:51 PM PDT 24 |
2202820636 ps |
| T1196 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1794856156 |
|
|
Jul 26 07:43:30 PM PDT 24 |
Jul 26 08:46:05 PM PDT 24 |
20878217061 ps |
| T842 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.966010344 |
|
|
Jul 26 08:13:42 PM PDT 24 |
Jul 26 08:20:15 PM PDT 24 |
3218053008 ps |
| T1197 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.234218637 |
|
|
Jul 26 08:12:10 PM PDT 24 |
Jul 26 08:19:57 PM PDT 24 |
3462927402 ps |
| T1198 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.3582939423 |
|
|
Jul 26 07:54:03 PM PDT 24 |
Jul 26 07:57:50 PM PDT 24 |
2693124548 ps |
| T1199 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.1409060693 |
|
|
Jul 26 07:57:15 PM PDT 24 |
Jul 26 08:00:14 PM PDT 24 |
2559809536 ps |
| T746 |
/workspace/coverage/default/2.chip_sw_power_idle_load.1201631988 |
|
|
Jul 26 08:07:07 PM PDT 24 |
Jul 26 08:20:36 PM PDT 24 |
4685526704 ps |
| T437 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1811609930 |
|
|
Jul 26 07:51:23 PM PDT 24 |
Jul 26 07:57:42 PM PDT 24 |
7687754900 ps |
| T813 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.3869257202 |
|
|
Jul 26 08:13:21 PM PDT 24 |
Jul 26 08:25:04 PM PDT 24 |
5249369772 ps |
| T844 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.447618822 |
|
|
Jul 26 08:09:49 PM PDT 24 |
Jul 26 08:15:03 PM PDT 24 |
3531515952 ps |
| T1200 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2113280500 |
|
|
Jul 26 07:59:05 PM PDT 24 |
Jul 26 08:07:08 PM PDT 24 |
4546653664 ps |
| T1201 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1135136731 |
|
|
Jul 26 07:51:43 PM PDT 24 |
Jul 26 09:33:03 PM PDT 24 |
23846264511 ps |
| T330 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1350570848 |
|
|
Jul 26 08:02:59 PM PDT 24 |
Jul 26 08:12:12 PM PDT 24 |
4043066304 ps |
| T1202 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.801543798 |
|
|
Jul 26 07:42:23 PM PDT 24 |
Jul 26 08:05:14 PM PDT 24 |
8177235000 ps |
| T346 |
/workspace/coverage/default/2.chip_sw_entropy_src_csrng.3405873978 |
|
|
Jul 26 08:02:36 PM PDT 24 |
Jul 26 08:31:01 PM PDT 24 |
6821099392 ps |
| T176 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.63344132 |
|
|
Jul 26 07:58:39 PM PDT 24 |
Jul 26 08:02:14 PM PDT 24 |
2503333779 ps |