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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.21 95.60 94.19 95.49 94.90 97.53 99.53


Total test records in report: 2935
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T1203 /workspace/coverage/default/2.rom_e2e_asm_init_rma.993060345 Jul 26 08:08:40 PM PDT 24 Jul 26 09:18:10 PM PDT 24 14493842764 ps
T314 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1930301504 Jul 26 07:45:29 PM PDT 24 Jul 26 07:50:51 PM PDT 24 2726430450 ps
T189 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.3586466138 Jul 26 07:46:33 PM PDT 24 Jul 26 07:49:24 PM PDT 24 3144528666 ps
T1204 /workspace/coverage/default/0.chip_sw_hmac_smoketest.1370917385 Jul 26 07:44:35 PM PDT 24 Jul 26 07:49:53 PM PDT 24 2832996696 ps
T1205 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2700032225 Jul 26 07:46:57 PM PDT 24 Jul 26 07:56:54 PM PDT 24 4110414428 ps
T1206 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2243490851 Jul 26 08:04:29 PM PDT 24 Jul 26 08:15:13 PM PDT 24 4459119898 ps
T690 /workspace/coverage/default/0.chip_sw_edn_boot_mode.4281801738 Jul 26 07:43:23 PM PDT 24 Jul 26 07:54:19 PM PDT 24 2708628546 ps
T1207 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2529279463 Jul 26 08:05:53 PM PDT 24 Jul 26 08:09:55 PM PDT 24 2984089682 ps
T1208 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2313843577 Jul 26 08:06:25 PM PDT 24 Jul 26 08:11:11 PM PDT 24 2643175034 ps
T1209 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2355391233 Jul 26 07:55:18 PM PDT 24 Jul 26 08:16:51 PM PDT 24 7576884724 ps
T1210 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2557675941 Jul 26 07:49:35 PM PDT 24 Jul 26 08:44:09 PM PDT 24 11707456824 ps
T318 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2423813412 Jul 26 08:03:39 PM PDT 24 Jul 26 08:19:26 PM PDT 24 6401093393 ps
T1211 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.3098361158 Jul 26 07:42:36 PM PDT 24 Jul 26 07:51:55 PM PDT 24 4812595520 ps
T1212 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3652191448 Jul 26 07:58:59 PM PDT 24 Jul 26 08:49:46 PM PDT 24 11592960824 ps
T1213 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.178646869 Jul 26 08:07:46 PM PDT 24 Jul 26 08:21:23 PM PDT 24 13823453126 ps
T1214 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.3001849981 Jul 26 08:04:47 PM PDT 24 Jul 26 08:09:02 PM PDT 24 2946778396 ps
T800 /workspace/coverage/default/78.chip_sw_all_escalation_resets.3734170013 Jul 26 08:14:48 PM PDT 24 Jul 26 08:27:49 PM PDT 24 5932153248 ps
T1215 /workspace/coverage/default/2.chip_sw_flash_crash_alert.1622867605 Jul 26 08:06:50 PM PDT 24 Jul 26 08:18:23 PM PDT 24 4579305080 ps
T1216 /workspace/coverage/default/1.chip_sw_aes_entropy.689383318 Jul 26 07:50:05 PM PDT 24 Jul 26 07:54:26 PM PDT 24 2869264344 ps
T1217 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1915080008 Jul 26 07:45:04 PM PDT 24 Jul 26 09:17:48 PM PDT 24 48066290995 ps
T319 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.4005483186 Jul 26 07:50:01 PM PDT 24 Jul 26 08:04:09 PM PDT 24 9003686362 ps
T1218 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1581802362 Jul 26 08:07:07 PM PDT 24 Jul 26 08:25:05 PM PDT 24 8431485984 ps
T816 /workspace/coverage/default/58.chip_sw_all_escalation_resets.861035757 Jul 26 08:13:13 PM PDT 24 Jul 26 08:23:04 PM PDT 24 5362452008 ps
T1219 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1477976802 Jul 26 07:58:49 PM PDT 24 Jul 26 09:07:12 PM PDT 24 15053726244 ps
T1220 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3058715733 Jul 26 07:53:51 PM PDT 24 Jul 26 08:02:58 PM PDT 24 5516484984 ps
T1221 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3276324203 Jul 26 08:04:45 PM PDT 24 Jul 26 08:28:03 PM PDT 24 8975166308 ps
T295 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2084602975 Jul 26 07:48:26 PM PDT 24 Jul 26 07:58:16 PM PDT 24 5479960500 ps
T1222 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.180994754 Jul 26 07:59:12 PM PDT 24 Jul 26 08:17:36 PM PDT 24 11973563354 ps
T753 /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.1146491325 Jul 26 07:47:50 PM PDT 24 Jul 26 08:20:59 PM PDT 24 11088224949 ps
T1223 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1268481001 Jul 26 08:08:31 PM PDT 24 Jul 26 08:14:53 PM PDT 24 3876256666 ps
T801 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.4074303090 Jul 26 08:11:40 PM PDT 24 Jul 26 08:19:21 PM PDT 24 3572502728 ps
T1224 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.1651023207 Jul 26 07:55:23 PM PDT 24 Jul 26 08:01:09 PM PDT 24 2886886611 ps
T805 /workspace/coverage/default/42.chip_sw_all_escalation_resets.3714445989 Jul 26 08:10:13 PM PDT 24 Jul 26 08:19:51 PM PDT 24 5693088476 ps
T692 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3969038454 Jul 26 08:06:34 PM PDT 24 Jul 27 02:16:16 AM PDT 24 164102696282 ps
T1225 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3290152134 Jul 26 08:13:25 PM PDT 24 Jul 26 08:20:01 PM PDT 24 4390146600 ps
T352 /workspace/coverage/default/2.chip_plic_all_irqs_20.2159743540 Jul 26 08:01:46 PM PDT 24 Jul 26 08:16:24 PM PDT 24 4560545260 ps
T1226 /workspace/coverage/default/66.chip_sw_all_escalation_resets.1757445631 Jul 26 08:12:53 PM PDT 24 Jul 26 08:21:21 PM PDT 24 5716026020 ps
T1227 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2572853830 Jul 26 08:03:43 PM PDT 24 Jul 26 08:09:37 PM PDT 24 3187200485 ps
T1228 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3281802976 Jul 26 07:42:02 PM PDT 24 Jul 26 08:56:40 PM PDT 24 19214086015 ps
T88 /workspace/coverage/default/56.chip_sw_all_escalation_resets.2774091774 Jul 26 08:12:36 PM PDT 24 Jul 26 08:21:52 PM PDT 24 4321355528 ps
T774 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1847155661 Jul 26 08:09:08 PM PDT 24 Jul 26 08:15:00 PM PDT 24 4230287650 ps
T1229 /workspace/coverage/default/1.chip_sw_flash_crash_alert.1097805507 Jul 26 07:53:33 PM PDT 24 Jul 26 08:05:43 PM PDT 24 4968744740 ps
T1230 /workspace/coverage/default/1.chip_tap_straps_prod.3304896534 Jul 26 07:51:46 PM PDT 24 Jul 26 08:02:29 PM PDT 24 7408976982 ps
T48 /workspace/coverage/default/0.chip_sw_alert_test.968708853 Jul 26 07:43:42 PM PDT 24 Jul 26 07:50:18 PM PDT 24 3360850708 ps
T1231 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2008677290 Jul 26 07:41:51 PM PDT 24 Jul 26 07:59:59 PM PDT 24 5615213501 ps
T768 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2313002090 Jul 26 08:09:28 PM PDT 24 Jul 26 08:17:37 PM PDT 24 4512100130 ps
T807 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1975538174 Jul 26 08:12:44 PM PDT 24 Jul 26 08:21:16 PM PDT 24 3657381880 ps
T1232 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3997103742 Jul 26 07:50:20 PM PDT 24 Jul 26 08:07:26 PM PDT 24 7598205904 ps
T372 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3603786972 Jul 26 07:56:10 PM PDT 24 Jul 26 08:08:29 PM PDT 24 4966250314 ps
T61 /workspace/coverage/default/2.chip_tap_straps_rma.2272310090 Jul 26 08:04:05 PM PDT 24 Jul 26 08:06:44 PM PDT 24 2458076867 ps
T1233 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.1255217691 Jul 26 07:47:22 PM PDT 24 Jul 26 08:08:40 PM PDT 24 6804663230 ps
T296 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.623392367 Jul 26 08:00:30 PM PDT 24 Jul 26 08:09:55 PM PDT 24 4248136022 ps
T833 /workspace/coverage/default/79.chip_sw_all_escalation_resets.2057112946 Jul 26 08:14:43 PM PDT 24 Jul 26 08:26:51 PM PDT 24 4451394236 ps
T1234 /workspace/coverage/default/2.rom_e2e_asm_init_dev.3772287216 Jul 26 08:09:05 PM PDT 24 Jul 26 09:23:00 PM PDT 24 15617222536 ps
T1235 /workspace/coverage/default/2.chip_sw_edn_sw_mode.3387379462 Jul 26 08:01:52 PM PDT 24 Jul 26 08:21:15 PM PDT 24 6597181560 ps
T1236 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1843786616 Jul 26 07:44:49 PM PDT 24 Jul 26 08:13:01 PM PDT 24 16055226548 ps
T1237 /workspace/coverage/default/0.chip_sw_aes_masking_off.2499295978 Jul 26 07:45:18 PM PDT 24 Jul 26 07:50:36 PM PDT 24 3163064734 ps
T1238 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.1934340937 Jul 26 07:50:06 PM PDT 24 Jul 26 08:28:17 PM PDT 24 11006918121 ps
T1239 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3278003470 Jul 26 07:59:21 PM PDT 24 Jul 26 08:12:01 PM PDT 24 4813805050 ps
T1240 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1382240431 Jul 26 07:59:41 PM PDT 24 Jul 26 08:16:27 PM PDT 24 6963438284 ps
T1241 /workspace/coverage/default/0.rom_e2e_asm_init_rma.1464011751 Jul 26 07:51:27 PM PDT 24 Jul 26 08:49:03 PM PDT 24 14458460160 ps
T828 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2372330692 Jul 26 08:09:28 PM PDT 24 Jul 26 08:17:23 PM PDT 24 4270510356 ps
T1242 /workspace/coverage/default/92.chip_sw_all_escalation_resets.182245491 Jul 26 08:15:12 PM PDT 24 Jul 26 08:24:12 PM PDT 24 5258106396 ps
T525 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2294851681 Jul 26 07:42:52 PM PDT 24 Jul 26 07:57:47 PM PDT 24 5170745968 ps
T215 /workspace/coverage/default/1.chip_jtag_mem_access.3557267057 Jul 26 07:44:24 PM PDT 24 Jul 26 08:12:53 PM PDT 24 14063050924 ps
T1243 /workspace/coverage/default/1.chip_sw_power_idle_load.3817994976 Jul 26 07:52:59 PM PDT 24 Jul 26 08:02:57 PM PDT 24 3936235902 ps
T1244 /workspace/coverage/default/2.chip_tap_straps_prod.3249736190 Jul 26 08:02:32 PM PDT 24 Jul 26 08:15:14 PM PDT 24 6650705616 ps
T344 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2506978977 Jul 26 08:00:37 PM PDT 24 Jul 26 08:34:18 PM PDT 24 11803958790 ps
T803 /workspace/coverage/default/17.chip_sw_all_escalation_resets.7129415 Jul 26 08:08:52 PM PDT 24 Jul 26 08:18:31 PM PDT 24 4448530290 ps
T141 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1359697516 Jul 26 08:03:11 PM PDT 24 Jul 26 08:10:07 PM PDT 24 5481136600 ps
T1245 /workspace/coverage/default/2.chip_sw_aes_masking_off.1839409803 Jul 26 08:01:18 PM PDT 24 Jul 26 08:06:13 PM PDT 24 3091046131 ps
T1246 /workspace/coverage/default/2.chip_sw_otbn_randomness.347393025 Jul 26 08:01:01 PM PDT 24 Jul 26 08:18:05 PM PDT 24 5783897730 ps
T1247 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.245310363 Jul 26 07:47:15 PM PDT 24 Jul 26 07:54:06 PM PDT 24 5860316760 ps
T526 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1485155898 Jul 26 07:47:26 PM PDT 24 Jul 26 08:01:01 PM PDT 24 4735731728 ps
T1248 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.393651410 Jul 26 07:45:47 PM PDT 24 Jul 26 07:50:56 PM PDT 24 3220283784 ps
T1249 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1124471325 Jul 26 07:49:12 PM PDT 24 Jul 26 07:56:14 PM PDT 24 5101620016 ps
T1250 /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3307665960 Jul 26 07:56:45 PM PDT 24 Jul 26 10:54:09 PM PDT 24 57916465932 ps
T754 /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.3058220558 Jul 26 07:54:19 PM PDT 24 Jul 26 08:46:10 PM PDT 24 24057279153 ps
T1251 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.864963563 Jul 26 07:44:50 PM PDT 24 Jul 26 07:52:10 PM PDT 24 5833727302 ps
T1252 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3960876998 Jul 26 07:48:49 PM PDT 24 Jul 26 07:55:57 PM PDT 24 8026167644 ps
T1253 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.378450320 Jul 26 07:52:32 PM PDT 24 Jul 26 09:31:39 PM PDT 24 23843843634 ps
T1254 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.1110261955 Jul 26 07:51:06 PM PDT 24 Jul 26 07:57:58 PM PDT 24 4089559804 ps
T1255 /workspace/coverage/default/94.chip_sw_all_escalation_resets.584619036 Jul 26 08:15:26 PM PDT 24 Jul 26 08:26:25 PM PDT 24 4556456036 ps
T1256 /workspace/coverage/default/1.rom_e2e_asm_init_rma.3090440305 Jul 26 07:58:57 PM PDT 24 Jul 26 09:03:15 PM PDT 24 14638841815 ps
T1257 /workspace/coverage/default/1.chip_sw_otbn_randomness.3797381660 Jul 26 07:47:41 PM PDT 24 Jul 26 08:02:26 PM PDT 24 6155397068 ps
T1258 /workspace/coverage/default/0.chip_sw_example_flash.1415252628 Jul 26 07:41:32 PM PDT 24 Jul 26 07:45:51 PM PDT 24 3131606888 ps
T1259 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.3206853467 Jul 26 08:00:21 PM PDT 24 Jul 26 09:00:08 PM PDT 24 14857762336 ps
T1260 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.983053686 Jul 26 08:06:49 PM PDT 24 Jul 26 08:19:17 PM PDT 24 4627202844 ps
T1261 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1001637467 Jul 26 07:49:48 PM PDT 24 Jul 26 08:00:34 PM PDT 24 3685014600 ps
T1262 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3112274732 Jul 26 07:52:43 PM PDT 24 Jul 26 07:57:40 PM PDT 24 3802674729 ps
T28 /workspace/coverage/default/2.chip_sw_gpio.977616253 Jul 26 07:57:12 PM PDT 24 Jul 26 08:05:06 PM PDT 24 3961753944 ps
T720 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2829847220 Jul 26 07:45:29 PM PDT 24 Jul 26 07:49:50 PM PDT 24 3206464840 ps
T804 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1226432746 Jul 26 08:11:11 PM PDT 24 Jul 26 08:17:50 PM PDT 24 4290970032 ps
T1263 /workspace/coverage/default/69.chip_sw_all_escalation_resets.690376619 Jul 26 08:13:42 PM PDT 24 Jul 26 08:24:39 PM PDT 24 5435184616 ps
T1264 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.615441221 Jul 26 07:49:23 PM PDT 24 Jul 26 08:58:47 PM PDT 24 14531819816 ps
T1265 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.4014124896 Jul 26 08:02:50 PM PDT 24 Jul 26 08:10:02 PM PDT 24 3595405443 ps
T1266 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.1952944701 Jul 26 07:46:33 PM PDT 24 Jul 26 07:51:31 PM PDT 24 3183123364 ps
T1267 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.599383087 Jul 26 08:04:20 PM PDT 24 Jul 26 08:11:28 PM PDT 24 3656825930 ps
T1268 /workspace/coverage/default/1.chip_sw_flash_init.3538562400 Jul 26 07:45:00 PM PDT 24 Jul 26 08:25:35 PM PDT 24 22469665968 ps
T1269 /workspace/coverage/default/3.chip_tap_straps_rma.4200742895 Jul 26 08:08:30 PM PDT 24 Jul 26 08:16:08 PM PDT 24 4755648123 ps
T1270 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.2502528019 Jul 26 07:58:52 PM PDT 24 Jul 26 09:35:32 PM PDT 24 48026039200 ps
T315 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2653051683 Jul 26 07:51:43 PM PDT 24 Jul 26 07:57:16 PM PDT 24 2637424704 ps
T1271 /workspace/coverage/default/0.chip_sw_hmac_multistream.2353640025 Jul 26 07:45:12 PM PDT 24 Jul 26 08:20:09 PM PDT 24 7755911128 ps
T1272 /workspace/coverage/default/0.chip_sw_csrng_smoketest.850002327 Jul 26 07:46:11 PM PDT 24 Jul 26 07:51:28 PM PDT 24 3061623168 ps
T827 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1654124121 Jul 26 08:15:25 PM PDT 24 Jul 26 08:21:17 PM PDT 24 4085548204 ps
T1273 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.929113564 Jul 26 07:51:09 PM PDT 24 Jul 26 08:01:08 PM PDT 24 4685892640 ps
T1274 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3367844785 Jul 26 08:00:57 PM PDT 24 Jul 26 11:41:50 PM PDT 24 255969032920 ps
T278 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.780548035 Jul 26 07:58:18 PM PDT 24 Jul 26 08:11:26 PM PDT 24 5814671600 ps
T1275 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2645122159 Jul 26 08:13:13 PM PDT 24 Jul 26 08:20:10 PM PDT 24 3904256240 ps
T1276 /workspace/coverage/default/1.chip_sw_kmac_entropy.3031833035 Jul 26 07:49:37 PM PDT 24 Jul 26 07:55:22 PM PDT 24 2762262294 ps
T1277 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1462513747 Jul 26 08:00:31 PM PDT 24 Jul 26 08:07:54 PM PDT 24 4198562988 ps
T1278 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1927040215 Jul 26 07:43:22 PM PDT 24 Jul 26 08:00:22 PM PDT 24 6189495768 ps
T721 /workspace/coverage/default/0.chip_sw_plic_sw_irq.3474677625 Jul 26 07:43:38 PM PDT 24 Jul 26 07:47:04 PM PDT 24 2532305060 ps
T1279 /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2898130120 Jul 26 07:42:40 PM PDT 24 Jul 26 07:51:45 PM PDT 24 4242893974 ps
T144 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3669188701 Jul 26 07:43:09 PM PDT 24 Jul 26 07:54:11 PM PDT 24 5609088768 ps
T1280 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1237233938 Jul 26 07:45:49 PM PDT 24 Jul 26 08:01:24 PM PDT 24 7834510056 ps
T1281 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3126501232 Jul 26 08:01:34 PM PDT 24 Jul 26 08:05:17 PM PDT 24 2482558436 ps
T1282 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.2950991613 Jul 26 08:00:52 PM PDT 24 Jul 26 09:16:16 PM PDT 24 15441558072 ps
T1283 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3863144043 Jul 26 08:01:22 PM PDT 24 Jul 26 08:20:38 PM PDT 24 9684623602 ps
T769 /workspace/coverage/default/72.chip_sw_all_escalation_resets.4240093941 Jul 26 08:14:44 PM PDT 24 Jul 26 08:28:46 PM PDT 24 5657410710 ps
T1284 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.776143481 Jul 26 07:49:59 PM PDT 24 Jul 26 08:52:31 PM PDT 24 14853698165 ps
T1285 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.1256982762 Jul 26 07:50:40 PM PDT 24 Jul 26 08:57:03 PM PDT 24 15102205371 ps
T1286 /workspace/coverage/default/2.rom_e2e_self_hash.1567300987 Jul 26 08:09:57 PM PDT 24 Jul 26 10:01:53 PM PDT 24 26381930440 ps
T1287 /workspace/coverage/default/1.chip_sw_uart_smoketest.3872107306 Jul 26 07:55:33 PM PDT 24 Jul 26 08:00:09 PM PDT 24 3378546216 ps
T1288 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2761221300 Jul 26 08:08:21 PM PDT 24 Jul 26 08:20:17 PM PDT 24 4275829456 ps
T1289 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.73711990 Jul 26 07:42:54 PM PDT 24 Jul 26 07:55:38 PM PDT 24 9845467290 ps
T213 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.3262208504 Jul 26 07:42:58 PM PDT 24 Jul 26 07:52:05 PM PDT 24 5070785139 ps
T1290 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.832730502 Jul 26 08:02:28 PM PDT 24 Jul 26 08:33:17 PM PDT 24 9559204600 ps
T1291 /workspace/coverage/default/1.chip_sw_kmac_smoketest.3369401698 Jul 26 07:57:07 PM PDT 24 Jul 26 08:02:19 PM PDT 24 2970934162 ps
T1292 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.171545626 Jul 26 08:08:53 PM PDT 24 Jul 26 08:18:16 PM PDT 24 5505711219 ps
T214 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.406091127 Jul 26 07:57:29 PM PDT 24 Jul 26 08:07:50 PM PDT 24 5887592420 ps
T702 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1707521352 Jul 26 07:43:27 PM PDT 24 Jul 26 07:53:11 PM PDT 24 4545184024 ps
T1293 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.901790544 Jul 26 07:59:13 PM PDT 24 Jul 26 08:05:11 PM PDT 24 3906955482 ps
T776 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3855983418 Jul 26 08:09:43 PM PDT 24 Jul 26 08:18:44 PM PDT 24 4220548616 ps
T1294 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1084194960 Jul 26 07:46:20 PM PDT 24 Jul 26 07:55:47 PM PDT 24 4637570160 ps
T1295 /workspace/coverage/default/0.rom_e2e_asm_init_prod.1061946888 Jul 26 07:51:41 PM PDT 24 Jul 26 09:15:40 PM PDT 24 15467447812 ps
T1296 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1136970866 Jul 26 07:43:41 PM PDT 24 Jul 26 07:55:03 PM PDT 24 7610776000 ps
T1297 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.370662016 Jul 26 07:45:26 PM PDT 24 Jul 26 08:15:58 PM PDT 24 8640066960 ps
T796 /workspace/coverage/default/43.chip_sw_all_escalation_resets.862958567 Jul 26 08:11:34 PM PDT 24 Jul 26 08:22:11 PM PDT 24 4753946242 ps
T1298 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1008218836 Jul 26 08:01:58 PM PDT 24 Jul 26 08:06:13 PM PDT 24 3100824878 ps
T1299 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2634344167 Jul 26 08:13:29 PM PDT 24 Jul 26 08:21:32 PM PDT 24 3387205044 ps
T1300 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.198767435 Jul 26 08:06:04 PM PDT 24 Jul 26 08:09:37 PM PDT 24 2457476268 ps
T1301 /workspace/coverage/default/2.chip_sw_kmac_entropy.2761105998 Jul 26 07:59:56 PM PDT 24 Jul 26 08:05:53 PM PDT 24 2780753356 ps
T1302 /workspace/coverage/default/1.chip_sw_hmac_smoketest.728019664 Jul 26 07:55:47 PM PDT 24 Jul 26 08:00:33 PM PDT 24 2886958680 ps
T1303 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.558051647 Jul 26 07:54:29 PM PDT 24 Jul 26 08:15:42 PM PDT 24 6153292970 ps
T1304 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.785403445 Jul 26 07:48:26 PM PDT 24 Jul 26 08:03:47 PM PDT 24 5464802620 ps
T1305 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1540071823 Jul 26 07:49:49 PM PDT 24 Jul 26 07:55:54 PM PDT 24 3305079914 ps
T1306 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1579889373 Jul 26 07:46:55 PM PDT 24 Jul 26 07:55:43 PM PDT 24 4760899334 ps
T1307 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3782129370 Jul 26 07:44:58 PM PDT 24 Jul 26 09:20:21 PM PDT 24 46325501880 ps
T1308 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.2922734889 Jul 26 07:45:38 PM PDT 24 Jul 26 07:52:52 PM PDT 24 9309766841 ps
T819 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1912447140 Jul 26 08:13:11 PM PDT 24 Jul 26 08:20:49 PM PDT 24 3967959592 ps
T1309 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.154187723 Jul 26 07:41:14 PM PDT 24 Jul 26 08:02:58 PM PDT 24 8958116320 ps
T1310 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.77046840 Jul 26 07:48:35 PM PDT 24 Jul 26 08:00:04 PM PDT 24 4484139380 ps
T244 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.885588332 Jul 26 07:49:59 PM PDT 24 Jul 26 08:30:25 PM PDT 24 10593901272 ps
T1311 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1799879505 Jul 26 08:00:38 PM PDT 24 Jul 26 08:09:30 PM PDT 24 3885137176 ps
T89 /workspace/coverage/default/83.chip_sw_all_escalation_resets.1158526618 Jul 26 08:14:36 PM PDT 24 Jul 26 08:25:58 PM PDT 24 5583451324 ps
T745 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2384808340 Jul 26 08:03:38 PM PDT 24 Jul 26 08:34:05 PM PDT 24 24068306630 ps
T1312 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3915370483 Jul 26 07:50:21 PM PDT 24 Jul 26 08:06:45 PM PDT 24 10922434381 ps
T1313 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2811780880 Jul 26 07:49:24 PM PDT 24 Jul 26 08:00:57 PM PDT 24 4125329018 ps
T1314 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1134572130 Jul 26 07:48:50 PM PDT 24 Jul 26 07:53:12 PM PDT 24 2375990300 ps
T62 /workspace/coverage/default/2.chip_tap_straps_testunlock0.1528311133 Jul 26 08:02:53 PM PDT 24 Jul 26 08:12:03 PM PDT 24 5937237782 ps
T1315 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1369047312 Jul 26 08:03:25 PM PDT 24 Jul 26 08:08:46 PM PDT 24 3185448870 ps
T1316 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3253754347 Jul 26 07:56:40 PM PDT 24 Jul 26 08:00:24 PM PDT 24 3169758432 ps
T1317 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3266884562 Jul 26 07:42:17 PM PDT 24 Jul 26 08:01:44 PM PDT 24 6551604700 ps
T658 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2981802515 Jul 26 08:01:40 PM PDT 24 Jul 26 08:11:27 PM PDT 24 4491227664 ps
T1318 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3263787627 Jul 26 07:53:51 PM PDT 24 Jul 26 08:04:46 PM PDT 24 5366230614 ps
T1319 /workspace/coverage/default/14.chip_sw_all_escalation_resets.2962766760 Jul 26 08:08:22 PM PDT 24 Jul 26 08:19:42 PM PDT 24 4936379080 ps
T1320 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1297460134 Jul 26 07:53:43 PM PDT 24 Jul 26 08:03:25 PM PDT 24 4788310816 ps
T1321 /workspace/coverage/default/0.chip_sw_coremark.907057266 Jul 26 07:44:03 PM PDT 24 Jul 27 12:17:08 AM PDT 24 71814045324 ps
T1322 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3576377603 Jul 26 07:42:33 PM PDT 24 Jul 26 07:50:57 PM PDT 24 7321487200 ps
T306 /workspace/coverage/default/59.chip_sw_all_escalation_resets.888967665 Jul 26 08:12:45 PM PDT 24 Jul 26 08:22:45 PM PDT 24 6011143608 ps
T1323 /workspace/coverage/default/1.chip_sw_example_flash.3923258743 Jul 26 07:52:00 PM PDT 24 Jul 26 07:55:27 PM PDT 24 2625858024 ps
T1324 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3155781427 Jul 26 08:15:49 PM PDT 24 Jul 26 08:21:30 PM PDT 24 4003202650 ps
T90 /workspace/coverage/default/10.chip_sw_all_escalation_resets.591356327 Jul 26 08:13:02 PM PDT 24 Jul 26 08:28:57 PM PDT 24 5127027310 ps
T1325 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3342888983 Jul 26 07:48:30 PM PDT 24 Jul 26 08:35:09 PM PDT 24 11175912332 ps
T1326 /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.4088204385 Jul 26 08:08:29 PM PDT 24 Jul 26 09:17:22 PM PDT 24 20870579744 ps
T1327 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.850983647 Jul 26 08:02:39 PM PDT 24 Jul 26 08:07:08 PM PDT 24 3074026342 ps
T340 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.4000984562 Jul 26 07:44:19 PM PDT 24 Jul 26 07:56:54 PM PDT 24 5142631442 ps
T1328 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1247642898 Jul 26 07:46:56 PM PDT 24 Jul 26 08:14:51 PM PDT 24 24685369250 ps
T190 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1820589144 Jul 26 07:46:12 PM PDT 24 Jul 26 07:51:03 PM PDT 24 4093131317 ps
T216 /workspace/coverage/default/2.chip_jtag_mem_access.2578800764 Jul 26 07:56:09 PM PDT 24 Jul 26 08:24:41 PM PDT 24 13832709007 ps
T1329 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.809119692 Jul 26 07:49:17 PM PDT 24 Jul 26 07:53:56 PM PDT 24 2914905613 ps
T1330 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1319252977 Jul 26 07:46:17 PM PDT 24 Jul 26 08:03:01 PM PDT 24 11671616820 ps
T831 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.141511251 Jul 26 08:15:07 PM PDT 24 Jul 26 08:22:07 PM PDT 24 3194210384 ps
T1331 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1824158134 Jul 26 07:42:08 PM PDT 24 Jul 26 07:47:52 PM PDT 24 3544817872 ps
T1332 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.3693305787 Jul 26 08:08:59 PM PDT 24 Jul 26 08:24:36 PM PDT 24 10120017967 ps
T70 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.2122785604 Jul 26 07:44:00 PM PDT 24 Jul 26 10:01:20 PM PDT 24 32198508600 ps
T1333 /workspace/coverage/default/1.chip_sw_csrng_smoketest.4255865004 Jul 26 07:55:26 PM PDT 24 Jul 26 08:00:55 PM PDT 24 3644658456 ps
T356 /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2596632514 Jul 26 08:05:09 PM PDT 24 Jul 26 08:13:04 PM PDT 24 4204508160 ps
T703 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1141775287 Jul 26 08:04:32 PM PDT 24 Jul 26 08:13:16 PM PDT 24 5167610899 ps
T380 /workspace/coverage/default/2.chip_sw_hmac_enc.3171701598 Jul 26 08:02:07 PM PDT 24 Jul 26 08:06:24 PM PDT 24 2928394196 ps
T1334 /workspace/coverage/default/0.chip_sw_aes_smoketest.246175815 Jul 26 07:44:50 PM PDT 24 Jul 26 07:48:08 PM PDT 24 2744726088 ps
T53 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.3029447083 Jul 26 07:57:26 PM PDT 24 Jul 26 08:03:49 PM PDT 24 3733652520 ps
T808 /workspace/coverage/default/1.chip_sw_all_escalation_resets.1833793436 Jul 26 07:52:56 PM PDT 24 Jul 26 08:03:14 PM PDT 24 5650408728 ps
T342 /workspace/coverage/default/0.chip_plic_all_irqs_0.853826638 Jul 26 07:47:22 PM PDT 24 Jul 26 08:12:19 PM PDT 24 6214897400 ps
T1335 /workspace/coverage/default/1.chip_sw_aes_idle.4209616656 Jul 26 07:47:45 PM PDT 24 Jul 26 07:51:56 PM PDT 24 3007896860 ps
T1336 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2171769358 Jul 26 08:10:35 PM PDT 24 Jul 26 08:17:04 PM PDT 24 4864211382 ps
T824 /workspace/coverage/default/61.chip_sw_all_escalation_resets.311781974 Jul 26 08:13:17 PM PDT 24 Jul 26 08:25:09 PM PDT 24 5634525208 ps
T1337 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3765468085 Jul 26 08:00:48 PM PDT 24 Jul 26 09:04:16 PM PDT 24 10865619472 ps
T1338 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1528928189 Jul 26 07:42:55 PM PDT 24 Jul 26 07:53:50 PM PDT 24 3373715224 ps
T825 /workspace/coverage/default/27.chip_sw_all_escalation_resets.3424102028 Jul 26 08:10:43 PM PDT 24 Jul 26 08:24:03 PM PDT 24 6216697880 ps
T1339 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.3990294277 Jul 26 07:49:55 PM PDT 24 Jul 26 07:59:00 PM PDT 24 5655532204 ps
T1340 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1778982515 Jul 26 07:59:01 PM PDT 24 Jul 26 08:03:40 PM PDT 24 3444982990 ps
T1341 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.1703626200 Jul 26 07:56:54 PM PDT 24 Jul 26 09:08:05 PM PDT 24 14377610117 ps
T1342 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3713318936 Jul 26 07:59:23 PM PDT 24 Jul 26 08:07:05 PM PDT 24 6383936988 ps
T1343 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.677636597 Jul 26 07:59:14 PM PDT 24 Jul 26 08:06:28 PM PDT 24 7149668587 ps
T1344 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1263734670 Jul 26 08:00:37 PM PDT 24 Jul 26 08:42:45 PM PDT 24 32264173516 ps
T1345 /workspace/coverage/default/2.chip_sw_edn_kat.2457714011 Jul 26 07:59:51 PM PDT 24 Jul 26 08:12:34 PM PDT 24 3778894120 ps
T841 /workspace/coverage/default/57.chip_sw_all_escalation_resets.2346502522 Jul 26 08:12:36 PM PDT 24 Jul 26 08:23:43 PM PDT 24 6722177380 ps
T1346 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2470546834 Jul 26 07:55:56 PM PDT 24 Jul 26 08:04:05 PM PDT 24 5264429260 ps
T1347 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.620413131 Jul 26 08:09:34 PM PDT 24 Jul 26 08:17:28 PM PDT 24 3167682080 ps
T1348 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3048807934 Jul 26 08:08:53 PM PDT 24 Jul 26 08:15:35 PM PDT 24 4146411796 ps
T34 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.4107705395 Jul 26 07:44:20 PM PDT 24 Jul 26 07:47:38 PM PDT 24 2641492784 ps
T1349 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1241776600 Jul 26 08:10:52 PM PDT 24 Jul 26 08:18:36 PM PDT 24 3231223576 ps
T1350 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1307275801 Jul 26 07:51:12 PM PDT 24 Jul 26 07:57:59 PM PDT 24 2889299404 ps
T40 /workspace/coverage/default/2.chip_sw_spi_device_tpm.3194757209 Jul 26 08:00:19 PM PDT 24 Jul 26 08:07:26 PM PDT 24 3879728074 ps
T1351 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.609042862 Jul 26 07:45:56 PM PDT 24 Jul 26 07:49:53 PM PDT 24 3092064600 ps
T1352 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.864513809 Jul 26 07:46:07 PM PDT 24 Jul 26 07:54:47 PM PDT 24 7096092404 ps
T1353 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1088215808 Jul 26 07:46:02 PM PDT 24 Jul 26 07:52:01 PM PDT 24 3374418022 ps
T1354 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3505749750 Jul 26 07:58:16 PM PDT 24 Jul 26 09:02:38 PM PDT 24 14712428200 ps
T797 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.673298581 Jul 26 08:16:31 PM PDT 24 Jul 26 08:22:45 PM PDT 24 4319526968 ps
T1355 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1722746899 Jul 26 07:58:19 PM PDT 24 Jul 26 08:21:42 PM PDT 24 9065173768 ps
T1356 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3829630498 Jul 26 07:46:12 PM PDT 24 Jul 26 07:50:19 PM PDT 24 2890276968 ps
T1357 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2932837452 Jul 26 08:07:33 PM PDT 24 Jul 26 09:11:26 PM PDT 24 14497177443 ps
T1358 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3667582482 Jul 26 07:45:22 PM PDT 24 Jul 26 08:05:59 PM PDT 24 5428140160 ps
T1359 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.4214050530 Jul 26 08:00:05 PM PDT 24 Jul 26 08:33:00 PM PDT 24 8511685497 ps
T1360 /workspace/coverage/default/2.chip_sw_kmac_app_rom.2117377127 Jul 26 08:02:37 PM PDT 24 Jul 26 08:08:44 PM PDT 24 3056048904 ps
T834 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.346994919 Jul 26 08:09:56 PM PDT 24 Jul 26 08:16:42 PM PDT 24 3902560892 ps
T527 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1301935682 Jul 26 08:00:25 PM PDT 24 Jul 26 08:12:51 PM PDT 24 5003720520 ps
T1361 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.2410944743 Jul 26 07:50:14 PM PDT 24 Jul 26 07:55:02 PM PDT 24 2618716752 ps
T818 /workspace/coverage/default/51.chip_sw_all_escalation_resets.2984087039 Jul 26 08:12:29 PM PDT 24 Jul 26 08:22:25 PM PDT 24 4786282352 ps
T1362 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3200455832 Jul 26 08:06:04 PM PDT 24 Jul 26 08:11:18 PM PDT 24 3479456950 ps
T1363 /workspace/coverage/default/2.chip_sw_kmac_smoketest.1294102670 Jul 26 08:06:05 PM PDT 24 Jul 26 08:10:42 PM PDT 24 3440641044 ps
T1364 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.251693137 Jul 26 08:05:00 PM PDT 24 Jul 26 08:17:53 PM PDT 24 4197930260 ps
T767 /workspace/coverage/default/8.chip_sw_all_escalation_resets.2844154321 Jul 26 08:06:41 PM PDT 24 Jul 26 08:18:25 PM PDT 24 6299050872 ps
T10 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2276907550 Jul 26 07:42:29 PM PDT 24 Jul 26 07:47:17 PM PDT 24 2364407012 ps
T1365 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3451286737 Jul 26 07:44:16 PM PDT 24 Jul 26 07:47:24 PM PDT 24 3607753242 ps
T1366 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3408793251 Jul 26 07:43:02 PM PDT 24 Jul 26 07:51:12 PM PDT 24 6829942440 ps
T1367 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1274842955 Jul 26 08:06:26 PM PDT 24 Jul 26 08:23:20 PM PDT 24 12504272174 ps
T225 /workspace/coverage/default/1.chip_jtag_csr_rw.1630992459 Jul 26 07:44:10 PM PDT 24 Jul 26 08:24:01 PM PDT 24 20262730381 ps
T843 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3636112713 Jul 26 08:09:09 PM PDT 24 Jul 26 08:16:02 PM PDT 24 3271487576 ps
T1368 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2146456804 Jul 26 08:01:25 PM PDT 24 Jul 26 08:07:23 PM PDT 24 3051836397 ps
T811 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3577316461 Jul 26 08:14:44 PM PDT 24 Jul 26 08:20:16 PM PDT 24 3525238090 ps
T347 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.3559274270 Jul 26 07:49:33 PM PDT 24 Jul 26 08:21:10 PM PDT 24 8013505672 ps
T1369 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.213524890 Jul 26 07:45:11 PM PDT 24 Jul 26 07:50:54 PM PDT 24 2890847590 ps
T307 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3144721256 Jul 26 08:12:10 PM PDT 24 Jul 26 08:18:49 PM PDT 24 4193347500 ps
T1370 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.1798109747 Jul 26 07:46:17 PM PDT 24 Jul 26 07:50:49 PM PDT 24 2817769610 ps
T798 /workspace/coverage/default/44.chip_sw_all_escalation_resets.3964737951 Jul 26 08:11:15 PM PDT 24 Jul 26 08:22:40 PM PDT 24 5258691112 ps
T770 /workspace/coverage/default/3.chip_sw_all_escalation_resets.1518915219 Jul 26 08:04:34 PM PDT 24 Jul 26 08:13:41 PM PDT 24 5859388184 ps
T439 /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.1251591609 Jul 26 07:48:10 PM PDT 24 Jul 26 08:27:12 PM PDT 24 24820631330 ps
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