Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo	75.00	50.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	201562311	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	21670	21670	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	201562311	0	0
T1	2224510	83642	0	0
T2	1249230	44322	0	0
T3	1715830	39820	0	0
T4	2899820	106718	0	0
T28	2522730	71926	0	0
T42	9419830	450671	0	0
T70	2205630	76143	0	0
T94	1937740	92968	0	0
T95	833980	28879	0	0
T96	4710580	156661	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2224510	2223930	0	0
T2	1249230	1248720	0	0
T3	1715830	1714020	0	0
T4	2899820	2898760	0	0
T28	2522730	2521100	0	0
T42	9419830	9419210	0	0
T70	2205630	2204500	0	0
T94	1937740	1937190	0	0
T95	833980	833400	0	0
T96	4710580	4708940	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2224510	2223930	0	0
T2	1249230	1248720	0	0
T3	1715830	1714020	0	0
T4	2899820	2898760	0	0
T28	2522730	2521100	0	0
T42	9419830	9419210	0	0
T70	2205630	2204500	0	0
T94	1937740	1937190	0	0
T95	833980	833400	0	0
T96	4710580	4708940	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2224510	2223930	0	0
T2	1249230	1248720	0	0
T3	1715830	1714020	0	0
T4	2899820	2898760	0	0
T28	2522730	2521100	0	0
T42	9419830	9419210	0	0
T70	2205630	2204500	0	0
T94	1937740	1937190	0	0
T95	833980	833400	0	0
T96	4710580	4708940	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	21670	21670	0	0
T1	10	10	0	0
T2	10	10	0	0
T3	10	10	0	0
T4	10	10	0	0
T28	10	10	0	0
T42	10	10	0	0
T70	10	10	0	0
T94	10	10	0	0
T95	10	10	0	0
T96	10	10	0	0