Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	544206842	64187637	0	0
DepthKnown_A	544206842	544099372	0	0
RvalidKnown_A	544206842	544099372	0	0
WreadyKnown_A	544206842	544099372	0	0
gen_passthru_fifo.paramCheckPass	1021	1021	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	64187637	0	0
T1	222451	22659	0	0
T2	124923	15411	0	0
T3	171583	13976	0	0
T4	289982	37682	0	0
T28	252273	26762	0	0
T42	941983	114212	0	0
T70	220563	29089	0	0
T94	193774	28376	0	0
T95	83398	9884	0	0
T96	471058	58266	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	544099372	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	544099372	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	544099372	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T28	1	1	0	0
T42	1	1	0	0
T70	1	1	0	0
T94	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	544206842	49703707	0	0
DepthKnown_A	544206842	544099372	0	0
RvalidKnown_A	544206842	544099372	0	0
WreadyKnown_A	544206842	544099372	0	0
gen_passthru_fifo.paramCheckPass	1021	1021	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	49703707	0	0
T1	222451	18733	0	0
T2	124923	11277	0	0
T3	171583	10215	0	0
T4	289982	28236	0	0
T28	252273	19080	0	0
T42	941983	95392	0	0
T70	220563	19413	0	0
T94	193774	24012	0	0
T95	83398	7437	0	0
T96	471058	46982	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	544099372	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	544099372	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	544099372	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T28	1	1	0	0
T42	1	1	0	0
T70	1	1	0	0
T94	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	544206842	47128171	0	0
DepthKnown_A	544206842	544099372	0	0
RvalidKnown_A	544206842	544099372	0	0
WreadyKnown_A	544206842	544099372	0	0
gen_passthru_fifo.paramCheckPass	1021	1021	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	47128171	0	0
T1	222451	21122	0	0
T2	124923	8906	0	0
T3	171583	7909	0	0
T4	289982	20288	0	0
T28	252273	13138	0	0
T42	941983	154447	0	0
T70	220563	13716	0	0
T94	193774	20344	0	0
T95	83398	5847	0	0
T96	471058	25928	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	544099372	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	544099372	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	544099372	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T28	1	1	0	0
T42	1	1	0	0
T70	1	1	0	0
T94	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	544206842	40134928	0	0
DepthKnown_A	544206842	544099372	0	0
RvalidKnown_A	544206842	544099372	0	0
WreadyKnown_A	544206842	544099372	0	0
gen_passthru_fifo.paramCheckPass	1021	1021	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	40134928	0	0
T1	222451	20916	0	0
T2	124923	8540	0	0
T3	171583	7612	0	0
T4	289982	19908	0	0
T28	252273	12674	0	0
T42	941983	86484	0	0
T70	220563	13321	0	0
T94	193774	20136	0	0
T95	83398	5655	0	0
T96	471058	25173	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	544099372	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	544099372	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544206842	544099372	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T28	1	1	0	0
T42	1	1	0	0
T70	1	1	0	0
T94	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	637713567	101074	0	0
DepthKnown_A	637713567	637589459	0	0
RvalidKnown_A	637713567	637589459	0	0
WreadyKnown_A	637713567	637589459	0	0
gen_passthru_fifo.paramCheckPass	2931	2931	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637713567	101074	0	0
T1	222451	53	0	0
T2	124923	47	0	0
T3	171583	27	0	0
T4	289982	151	0	0
T28	252273	68	0	0
T42	941983	34	0	0
T70	220563	151	0	0
T94	193774	25	0	0
T95	83398	14	0	0
T96	471058	78	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637713567	637589459	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637713567	637589459	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637713567	637589459	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2931	2931	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T28	1	1	0	0
T42	1	1	0	0
T70	1	1	0	0
T94	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	637713567	102860	0	0
DepthKnown_A	637713567	637589459	0	0
RvalidKnown_A	637713567	637589459	0	0
WreadyKnown_A	637713567	637589459	0	0
gen_passthru_fifo.paramCheckPass	2931	2931	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637713567	102860	0	0
T1	222451	53	0	0
T2	124923	47	0	0
T3	171583	27	0	0
T4	289982	151	0	0
T28	252273	68	0	0
T42	941983	34	0	0
T70	220563	151	0	0
T94	193774	25	0	0
T95	83398	14	0	0
T96	471058	78	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637713567	637589459	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637713567	637589459	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637713567	637589459	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2931	2931	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T28	1	1	0	0
T42	1	1	0	0
T70	1	1	0	0
T94	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	637713567	52472	0	0
DepthKnown_A	637713567	637589459	0	0
RvalidKnown_A	637713567	637589459	0	0
WreadyKnown_A	637713567	637589459	0	0
gen_passthru_fifo.paramCheckPass	2931	2931	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637713567	52472	0	0
T1	222451	52	0	0
T2	124923	44	0	0
T3	171583	25	0	0
T4	289982	95	0	0
T28	252273	63	0	0
T42	941983	5	0	0
T70	220563	95	0	0
T94	193774	12	0	0
T95	83398	13	0	0
T96	471058	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637713567	637589459	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637713567	637589459	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637713567	637589459	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2931	2931	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T28	1	1	0	0
T42	1	1	0	0
T70	1	1	0	0
T94	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	637713567	52472	0	0
DepthKnown_A	637713567	637589459	0	0
RvalidKnown_A	637713567	637589459	0	0
WreadyKnown_A	637713567	637589459	0	0
gen_passthru_fifo.paramCheckPass	2931	2931	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637713567	52472	0	0
T1	222451	52	0	0
T2	124923	44	0	0
T3	171583	25	0	0
T4	289982	95	0	0
T28	252273	63	0	0
T42	941983	5	0	0
T70	220563	95	0	0
T94	193774	12	0	0
T95	83398	13	0	0
T96	471058	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637713567	637589459	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637713567	637589459	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637713567	637589459	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2931	2931	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T28	1	1	0	0
T42	1	1	0	0
T70	1	1	0	0
T94	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	637713567	48602	0	0
DepthKnown_A	637713567	637589459	0	0
RvalidKnown_A	637713567	637589459	0	0
WreadyKnown_A	637713567	637589459	0	0
gen_passthru_fifo.paramCheckPass	2931	2931	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637713567	48602	0	0
T1	222451	1	0	0
T2	124923	3	0	0
T3	171583	2	0	0
T4	289982	56	0	0
T28	252273	5	0	0
T42	941983	29	0	0
T70	220563	56	0	0
T94	193774	13	0	0
T95	83398	1	0	0
T96	471058	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637713567	637589459	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637713567	637589459	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637713567	637589459	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2931	2931	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T28	1	1	0	0
T42	1	1	0	0
T70	1	1	0	0
T94	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	637713567	50388	0	0
DepthKnown_A	637713567	637589459	0	0
RvalidKnown_A	637713567	637589459	0	0
WreadyKnown_A	637713567	637589459	0	0
gen_passthru_fifo.paramCheckPass	2931	2931	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637713567	50388	0	0
T1	222451	1	0	0
T2	124923	3	0	0
T3	171583	2	0	0
T4	289982	56	0	0
T28	252273	5	0	0
T42	941983	29	0	0
T70	220563	56	0	0
T94	193774	13	0	0
T95	83398	1	0	0
T96	471058	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637713567	637589459	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637713567	637589459	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637713567	637589459	0	0
T1	222451	222393	0	0
T2	124923	124872	0	0
T3	171583	171402	0	0
T4	289982	289876	0	0
T28	252273	252110	0	0
T42	941983	941921	0	0
T70	220563	220450	0	0
T94	193774	193719	0	0
T95	83398	83340	0	0
T96	471058	470894	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2931	2931	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T28	1	1	0	0
T42	1	1	0	0
T70	1	1	0	0
T94	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0