| T777 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.2200309757 |
|
|
Jul 28 08:39:05 PM PDT 24 |
Jul 28 08:46:17 PM PDT 24 |
4882446460 ps |
| T838 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3938653569 |
|
|
Jul 28 08:33:16 PM PDT 24 |
Jul 28 08:40:54 PM PDT 24 |
3411586392 ps |
| T971 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.17779586 |
|
|
Jul 28 08:10:32 PM PDT 24 |
Jul 28 08:43:45 PM PDT 24 |
8542709784 ps |
| T24 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.3863375825 |
|
|
Jul 28 08:06:31 PM PDT 24 |
Jul 28 09:59:12 PM PDT 24 |
32300200184 ps |
| T761 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.2808113608 |
|
|
Jul 28 08:12:55 PM PDT 24 |
Jul 28 08:21:01 PM PDT 24 |
4531386184 ps |
| T972 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.398264411 |
|
|
Jul 28 08:13:59 PM PDT 24 |
Jul 28 08:18:41 PM PDT 24 |
3557884068 ps |
| T158 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.1601806803 |
|
|
Jul 28 08:21:28 PM PDT 24 |
Jul 28 09:57:43 PM PDT 24 |
44283657752 ps |
| T708 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.81673798 |
|
|
Jul 28 08:10:49 PM PDT 24 |
Jul 28 08:20:26 PM PDT 24 |
3384744600 ps |
| T973 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1843043776 |
|
|
Jul 28 08:22:32 PM PDT 24 |
Jul 28 08:39:50 PM PDT 24 |
11463138962 ps |
| T396 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3859835192 |
|
|
Jul 28 08:12:27 PM PDT 24 |
Jul 28 09:43:20 PM PDT 24 |
24575143626 ps |
| T163 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2084617837 |
|
|
Jul 28 08:08:50 PM PDT 24 |
Jul 28 08:18:54 PM PDT 24 |
5720076380 ps |
| T974 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.4144631714 |
|
|
Jul 28 08:19:04 PM PDT 24 |
Jul 28 08:32:44 PM PDT 24 |
3548810650 ps |
| T254 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4030787687 |
|
|
Jul 28 08:16:15 PM PDT 24 |
Jul 28 08:22:51 PM PDT 24 |
4277410412 ps |
| T821 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.2898836696 |
|
|
Jul 28 08:39:42 PM PDT 24 |
Jul 28 08:51:21 PM PDT 24 |
5424841000 ps |
| T110 |
/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.1022194134 |
|
|
Jul 28 08:15:26 PM PDT 24 |
Jul 28 09:19:21 PM PDT 24 |
25155848476 ps |
| T248 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.2255439550 |
|
|
Jul 28 08:18:54 PM PDT 24 |
Jul 28 08:27:40 PM PDT 24 |
4116316776 ps |
| T975 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1543416215 |
|
|
Jul 28 08:16:48 PM PDT 24 |
Jul 28 08:31:02 PM PDT 24 |
3819605988 ps |
| T976 |
/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.963599362 |
|
|
Jul 28 08:10:38 PM PDT 24 |
Jul 28 08:21:39 PM PDT 24 |
3814981586 ps |
| T135 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.352567040 |
|
|
Jul 28 08:05:24 PM PDT 24 |
Jul 28 08:14:17 PM PDT 24 |
3876849808 ps |
| T243 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.350771857 |
|
|
Jul 28 08:39:10 PM PDT 24 |
Jul 28 08:44:30 PM PDT 24 |
4164715350 ps |
| T256 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.3554834454 |
|
|
Jul 28 08:38:06 PM PDT 24 |
Jul 28 08:50:25 PM PDT 24 |
5977606550 ps |
| T296 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.2233570833 |
|
|
Jul 28 08:09:15 PM PDT 24 |
Jul 28 08:13:39 PM PDT 24 |
3105108392 ps |
| T11 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.81112181 |
|
|
Jul 28 08:05:46 PM PDT 24 |
Jul 28 08:16:03 PM PDT 24 |
6006019698 ps |
| T297 |
/workspace/coverage/default/0.chip_sw_aes_idle.831383964 |
|
|
Jul 28 08:07:15 PM PDT 24 |
Jul 28 08:11:35 PM PDT 24 |
3144513940 ps |
| T62 |
/workspace/coverage/default/3.chip_tap_straps_rma.1236356607 |
|
|
Jul 28 08:30:25 PM PDT 24 |
Jul 28 08:40:32 PM PDT 24 |
6600052842 ps |
| T298 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1966052943 |
|
|
Jul 28 08:13:09 PM PDT 24 |
Jul 28 08:23:40 PM PDT 24 |
7272380656 ps |
| T299 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3661180478 |
|
|
Jul 28 08:15:03 PM PDT 24 |
Jul 28 08:37:06 PM PDT 24 |
7883529266 ps |
| T300 |
/workspace/coverage/default/1.chip_sw_hmac_oneshot.2858862986 |
|
|
Jul 28 08:16:24 PM PDT 24 |
Jul 28 08:22:26 PM PDT 24 |
3416273536 ps |
| T301 |
/workspace/coverage/default/1.chip_sw_edn_auto_mode.1541400426 |
|
|
Jul 28 08:14:31 PM PDT 24 |
Jul 28 08:45:43 PM PDT 24 |
6859480376 ps |
| T249 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.2464844247 |
|
|
Jul 28 08:16:29 PM PDT 24 |
Jul 28 08:21:16 PM PDT 24 |
2544230700 ps |
| T977 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.1666169315 |
|
|
Jul 28 08:22:13 PM PDT 24 |
Jul 28 08:39:33 PM PDT 24 |
12681505555 ps |
| T978 |
/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1223040252 |
|
|
Jul 28 08:33:35 PM PDT 24 |
Jul 28 09:12:40 PM PDT 24 |
11596999456 ps |
| T168 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3931770968 |
|
|
Jul 28 08:27:45 PM PDT 24 |
Jul 28 08:32:34 PM PDT 24 |
3101790200 ps |
| T979 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.1905115289 |
|
|
Jul 28 08:06:00 PM PDT 24 |
Jul 28 08:10:28 PM PDT 24 |
3281542958 ps |
| T980 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.836616256 |
|
|
Jul 28 08:07:42 PM PDT 24 |
Jul 28 08:19:10 PM PDT 24 |
4342016600 ps |
| T194 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.3796967200 |
|
|
Jul 28 08:06:55 PM PDT 24 |
Jul 28 11:32:06 PM PDT 24 |
66185517893 ps |
| T89 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.434297923 |
|
|
Jul 28 08:36:19 PM PDT 24 |
Jul 28 08:45:14 PM PDT 24 |
5400066960 ps |
| T981 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.1120281771 |
|
|
Jul 28 08:16:44 PM PDT 24 |
Jul 28 08:21:41 PM PDT 24 |
3250339160 ps |
| T148 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3670337008 |
|
|
Jul 28 08:16:33 PM PDT 24 |
Jul 28 08:18:14 PM PDT 24 |
1680704789 ps |
| T982 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2627751079 |
|
|
Jul 28 08:08:08 PM PDT 24 |
Jul 28 08:17:02 PM PDT 24 |
9585777004 ps |
| T983 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2709299451 |
|
|
Jul 28 08:25:35 PM PDT 24 |
Jul 28 08:41:15 PM PDT 24 |
10881181148 ps |
| T984 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.3716811480 |
|
|
Jul 28 08:11:51 PM PDT 24 |
Jul 28 08:21:11 PM PDT 24 |
3759335216 ps |
| T985 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx.3367234735 |
|
|
Jul 28 08:30:07 PM PDT 24 |
Jul 28 08:39:52 PM PDT 24 |
4665662840 ps |
| T986 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2042814870 |
|
|
Jul 28 08:11:56 PM PDT 24 |
Jul 28 08:21:06 PM PDT 24 |
4990513724 ps |
| T987 |
/workspace/coverage/default/0.chip_sw_hmac_smoketest.4064060634 |
|
|
Jul 28 08:10:33 PM PDT 24 |
Jul 28 08:16:34 PM PDT 24 |
3201125100 ps |
| T988 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1431857382 |
|
|
Jul 28 08:15:16 PM PDT 24 |
Jul 28 09:08:04 PM PDT 24 |
11595773620 ps |
| T302 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2235725576 |
|
|
Jul 28 08:17:29 PM PDT 24 |
Jul 28 08:20:52 PM PDT 24 |
2022058769 ps |
| T989 |
/workspace/coverage/default/1.chip_sw_edn_kat.3657967918 |
|
|
Jul 28 08:16:35 PM PDT 24 |
Jul 28 08:27:46 PM PDT 24 |
3328323472 ps |
| T12 |
/workspace/coverage/default/1.chip_sw_power_virus.2115351456 |
|
|
Jul 28 08:24:52 PM PDT 24 |
Jul 28 08:50:50 PM PDT 24 |
5619925648 ps |
| T990 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.315198081 |
|
|
Jul 28 08:28:47 PM PDT 24 |
Jul 28 08:34:13 PM PDT 24 |
2931429960 ps |
| T991 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.2527193440 |
|
|
Jul 28 08:25:33 PM PDT 24 |
Jul 28 08:34:07 PM PDT 24 |
5296609296 ps |
| T164 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.609225895 |
|
|
Jul 28 08:10:52 PM PDT 24 |
Jul 28 08:18:57 PM PDT 24 |
4648629110 ps |
| T992 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.1623200866 |
|
|
Jul 28 08:20:28 PM PDT 24 |
Jul 28 08:25:39 PM PDT 24 |
3074849778 ps |
| T67 |
/workspace/coverage/default/2.chip_tap_straps_prod.3056593981 |
|
|
Jul 28 08:27:26 PM PDT 24 |
Jul 28 08:50:38 PM PDT 24 |
13291158117 ps |
| T993 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2168262015 |
|
|
Jul 28 08:07:40 PM PDT 24 |
Jul 28 08:19:22 PM PDT 24 |
4321079138 ps |
| T994 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1781775044 |
|
|
Jul 28 08:07:13 PM PDT 24 |
Jul 28 09:06:01 PM PDT 24 |
18540990880 ps |
| T995 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.135196716 |
|
|
Jul 28 08:08:14 PM PDT 24 |
Jul 28 08:14:40 PM PDT 24 |
5049427352 ps |
| T345 |
/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.4015019680 |
|
|
Jul 28 08:17:13 PM PDT 24 |
Jul 28 08:25:29 PM PDT 24 |
3797762404 ps |
| T996 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.756158799 |
|
|
Jul 28 08:06:15 PM PDT 24 |
Jul 28 08:10:14 PM PDT 24 |
2756126112 ps |
| T774 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.388770280 |
|
|
Jul 28 08:40:56 PM PDT 24 |
Jul 28 08:47:36 PM PDT 24 |
4079442790 ps |
| T364 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2927789822 |
|
|
Jul 28 08:39:07 PM PDT 24 |
Jul 28 08:47:46 PM PDT 24 |
5851236292 ps |
| T22 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1765668762 |
|
|
Jul 28 08:07:34 PM PDT 24 |
Jul 28 09:10:05 PM PDT 24 |
20340477925 ps |
| T997 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2360943478 |
|
|
Jul 28 08:31:23 PM PDT 24 |
Jul 28 09:12:14 PM PDT 24 |
13081059320 ps |
| T239 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.764238805 |
|
|
Jul 28 08:34:35 PM PDT 24 |
Jul 28 08:44:08 PM PDT 24 |
5167830496 ps |
| T718 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.398667035 |
|
|
Jul 28 08:14:28 PM PDT 24 |
Jul 28 08:16:25 PM PDT 24 |
2754733281 ps |
| T998 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter.2961523755 |
|
|
Jul 28 08:14:50 PM PDT 24 |
Jul 28 08:18:14 PM PDT 24 |
2966391594 ps |
| T999 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.599156770 |
|
|
Jul 28 08:22:25 PM PDT 24 |
Jul 28 08:43:02 PM PDT 24 |
6277210842 ps |
| T775 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.3419677418 |
|
|
Jul 28 08:39:32 PM PDT 24 |
Jul 28 08:50:26 PM PDT 24 |
5969024620 ps |
| T1000 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.974544113 |
|
|
Jul 28 08:08:05 PM PDT 24 |
Jul 28 08:13:00 PM PDT 24 |
3030245800 ps |
| T788 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2829871655 |
|
|
Jul 28 08:07:10 PM PDT 24 |
Jul 28 08:13:31 PM PDT 24 |
3245945718 ps |
| T222 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3294606679 |
|
|
Jul 28 08:26:09 PM PDT 24 |
Jul 28 09:36:21 PM PDT 24 |
17139355912 ps |
| T200 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.149921508 |
|
|
Jul 28 08:24:43 PM PDT 24 |
Jul 28 09:10:01 PM PDT 24 |
20372565542 ps |
| T752 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.2959662102 |
|
|
Jul 28 08:07:24 PM PDT 24 |
Jul 28 08:21:54 PM PDT 24 |
5631252440 ps |
| T13 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.3386202198 |
|
|
Jul 28 08:21:01 PM PDT 24 |
Jul 28 08:33:22 PM PDT 24 |
6925917872 ps |
| T367 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.3797920209 |
|
|
Jul 28 08:06:55 PM PDT 24 |
Jul 28 08:12:03 PM PDT 24 |
3020332696 ps |
| T770 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1123044993 |
|
|
Jul 28 08:35:48 PM PDT 24 |
Jul 28 08:42:15 PM PDT 24 |
3755828076 ps |
| T257 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2291936885 |
|
|
Jul 28 08:33:57 PM PDT 24 |
Jul 28 08:40:52 PM PDT 24 |
3211168776 ps |
| T232 |
/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3140840779 |
|
|
Jul 28 08:31:19 PM PDT 24 |
Jul 28 09:03:21 PM PDT 24 |
23035566853 ps |
| T1001 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.604499046 |
|
|
Jul 28 08:13:48 PM PDT 24 |
Jul 28 09:11:28 PM PDT 24 |
14806634640 ps |
| T361 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.850559705 |
|
|
Jul 28 08:12:16 PM PDT 24 |
Jul 28 08:20:42 PM PDT 24 |
19004446048 ps |
| T165 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2000914755 |
|
|
Jul 28 08:18:48 PM PDT 24 |
Jul 28 08:29:50 PM PDT 24 |
5901473170 ps |
| T1002 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.350517239 |
|
|
Jul 28 08:20:46 PM PDT 24 |
Jul 28 08:24:36 PM PDT 24 |
2562018607 ps |
| T808 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.796521736 |
|
|
Jul 28 08:34:18 PM PDT 24 |
Jul 28 08:41:43 PM PDT 24 |
3098038506 ps |
| T782 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.929161607 |
|
|
Jul 28 08:37:21 PM PDT 24 |
Jul 28 08:50:13 PM PDT 24 |
6400819958 ps |
| T1003 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.975867969 |
|
|
Jul 28 08:23:54 PM PDT 24 |
Jul 28 09:48:50 PM PDT 24 |
18549508672 ps |
| T1004 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.245175303 |
|
|
Jul 28 08:15:48 PM PDT 24 |
Jul 28 08:28:51 PM PDT 24 |
6784654600 ps |
| T336 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3896962873 |
|
|
Jul 28 08:06:14 PM PDT 24 |
Jul 28 08:17:56 PM PDT 24 |
4459082550 ps |
| T733 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.547829571 |
|
|
Jul 28 08:15:23 PM PDT 24 |
Jul 28 08:20:54 PM PDT 24 |
3775553590 ps |
| T776 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.2073345039 |
|
|
Jul 28 08:34:25 PM PDT 24 |
Jul 28 08:43:52 PM PDT 24 |
5067424012 ps |
| T347 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2665716811 |
|
|
Jul 28 08:05:55 PM PDT 24 |
Jul 28 08:17:54 PM PDT 24 |
4570866159 ps |
| T746 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.3340140840 |
|
|
Jul 28 08:39:14 PM PDT 24 |
Jul 28 08:47:26 PM PDT 24 |
6120556384 ps |
| T415 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.1510889047 |
|
|
Jul 28 08:26:46 PM PDT 24 |
Jul 28 08:36:10 PM PDT 24 |
5727781144 ps |
| T443 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.804430361 |
|
|
Jul 28 08:14:51 PM PDT 24 |
Jul 28 09:24:46 PM PDT 24 |
14490183372 ps |
| T362 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2601142736 |
|
|
Jul 28 08:26:20 PM PDT 24 |
Jul 28 08:31:28 PM PDT 24 |
3358790743 ps |
| T444 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx.3361762074 |
|
|
Jul 28 08:12:09 PM PDT 24 |
Jul 28 08:23:28 PM PDT 24 |
4706085528 ps |
| T32 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1660212891 |
|
|
Jul 28 08:21:39 PM PDT 24 |
Jul 28 08:27:20 PM PDT 24 |
3043558528 ps |
| T445 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.675907187 |
|
|
Jul 28 08:26:40 PM PDT 24 |
Jul 28 09:16:11 PM PDT 24 |
15511353580 ps |
| T26 |
/workspace/coverage/default/0.chip_sw_gpio.1730527307 |
|
|
Jul 28 08:08:29 PM PDT 24 |
Jul 28 08:17:35 PM PDT 24 |
4794437886 ps |
| T446 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.1047693887 |
|
|
Jul 28 08:37:30 PM PDT 24 |
Jul 28 08:47:10 PM PDT 24 |
5952514236 ps |
| T447 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.1469617035 |
|
|
Jul 28 08:12:14 PM PDT 24 |
Jul 28 08:16:38 PM PDT 24 |
2000101104 ps |
| T359 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.1862126872 |
|
|
Jul 28 08:33:22 PM PDT 24 |
Jul 28 08:44:16 PM PDT 24 |
5660049498 ps |
| T333 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2727102533 |
|
|
Jul 28 08:30:21 PM PDT 24 |
Jul 28 08:38:33 PM PDT 24 |
4994991712 ps |
| T352 |
/workspace/coverage/default/0.chip_sw_hmac_enc.1193782587 |
|
|
Jul 28 08:07:20 PM PDT 24 |
Jul 28 08:11:04 PM PDT 24 |
2511985204 ps |
| T827 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.43259531 |
|
|
Jul 28 08:39:26 PM PDT 24 |
Jul 28 08:47:10 PM PDT 24 |
4674372030 ps |
| T1005 |
/workspace/coverage/default/1.rom_keymgr_functest.3744396320 |
|
|
Jul 28 08:19:48 PM PDT 24 |
Jul 28 08:27:50 PM PDT 24 |
4944472572 ps |
| T1006 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2368357562 |
|
|
Jul 28 08:32:03 PM PDT 24 |
Jul 28 08:36:47 PM PDT 24 |
2789749624 ps |
| T1007 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.380713757 |
|
|
Jul 28 08:14:16 PM PDT 24 |
Jul 28 09:19:04 PM PDT 24 |
15298210792 ps |
| T1008 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3152151768 |
|
|
Jul 28 08:25:58 PM PDT 24 |
Jul 28 08:37:46 PM PDT 24 |
7420653240 ps |
| T542 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.4116926901 |
|
|
Jul 28 08:25:11 PM PDT 24 |
Jul 28 08:40:12 PM PDT 24 |
4938929700 ps |
| T244 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.2605452854 |
|
|
Jul 28 08:39:08 PM PDT 24 |
Jul 28 08:48:29 PM PDT 24 |
5879904090 ps |
| T227 |
/workspace/coverage/default/2.chip_sw_flash_init.632276569 |
|
|
Jul 28 08:19:47 PM PDT 24 |
Jul 28 08:46:20 PM PDT 24 |
24789373342 ps |
| T320 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1155636801 |
|
|
Jul 28 08:13:07 PM PDT 24 |
Jul 28 08:22:45 PM PDT 24 |
4212228378 ps |
| T1009 |
/workspace/coverage/default/2.chip_tap_straps_dev.1026843356 |
|
|
Jul 28 08:29:18 PM PDT 24 |
Jul 28 08:32:10 PM PDT 24 |
2758001585 ps |
| T1010 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.189823936 |
|
|
Jul 28 08:07:50 PM PDT 24 |
Jul 28 08:26:26 PM PDT 24 |
11499983782 ps |
| T1011 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1398255971 |
|
|
Jul 28 08:08:41 PM PDT 24 |
Jul 28 08:30:52 PM PDT 24 |
7612837904 ps |
| T743 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3196212199 |
|
|
Jul 28 08:36:27 PM PDT 24 |
Jul 28 08:42:24 PM PDT 24 |
3320666568 ps |
| T1012 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2925792368 |
|
|
Jul 28 08:13:59 PM PDT 24 |
Jul 28 08:23:17 PM PDT 24 |
5243262456 ps |
| T1013 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2910833166 |
|
|
Jul 28 08:27:40 PM PDT 24 |
Jul 28 08:37:57 PM PDT 24 |
4529425424 ps |
| T330 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.700910478 |
|
|
Jul 28 08:13:06 PM PDT 24 |
Jul 28 08:51:19 PM PDT 24 |
7826443556 ps |
| T1014 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.2480949772 |
|
|
Jul 28 08:14:41 PM PDT 24 |
Jul 28 09:18:05 PM PDT 24 |
14588786440 ps |
| T337 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1840042075 |
|
|
Jul 28 08:12:45 PM PDT 24 |
Jul 28 08:27:00 PM PDT 24 |
5559886736 ps |
| T146 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2308682216 |
|
|
Jul 28 08:33:13 PM PDT 24 |
Jul 28 08:39:21 PM PDT 24 |
3565734044 ps |
| T51 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.517476014 |
|
|
Jul 28 08:11:20 PM PDT 24 |
Jul 28 08:16:14 PM PDT 24 |
3783521984 ps |
| T419 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3651761139 |
|
|
Jul 28 08:06:25 PM PDT 24 |
Jul 28 08:11:39 PM PDT 24 |
3435020284 ps |
| T284 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1790513101 |
|
|
Jul 28 08:26:19 PM PDT 24 |
Jul 28 08:37:01 PM PDT 24 |
4312487411 ps |
| T420 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.152245249 |
|
|
Jul 28 08:31:25 PM PDT 24 |
Jul 28 08:41:43 PM PDT 24 |
4568706300 ps |
| T421 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3941940491 |
|
|
Jul 28 08:23:33 PM PDT 24 |
Jul 28 08:31:35 PM PDT 24 |
7757464928 ps |
| T422 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2627831652 |
|
|
Jul 28 08:30:03 PM PDT 24 |
Jul 28 08:41:31 PM PDT 24 |
6364673720 ps |
| T125 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1720061433 |
|
|
Jul 28 08:27:06 PM PDT 24 |
Jul 28 08:44:30 PM PDT 24 |
8164103600 ps |
| T423 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.2573306774 |
|
|
Jul 28 08:41:05 PM PDT 24 |
Jul 28 08:48:26 PM PDT 24 |
4658234628 ps |
| T424 |
/workspace/coverage/default/2.chip_sw_aes_idle.3364378553 |
|
|
Jul 28 08:25:57 PM PDT 24 |
Jul 28 08:31:37 PM PDT 24 |
3566688904 ps |
| T425 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.397472354 |
|
|
Jul 28 08:22:53 PM PDT 24 |
Jul 28 08:26:52 PM PDT 24 |
2720412192 ps |
| T186 |
/workspace/coverage/default/0.chip_sw_power_virus.286783181 |
|
|
Jul 28 08:16:28 PM PDT 24 |
Jul 28 08:44:10 PM PDT 24 |
5566726952 ps |
| T829 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.110469053 |
|
|
Jul 28 08:34:56 PM PDT 24 |
Jul 28 08:43:02 PM PDT 24 |
3753539548 ps |
| T1015 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1917126030 |
|
|
Jul 28 08:12:36 PM PDT 24 |
Jul 28 08:47:49 PM PDT 24 |
8119853068 ps |
| T37 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.3706334779 |
|
|
Jul 28 08:22:23 PM PDT 24 |
Jul 28 08:28:11 PM PDT 24 |
3257384374 ps |
| T76 |
/workspace/coverage/default/1.chip_jtag_mem_access.717271098 |
|
|
Jul 28 08:10:20 PM PDT 24 |
Jul 28 08:37:56 PM PDT 24 |
13313024578 ps |
| T251 |
/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.1522467910 |
|
|
Jul 28 08:29:48 PM PDT 24 |
Jul 28 08:35:10 PM PDT 24 |
3133442556 ps |
| T712 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.636911271 |
|
|
Jul 28 08:39:41 PM PDT 24 |
Jul 28 08:45:37 PM PDT 24 |
4304312900 ps |
| T1016 |
/workspace/coverage/default/1.rom_e2e_self_hash.4229271299 |
|
|
Jul 28 08:24:56 PM PDT 24 |
Jul 28 10:01:15 PM PDT 24 |
25862076648 ps |
| T285 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1202992960 |
|
|
Jul 28 08:10:29 PM PDT 24 |
Jul 28 08:19:44 PM PDT 24 |
4133098721 ps |
| T1017 |
/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1648174703 |
|
|
Jul 28 08:14:19 PM PDT 24 |
Jul 28 08:19:46 PM PDT 24 |
3787997238 ps |
| T713 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.359853920 |
|
|
Jul 28 08:09:47 PM PDT 24 |
Jul 28 09:56:09 PM PDT 24 |
39693894375 ps |
| T1018 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3156115203 |
|
|
Jul 28 08:23:06 PM PDT 24 |
Jul 28 08:45:07 PM PDT 24 |
15376171248 ps |
| T1019 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3376665177 |
|
|
Jul 28 08:08:35 PM PDT 24 |
Jul 28 08:19:27 PM PDT 24 |
3872682324 ps |
| T397 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.32471923 |
|
|
Jul 28 08:07:59 PM PDT 24 |
Jul 28 08:10:19 PM PDT 24 |
2187501812 ps |
| T1020 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.2478259133 |
|
|
Jul 28 08:17:32 PM PDT 24 |
Jul 28 08:27:02 PM PDT 24 |
4957231386 ps |
| T140 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.1406939612 |
|
|
Jul 28 08:08:13 PM PDT 24 |
Jul 28 08:17:10 PM PDT 24 |
4312428630 ps |
| T1021 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.288298664 |
|
|
Jul 28 08:20:24 PM PDT 24 |
Jul 28 08:23:27 PM PDT 24 |
2578776620 ps |
| T1022 |
/workspace/coverage/default/0.chip_sw_aes_enc.990452912 |
|
|
Jul 28 08:07:58 PM PDT 24 |
Jul 28 08:12:14 PM PDT 24 |
3644770734 ps |
| T778 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.4138960982 |
|
|
Jul 28 08:37:51 PM PDT 24 |
Jul 28 08:48:46 PM PDT 24 |
6309383320 ps |
| T1023 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.339431732 |
|
|
Jul 28 08:09:37 PM PDT 24 |
Jul 28 08:56:12 PM PDT 24 |
27559925918 ps |
| T1024 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.2620026786 |
|
|
Jul 28 08:22:35 PM PDT 24 |
Jul 28 08:26:38 PM PDT 24 |
2884734070 ps |
| T1025 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.1923369281 |
|
|
Jul 28 08:12:36 PM PDT 24 |
Jul 28 08:17:13 PM PDT 24 |
3151758096 ps |
| T1026 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3771930283 |
|
|
Jul 28 08:30:14 PM PDT 24 |
Jul 28 08:45:15 PM PDT 24 |
9718053644 ps |
| T1027 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2870490991 |
|
|
Jul 28 08:15:53 PM PDT 24 |
Jul 28 09:29:57 PM PDT 24 |
17667267582 ps |
| T38 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.1873220305 |
|
|
Jul 28 08:12:56 PM PDT 24 |
Jul 28 08:19:59 PM PDT 24 |
3639282745 ps |
| T370 |
/workspace/coverage/default/1.chip_sw_hmac_enc.1819304521 |
|
|
Jul 28 08:15:14 PM PDT 24 |
Jul 28 08:19:06 PM PDT 24 |
2538920704 ps |
| T1028 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.2097465134 |
|
|
Jul 28 08:21:59 PM PDT 24 |
Jul 28 08:27:10 PM PDT 24 |
2891220050 ps |
| T1029 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.3623016681 |
|
|
Jul 28 08:18:10 PM PDT 24 |
Jul 28 08:43:00 PM PDT 24 |
7733161812 ps |
| T331 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.2794679199 |
|
|
Jul 28 08:15:45 PM PDT 24 |
Jul 28 08:44:41 PM PDT 24 |
7927873160 ps |
| T1030 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.122810845 |
|
|
Jul 28 08:16:32 PM PDT 24 |
Jul 28 09:32:13 PM PDT 24 |
14747081178 ps |
| T147 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.2112073384 |
|
|
Jul 28 08:35:39 PM PDT 24 |
Jul 28 08:48:00 PM PDT 24 |
5769508468 ps |
| T835 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.1627985672 |
|
|
Jul 28 08:33:46 PM PDT 24 |
Jul 28 08:45:51 PM PDT 24 |
4560790504 ps |
| T230 |
/workspace/coverage/default/1.chip_sw_flash_init.3355379577 |
|
|
Jul 28 08:12:27 PM PDT 24 |
Jul 28 08:48:30 PM PDT 24 |
18820938574 ps |
| T734 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.2874229638 |
|
|
Jul 28 08:26:09 PM PDT 24 |
Jul 28 08:31:02 PM PDT 24 |
3530324040 ps |
| T744 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.601162066 |
|
|
Jul 28 08:41:11 PM PDT 24 |
Jul 28 08:50:03 PM PDT 24 |
4866137700 ps |
| T1031 |
/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.1659961051 |
|
|
Jul 28 08:06:12 PM PDT 24 |
Jul 28 08:29:00 PM PDT 24 |
9886803256 ps |
| T258 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.135622928 |
|
|
Jul 28 08:17:54 PM PDT 24 |
Jul 28 08:20:55 PM PDT 24 |
2146401612 ps |
| T1032 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2043403921 |
|
|
Jul 28 08:12:05 PM PDT 24 |
Jul 28 08:16:44 PM PDT 24 |
3318419680 ps |
| T275 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.3006767783 |
|
|
Jul 28 08:10:30 PM PDT 24 |
Jul 28 08:22:13 PM PDT 24 |
5830024080 ps |
| T277 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.2909056697 |
|
|
Jul 28 08:08:17 PM PDT 24 |
Jul 28 08:36:45 PM PDT 24 |
7852287380 ps |
| T278 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.523847801 |
|
|
Jul 28 08:34:48 PM PDT 24 |
Jul 28 08:42:26 PM PDT 24 |
3661075584 ps |
| T279 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.288162794 |
|
|
Jul 28 08:26:49 PM PDT 24 |
Jul 28 08:38:25 PM PDT 24 |
5546613806 ps |
| T280 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.4083122006 |
|
|
Jul 28 08:06:58 PM PDT 24 |
Jul 28 08:26:48 PM PDT 24 |
6861045048 ps |
| T281 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3097462446 |
|
|
Jul 28 08:15:44 PM PDT 24 |
Jul 28 08:54:49 PM PDT 24 |
10725051110 ps |
| T242 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2008367130 |
|
|
Jul 28 08:23:27 PM PDT 24 |
Jul 28 08:49:06 PM PDT 24 |
12123281468 ps |
| T282 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.1283276165 |
|
|
Jul 28 08:37:02 PM PDT 24 |
Jul 28 08:46:33 PM PDT 24 |
5916089682 ps |
| T283 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.4259072880 |
|
|
Jul 28 08:36:24 PM PDT 24 |
Jul 28 08:44:14 PM PDT 24 |
5512085459 ps |
| T46 |
/workspace/coverage/default/0.chip_jtag_csr_rw.1719020766 |
|
|
Jul 28 07:59:55 PM PDT 24 |
Jul 28 08:17:39 PM PDT 24 |
11084269528 ps |
| T314 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1066592911 |
|
|
Jul 28 08:07:49 PM PDT 24 |
Jul 28 08:34:45 PM PDT 24 |
8157289384 ps |
| T315 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.259088534 |
|
|
Jul 28 08:35:36 PM PDT 24 |
Jul 28 08:42:49 PM PDT 24 |
4062627840 ps |
| T316 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.3479217320 |
|
|
Jul 28 08:17:40 PM PDT 24 |
Jul 28 08:26:08 PM PDT 24 |
6308642840 ps |
| T317 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1111261917 |
|
|
Jul 28 08:13:43 PM PDT 24 |
Jul 28 08:26:58 PM PDT 24 |
6915083528 ps |
| T318 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3574797925 |
|
|
Jul 28 08:33:27 PM PDT 24 |
Jul 28 08:39:59 PM PDT 24 |
3176129124 ps |
| T319 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.3507976531 |
|
|
Jul 28 08:25:21 PM PDT 24 |
Jul 28 08:35:52 PM PDT 24 |
3469068956 ps |
| T197 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.4161205585 |
|
|
Jul 28 08:05:14 PM PDT 24 |
Jul 28 08:10:46 PM PDT 24 |
3536746956 ps |
| T830 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2993522563 |
|
|
Jul 28 08:36:34 PM PDT 24 |
Jul 28 08:42:59 PM PDT 24 |
3567542680 ps |
| T1033 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2898940517 |
|
|
Jul 28 08:08:19 PM PDT 24 |
Jul 28 08:19:55 PM PDT 24 |
5039460702 ps |
| T175 |
/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.2442041786 |
|
|
Jul 28 08:07:28 PM PDT 24 |
Jul 28 08:13:43 PM PDT 24 |
4414570254 ps |
| T1034 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.2035517035 |
|
|
Jul 28 08:27:05 PM PDT 24 |
Jul 28 08:30:28 PM PDT 24 |
2448412193 ps |
| T1035 |
/workspace/coverage/default/0.rom_e2e_self_hash.16210039 |
|
|
Jul 28 08:15:52 PM PDT 24 |
Jul 28 09:53:19 PM PDT 24 |
25821187200 ps |
| T1036 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1229292970 |
|
|
Jul 28 08:13:12 PM PDT 24 |
Jul 28 08:18:31 PM PDT 24 |
3433375360 ps |
| T1037 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2497391958 |
|
|
Jul 28 08:19:06 PM PDT 24 |
Jul 28 08:31:05 PM PDT 24 |
4692757112 ps |
| T399 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1402466393 |
|
|
Jul 28 08:35:14 PM PDT 24 |
Jul 28 08:43:06 PM PDT 24 |
3679627224 ps |
| T1038 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.4293967693 |
|
|
Jul 28 08:08:12 PM PDT 24 |
Jul 28 08:29:16 PM PDT 24 |
5848481137 ps |
| T1039 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.2706632546 |
|
|
Jul 28 08:19:51 PM PDT 24 |
Jul 28 08:23:38 PM PDT 24 |
2299106488 ps |
| T810 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.73950753 |
|
|
Jul 28 08:34:07 PM PDT 24 |
Jul 28 08:40:51 PM PDT 24 |
2992809774 ps |
| T1040 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3177905598 |
|
|
Jul 28 08:31:25 PM PDT 24 |
Jul 28 08:40:10 PM PDT 24 |
7039635752 ps |
| T65 |
/workspace/coverage/default/1.chip_tap_straps_testunlock0.2157658029 |
|
|
Jul 28 08:19:33 PM PDT 24 |
Jul 28 08:27:34 PM PDT 24 |
4584947508 ps |
| T825 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.1707134930 |
|
|
Jul 28 08:36:18 PM PDT 24 |
Jul 28 08:46:29 PM PDT 24 |
6205526168 ps |
| T1041 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod.352234528 |
|
|
Jul 28 08:27:37 PM PDT 24 |
Jul 28 09:29:13 PM PDT 24 |
16169573181 ps |
| T755 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.3217332549 |
|
|
Jul 28 08:13:25 PM PDT 24 |
Jul 28 08:19:52 PM PDT 24 |
3283225560 ps |
| T771 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3545592278 |
|
|
Jul 28 08:34:36 PM PDT 24 |
Jul 28 08:41:03 PM PDT 24 |
4007354796 ps |
| T1042 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.4162046499 |
|
|
Jul 28 08:29:03 PM PDT 24 |
Jul 28 08:33:35 PM PDT 24 |
2967276256 ps |
| T1043 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.191515720 |
|
|
Jul 28 08:20:23 PM PDT 24 |
Jul 28 08:59:20 PM PDT 24 |
12731640452 ps |
| T1044 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.3863314207 |
|
|
Jul 28 08:12:27 PM PDT 24 |
Jul 28 09:04:26 PM PDT 24 |
25771680500 ps |
| T849 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.1358104220 |
|
|
Jul 28 08:37:05 PM PDT 24 |
Jul 28 08:44:16 PM PDT 24 |
4573564018 ps |
| T1045 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.3812221170 |
|
|
Jul 28 08:11:38 PM PDT 24 |
Jul 28 08:17:37 PM PDT 24 |
2693094445 ps |
| T410 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.1320032856 |
|
|
Jul 28 08:21:48 PM PDT 24 |
Jul 28 08:28:47 PM PDT 24 |
5074406116 ps |
| T1046 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.2835217458 |
|
|
Jul 28 08:31:28 PM PDT 24 |
Jul 28 08:41:06 PM PDT 24 |
6304192436 ps |
| T48 |
/workspace/coverage/default/2.chip_sw_alert_test.266878182 |
|
|
Jul 28 08:25:59 PM PDT 24 |
Jul 28 08:30:45 PM PDT 24 |
3447743600 ps |
| T1047 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.579297679 |
|
|
Jul 28 08:08:01 PM PDT 24 |
Jul 28 08:28:55 PM PDT 24 |
10660106952 ps |
| T763 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2950343068 |
|
|
Jul 28 08:38:29 PM PDT 24 |
Jul 28 08:43:59 PM PDT 24 |
3402058500 ps |
| T1048 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.2304476159 |
|
|
Jul 28 08:08:41 PM PDT 24 |
Jul 28 08:30:30 PM PDT 24 |
7425990392 ps |
| T1049 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.696825155 |
|
|
Jul 28 08:33:00 PM PDT 24 |
Jul 28 08:40:48 PM PDT 24 |
6386743268 ps |
| T90 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.3963026334 |
|
|
Jul 28 08:37:47 PM PDT 24 |
Jul 28 08:44:58 PM PDT 24 |
4433437480 ps |
| T1050 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.4233391103 |
|
|
Jul 28 08:06:31 PM PDT 24 |
Jul 28 08:36:47 PM PDT 24 |
8006190784 ps |
| T59 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1715713623 |
|
|
Jul 28 08:21:09 PM PDT 24 |
Jul 28 08:29:01 PM PDT 24 |
5295048166 ps |
| T1051 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.579561602 |
|
|
Jul 28 08:23:31 PM PDT 24 |
Jul 28 08:40:49 PM PDT 24 |
5926659736 ps |
| T1052 |
/workspace/coverage/default/4.chip_tap_straps_dev.97310692 |
|
|
Jul 28 08:30:56 PM PDT 24 |
Jul 28 08:37:51 PM PDT 24 |
4666757585 ps |
| T412 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3004447914 |
|
|
Jul 28 08:12:37 PM PDT 24 |
Jul 28 08:14:54 PM PDT 24 |
3211073796 ps |
| T804 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3001891684 |
|
|
Jul 28 08:37:41 PM PDT 24 |
Jul 28 08:45:10 PM PDT 24 |
3693899138 ps |
| T764 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2576098159 |
|
|
Jul 28 08:34:27 PM PDT 24 |
Jul 28 08:42:22 PM PDT 24 |
3187639300 ps |
| T1053 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1304640415 |
|
|
Jul 28 08:13:52 PM PDT 24 |
Jul 28 08:18:28 PM PDT 24 |
2214742024 ps |
| T81 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.183447976 |
|
|
Jul 28 08:14:28 PM PDT 24 |
Jul 28 08:39:34 PM PDT 24 |
12403718392 ps |
| T1054 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3465295743 |
|
|
Jul 28 08:14:43 PM PDT 24 |
Jul 28 09:10:39 PM PDT 24 |
11907599430 ps |
| T231 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3260562471 |
|
|
Jul 28 08:11:12 PM PDT 24 |
Jul 28 08:20:19 PM PDT 24 |
4135317120 ps |
| T1055 |
/workspace/coverage/default/2.chip_sw_alert_handler_escalation.937571978 |
|
|
Jul 28 08:25:20 PM PDT 24 |
Jul 28 08:36:42 PM PDT 24 |
6057550760 ps |
| T1056 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.2500175268 |
|
|
Jul 28 08:20:55 PM PDT 24 |
Jul 28 08:25:34 PM PDT 24 |
3092779126 ps |
| T1057 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.4094133479 |
|
|
Jul 28 08:26:57 PM PDT 24 |
Jul 28 08:36:36 PM PDT 24 |
4092810184 ps |
| T1058 |
/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2565151917 |
|
|
Jul 28 08:09:50 PM PDT 24 |
Jul 28 08:14:06 PM PDT 24 |
2671130116 ps |
| T1059 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.1651887735 |
|
|
Jul 28 08:07:15 PM PDT 24 |
Jul 28 08:12:50 PM PDT 24 |
3472195958 ps |
| T1060 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.2487818497 |
|
|
Jul 28 08:07:37 PM PDT 24 |
Jul 28 08:12:41 PM PDT 24 |
3033968000 ps |
| T815 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2919204349 |
|
|
Jul 28 08:37:35 PM PDT 24 |
Jul 28 08:43:57 PM PDT 24 |
3795947312 ps |
| T341 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3483780159 |
|
|
Jul 28 08:30:09 PM PDT 24 |
Jul 28 08:41:00 PM PDT 24 |
4498936266 ps |
| T1061 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.3156274246 |
|
|
Jul 28 08:09:09 PM PDT 24 |
Jul 28 08:13:25 PM PDT 24 |
2600576696 ps |
| T240 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1223018467 |
|
|
Jul 28 08:12:20 PM PDT 24 |
Jul 28 08:20:47 PM PDT 24 |
6672970940 ps |
| T1062 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3787998748 |
|
|
Jul 28 08:07:41 PM PDT 24 |
Jul 28 08:26:54 PM PDT 24 |
10918381909 ps |
| T198 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2753895165 |
|
|
Jul 28 08:06:14 PM PDT 24 |
Jul 28 08:17:18 PM PDT 24 |
4631264895 ps |
| T1063 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1743580206 |
|
|
Jul 28 08:09:46 PM PDT 24 |
Jul 28 08:22:10 PM PDT 24 |
9299295610 ps |
| T1064 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.2273147552 |
|
|
Jul 28 08:11:30 PM PDT 24 |
Jul 28 08:14:51 PM PDT 24 |
2822176600 ps |
| T1065 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.2010307149 |
|
|
Jul 28 08:38:54 PM PDT 24 |
Jul 28 08:48:32 PM PDT 24 |
4262104652 ps |
| T1066 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.3158820432 |
|
|
Jul 28 08:06:49 PM PDT 24 |
Jul 28 08:56:54 PM PDT 24 |
12031799024 ps |
| T765 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.2647598375 |
|
|
Jul 28 08:37:31 PM PDT 24 |
Jul 28 08:48:31 PM PDT 24 |
5033197958 ps |
| T199 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.4107890696 |
|
|
Jul 28 08:13:16 PM PDT 24 |
Jul 28 08:23:29 PM PDT 24 |
5277524431 ps |
| T1067 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2318601655 |
|
|
Jul 28 08:30:21 PM PDT 24 |
Jul 28 08:45:42 PM PDT 24 |
9258029461 ps |
| T1068 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.1801805485 |
|
|
Jul 28 08:36:47 PM PDT 24 |
Jul 28 08:47:54 PM PDT 24 |
5907860516 ps |
| T1069 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2369752875 |
|
|
Jul 28 08:24:33 PM PDT 24 |
Jul 28 08:38:48 PM PDT 24 |
10143742936 ps |
| T1070 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1156402448 |
|
|
Jul 28 08:08:46 PM PDT 24 |
Jul 28 08:17:01 PM PDT 24 |
4373168576 ps |