| T1231 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3810336043 |
|
|
Jul 28 08:27:14 PM PDT 24 |
Jul 28 08:39:32 PM PDT 24 |
4433123104 ps |
| T1232 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2112107328 |
|
|
Jul 28 08:21:17 PM PDT 24 |
Jul 28 08:30:42 PM PDT 24 |
3900954488 ps |
| T1233 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.40313615 |
|
|
Jul 28 08:23:55 PM PDT 24 |
Jul 28 08:30:19 PM PDT 24 |
5818933198 ps |
| T321 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.1449393560 |
|
|
Jul 28 08:16:07 PM PDT 24 |
Jul 28 08:35:38 PM PDT 24 |
5331002616 ps |
| T1234 |
/workspace/coverage/default/2.chip_sw_kmac_app_rom.2798420465 |
|
|
Jul 28 08:28:08 PM PDT 24 |
Jul 28 08:31:28 PM PDT 24 |
2373432050 ps |
| T1235 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.2768369961 |
|
|
Jul 28 08:26:03 PM PDT 24 |
Jul 28 09:11:07 PM PDT 24 |
11226720612 ps |
| T1236 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.4271607615 |
|
|
Jul 28 08:28:04 PM PDT 24 |
Jul 28 09:40:06 PM PDT 24 |
22775638940 ps |
| T193 |
/workspace/coverage/default/0.chip_jtag_mem_access.1246633851 |
|
|
Jul 28 07:59:53 PM PDT 24 |
Jul 28 08:24:21 PM PDT 24 |
13688468100 ps |
| T1237 |
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3435537905 |
|
|
Jul 28 08:29:50 PM PDT 24 |
Jul 28 09:02:47 PM PDT 24 |
8343582548 ps |
| T1238 |
/workspace/coverage/default/2.chip_sw_aes_entropy.2433866072 |
|
|
Jul 28 08:25:11 PM PDT 24 |
Jul 28 08:30:17 PM PDT 24 |
2590054524 ps |
| T1239 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.3096745000 |
|
|
Jul 28 08:28:48 PM PDT 24 |
Jul 28 08:32:11 PM PDT 24 |
2726527744 ps |
| T1240 |
/workspace/coverage/default/1.chip_sw_inject_scramble_seed.549619947 |
|
|
Jul 28 08:10:37 PM PDT 24 |
Jul 28 11:25:19 PM PDT 24 |
64880417002 ps |
| T1241 |
/workspace/coverage/default/1.chip_tap_straps_dev.2667681879 |
|
|
Jul 28 08:17:04 PM PDT 24 |
Jul 28 08:21:05 PM PDT 24 |
3894038811 ps |
| T1242 |
/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3121913602 |
|
|
Jul 28 08:23:46 PM PDT 24 |
Jul 28 08:28:56 PM PDT 24 |
3444244530 ps |
| T372 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1037952537 |
|
|
Jul 28 08:17:32 PM PDT 24 |
Jul 28 08:24:24 PM PDT 24 |
6347099004 ps |
| T1243 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.4003556288 |
|
|
Jul 28 08:35:26 PM PDT 24 |
Jul 28 08:43:58 PM PDT 24 |
5399918250 ps |
| T130 |
/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.3351683028 |
|
|
Jul 28 08:29:20 PM PDT 24 |
Jul 28 09:26:47 PM PDT 24 |
22316659181 ps |
| T35 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2685868327 |
|
|
Jul 28 08:09:15 PM PDT 24 |
Jul 28 08:18:25 PM PDT 24 |
6557160400 ps |
| T107 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.4115772970 |
|
|
Jul 28 08:08:47 PM PDT 24 |
Jul 28 08:16:54 PM PDT 24 |
4215517912 ps |
| T448 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2401812314 |
|
|
Jul 28 08:09:40 PM PDT 24 |
Jul 28 08:13:16 PM PDT 24 |
2524317808 ps |
| T449 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod.2675880942 |
|
|
Jul 28 08:17:19 PM PDT 24 |
Jul 28 09:22:30 PM PDT 24 |
15380868831 ps |
| T154 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.3258501457 |
|
|
Jul 28 08:17:16 PM PDT 24 |
Jul 28 08:26:22 PM PDT 24 |
4398818732 ps |
| T450 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.2506108651 |
|
|
Jul 28 08:27:32 PM PDT 24 |
Jul 28 08:33:45 PM PDT 24 |
2969146364 ps |
| T152 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1581270630 |
|
|
Jul 28 08:05:58 PM PDT 24 |
Jul 28 08:19:11 PM PDT 24 |
6346356058 ps |
| T451 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3853236304 |
|
|
Jul 28 08:37:46 PM PDT 24 |
Jul 28 08:44:54 PM PDT 24 |
3827143044 ps |
| T377 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2712113302 |
|
|
Jul 28 08:33:01 PM PDT 24 |
Jul 28 08:40:13 PM PDT 24 |
3696552944 ps |
| T452 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.1725918892 |
|
|
Jul 28 08:23:11 PM PDT 24 |
Jul 28 08:30:12 PM PDT 24 |
4065152360 ps |
| T453 |
/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2295607359 |
|
|
Jul 28 08:22:03 PM PDT 24 |
Jul 28 08:35:01 PM PDT 24 |
6164384610 ps |
| T1244 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1438384997 |
|
|
Jul 28 08:13:55 PM PDT 24 |
Jul 28 09:13:23 PM PDT 24 |
11386498392 ps |
| T1245 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2548971676 |
|
|
Jul 28 08:22:25 PM PDT 24 |
Jul 28 08:48:59 PM PDT 24 |
8730987940 ps |
| T1246 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.1177612544 |
|
|
Jul 28 08:15:11 PM PDT 24 |
Jul 28 09:13:06 PM PDT 24 |
17121939596 ps |
| T1247 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.599086228 |
|
|
Jul 28 08:08:24 PM PDT 24 |
Jul 28 08:17:12 PM PDT 24 |
6828244256 ps |
| T1248 |
/workspace/coverage/default/2.chip_sw_kmac_smoketest.1580674243 |
|
|
Jul 28 08:31:11 PM PDT 24 |
Jul 28 08:36:20 PM PDT 24 |
3089600664 ps |
| T1249 |
/workspace/coverage/default/2.chip_sw_power_idle_load.2670428572 |
|
|
Jul 28 08:27:23 PM PDT 24 |
Jul 28 08:38:29 PM PDT 24 |
4522148814 ps |
| T1250 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.11539868 |
|
|
Jul 28 08:24:28 PM PDT 24 |
Jul 28 08:37:17 PM PDT 24 |
7990187734 ps |
| T1251 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.4224986908 |
|
|
Jul 28 08:10:44 PM PDT 24 |
Jul 28 08:15:43 PM PDT 24 |
3523868806 ps |
| T1252 |
/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.919347990 |
|
|
Jul 28 08:09:42 PM PDT 24 |
Jul 28 08:21:11 PM PDT 24 |
4497621700 ps |
| T847 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.448328295 |
|
|
Jul 28 08:31:50 PM PDT 24 |
Jul 28 08:37:53 PM PDT 24 |
3182360232 ps |
| T235 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.996659402 |
|
|
Jul 28 08:26:23 PM PDT 24 |
Jul 28 08:32:41 PM PDT 24 |
3755420523 ps |
| T1253 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.813609697 |
|
|
Jul 28 08:06:34 PM PDT 24 |
Jul 28 08:21:56 PM PDT 24 |
6377975596 ps |
| T1254 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.760292089 |
|
|
Jul 28 08:26:39 PM PDT 24 |
Jul 28 08:52:22 PM PDT 24 |
11563191325 ps |
| T1255 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1447830824 |
|
|
Jul 28 08:12:32 PM PDT 24 |
Jul 28 08:26:13 PM PDT 24 |
13035595647 ps |
| T1256 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.1116007295 |
|
|
Jul 28 08:07:10 PM PDT 24 |
Jul 28 08:18:39 PM PDT 24 |
4249322720 ps |
| T223 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.4183129960 |
|
|
Jul 28 08:25:37 PM PDT 24 |
Jul 28 08:45:56 PM PDT 24 |
6719684090 ps |
| T58 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.2139015171 |
|
|
Jul 28 08:10:09 PM PDT 24 |
Jul 28 08:13:12 PM PDT 24 |
2876004552 ps |
| T1257 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.439443066 |
|
|
Jul 28 08:07:43 PM PDT 24 |
Jul 28 08:17:15 PM PDT 24 |
5163373150 ps |
| T1258 |
/workspace/coverage/default/2.rom_volatile_raw_unlock.1257510670 |
|
|
Jul 28 08:30:08 PM PDT 24 |
Jul 28 08:32:12 PM PDT 24 |
2674957456 ps |
| T69 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3722959793 |
|
|
Jul 28 08:07:51 PM PDT 24 |
Jul 28 08:16:51 PM PDT 24 |
3117693300 ps |
| T234 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.2085203455 |
|
|
Jul 28 08:21:32 PM PDT 24 |
Jul 28 08:30:13 PM PDT 24 |
4979427280 ps |
| T1259 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.541693662 |
|
|
Jul 28 08:29:38 PM PDT 24 |
Jul 28 08:41:48 PM PDT 24 |
5009875726 ps |
| T1260 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1573586672 |
|
|
Jul 28 08:17:30 PM PDT 24 |
Jul 28 08:36:59 PM PDT 24 |
6296965732 ps |
| T1261 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2384429791 |
|
|
Jul 28 08:31:00 PM PDT 24 |
Jul 28 08:36:14 PM PDT 24 |
3345066398 ps |
| T1262 |
/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3578163422 |
|
|
Jul 28 08:17:57 PM PDT 24 |
Jul 28 08:53:42 PM PDT 24 |
26079994137 ps |
| T1263 |
/workspace/coverage/default/0.rom_raw_unlock.1588427231 |
|
|
Jul 28 08:11:11 PM PDT 24 |
Jul 28 08:15:56 PM PDT 24 |
6140684824 ps |
| T1264 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2957302411 |
|
|
Jul 28 08:10:40 PM PDT 24 |
Jul 28 08:19:52 PM PDT 24 |
3136470011 ps |
| T1265 |
/workspace/coverage/default/1.chip_sw_uart_smoketest.1282991035 |
|
|
Jul 28 08:22:12 PM PDT 24 |
Jul 28 08:28:08 PM PDT 24 |
2955521016 ps |
| T1266 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.3605379803 |
|
|
Jul 28 08:06:13 PM PDT 24 |
Jul 28 08:08:57 PM PDT 24 |
3436742719 ps |
| T1267 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3478051075 |
|
|
Jul 28 08:23:51 PM PDT 24 |
Jul 28 08:48:49 PM PDT 24 |
22651083404 ps |
| T1268 |
/workspace/coverage/default/29.chip_sw_all_escalation_resets.480339472 |
|
|
Jul 28 08:33:54 PM PDT 24 |
Jul 28 08:45:29 PM PDT 24 |
4505641336 ps |
| T342 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.926809713 |
|
|
Jul 28 08:08:44 PM PDT 24 |
Jul 28 08:21:38 PM PDT 24 |
4323431188 ps |
| T439 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1412541021 |
|
|
Jul 28 08:17:44 PM PDT 24 |
Jul 28 08:42:58 PM PDT 24 |
19985714258 ps |
| T1269 |
/workspace/coverage/default/2.chip_sw_edn_kat.3460699298 |
|
|
Jul 28 08:24:00 PM PDT 24 |
Jul 28 08:35:07 PM PDT 24 |
3784543540 ps |
| T1270 |
/workspace/coverage/default/0.chip_sw_aes_masking_off.4066563827 |
|
|
Jul 28 08:09:32 PM PDT 24 |
Jul 28 08:14:42 PM PDT 24 |
3281539323 ps |
| T1271 |
/workspace/coverage/default/1.rom_e2e_shutdown_output.2953820576 |
|
|
Jul 28 08:24:03 PM PDT 24 |
Jul 28 09:10:09 PM PDT 24 |
26539953925 ps |
| T1272 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3909182666 |
|
|
Jul 28 08:22:35 PM PDT 24 |
Jul 28 08:29:44 PM PDT 24 |
4386377853 ps |
| T1273 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.4094277274 |
|
|
Jul 28 08:12:24 PM PDT 24 |
Jul 28 08:22:59 PM PDT 24 |
4544639680 ps |
| T1274 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1136617722 |
|
|
Jul 28 08:06:34 PM PDT 24 |
Jul 28 10:57:11 PM PDT 24 |
59576055064 ps |
| T1275 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2242234240 |
|
|
Jul 28 08:31:53 PM PDT 24 |
Jul 28 08:44:16 PM PDT 24 |
4264305050 ps |
| T843 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1990137573 |
|
|
Jul 28 08:38:07 PM PDT 24 |
Jul 28 08:44:17 PM PDT 24 |
3263715108 ps |
| T786 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.238502476 |
|
|
Jul 28 08:39:10 PM PDT 24 |
Jul 28 08:47:09 PM PDT 24 |
4485495210 ps |
| T1276 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.3025002129 |
|
|
Jul 28 08:22:43 PM PDT 24 |
Jul 28 09:53:54 PM PDT 24 |
47614368440 ps |
| T1277 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3220312781 |
|
|
Jul 28 08:33:26 PM PDT 24 |
Jul 28 09:02:46 PM PDT 24 |
8182765120 ps |
| T1278 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1854291908 |
|
|
Jul 28 08:06:48 PM PDT 24 |
Jul 28 08:22:48 PM PDT 24 |
6619005284 ps |
| T325 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.1135285730 |
|
|
Jul 28 08:26:05 PM PDT 24 |
Jul 28 08:40:41 PM PDT 24 |
4459241146 ps |
| T1279 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3894675153 |
|
|
Jul 28 08:07:46 PM PDT 24 |
Jul 28 09:40:12 PM PDT 24 |
47284950006 ps |
| T1280 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.515363138 |
|
|
Jul 28 08:09:39 PM PDT 24 |
Jul 28 08:16:14 PM PDT 24 |
3419582985 ps |
| T1281 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.397428628 |
|
|
Jul 28 08:30:47 PM PDT 24 |
Jul 28 08:40:23 PM PDT 24 |
5652968840 ps |
| T1282 |
/workspace/coverage/default/0.chip_tap_straps_rma.2930700306 |
|
|
Jul 28 08:08:07 PM PDT 24 |
Jul 28 08:10:21 PM PDT 24 |
2217755341 ps |
| T1283 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1251792604 |
|
|
Jul 28 08:13:41 PM PDT 24 |
Jul 28 08:21:59 PM PDT 24 |
18992050976 ps |
| T1284 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1476675622 |
|
|
Jul 28 08:10:52 PM PDT 24 |
Jul 28 08:22:46 PM PDT 24 |
5448861960 ps |
| T1285 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3673021497 |
|
|
Jul 28 08:12:11 PM PDT 24 |
Jul 28 08:53:29 PM PDT 24 |
34128098296 ps |
| T335 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.432113463 |
|
|
Jul 28 08:13:58 PM PDT 24 |
Jul 28 08:29:49 PM PDT 24 |
4726263280 ps |
| T1286 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.147829115 |
|
|
Jul 28 08:15:14 PM PDT 24 |
Jul 28 09:06:01 PM PDT 24 |
11774831016 ps |
| T1287 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.3237791380 |
|
|
Jul 28 08:34:28 PM PDT 24 |
Jul 28 09:31:13 PM PDT 24 |
14920537564 ps |
| T1288 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1553305223 |
|
|
Jul 28 08:05:50 PM PDT 24 |
Jul 28 09:41:01 PM PDT 24 |
50873193685 ps |
| T766 |
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1064470278 |
|
|
Jul 28 08:38:10 PM PDT 24 |
Jul 28 08:44:39 PM PDT 24 |
3381801610 ps |
| T310 |
/workspace/coverage/default/56.chip_sw_all_escalation_resets.2304383544 |
|
|
Jul 28 08:35:53 PM PDT 24 |
Jul 28 08:46:09 PM PDT 24 |
5483080752 ps |
| T440 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.221358922 |
|
|
Jul 28 08:28:01 PM PDT 24 |
Jul 28 08:51:34 PM PDT 24 |
23831499090 ps |
| T1289 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.1295067133 |
|
|
Jul 28 08:08:43 PM PDT 24 |
Jul 28 08:16:11 PM PDT 24 |
5988412070 ps |
| T1290 |
/workspace/coverage/default/0.chip_sw_example_flash.40799907 |
|
|
Jul 28 08:10:40 PM PDT 24 |
Jul 28 08:14:10 PM PDT 24 |
2329902506 ps |
| T1291 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2921667849 |
|
|
Jul 28 08:11:45 PM PDT 24 |
Jul 28 08:22:03 PM PDT 24 |
6391451932 ps |
| T1292 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1997602582 |
|
|
Jul 28 08:13:26 PM PDT 24 |
Jul 28 08:16:40 PM PDT 24 |
2807441934 ps |
| T1293 |
/workspace/coverage/default/1.chip_sw_alert_handler_escalation.1929369174 |
|
|
Jul 28 08:14:08 PM PDT 24 |
Jul 28 08:22:01 PM PDT 24 |
4368177784 ps |
| T171 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.2329664134 |
|
|
Jul 28 08:07:59 PM PDT 24 |
Jul 28 09:25:36 PM PDT 24 |
43182016694 ps |
| T1294 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3689249740 |
|
|
Jul 28 08:15:25 PM PDT 24 |
Jul 28 08:23:47 PM PDT 24 |
5408147412 ps |
| T1295 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3868889621 |
|
|
Jul 28 08:08:16 PM PDT 24 |
Jul 28 08:16:28 PM PDT 24 |
4537419730 ps |
| T1296 |
/workspace/coverage/default/0.chip_sw_power_idle_load.3029363482 |
|
|
Jul 28 08:12:37 PM PDT 24 |
Jul 28 08:23:57 PM PDT 24 |
4630002160 ps |
| T831 |
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1327877123 |
|
|
Jul 28 08:41:39 PM PDT 24 |
Jul 28 08:48:35 PM PDT 24 |
3703419860 ps |
| T828 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.460131622 |
|
|
Jul 28 08:37:26 PM PDT 24 |
Jul 28 08:47:01 PM PDT 24 |
4387977340 ps |
| T836 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1410507655 |
|
|
Jul 28 08:35:04 PM PDT 24 |
Jul 28 08:42:39 PM PDT 24 |
3919667396 ps |
| T1297 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.3206699730 |
|
|
Jul 28 08:09:57 PM PDT 24 |
Jul 28 08:15:16 PM PDT 24 |
2889053908 ps |
| T1298 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.530193597 |
|
|
Jul 28 08:12:53 PM PDT 24 |
Jul 28 08:18:11 PM PDT 24 |
6413464568 ps |
| T1299 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.1560342425 |
|
|
Jul 28 08:28:25 PM PDT 24 |
Jul 28 08:34:05 PM PDT 24 |
2797350152 ps |
| T1300 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.1596602992 |
|
|
Jul 28 08:14:35 PM PDT 24 |
Jul 28 09:22:45 PM PDT 24 |
14627444023 ps |
| T172 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.611059377 |
|
|
Jul 28 08:09:34 PM PDT 24 |
Jul 28 09:29:49 PM PDT 24 |
44203577902 ps |
| T441 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4126849264 |
|
|
Jul 28 08:28:04 PM PDT 24 |
Jul 28 08:35:08 PM PDT 24 |
6913414712 ps |
| T10 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3077437405 |
|
|
Jul 28 08:16:25 PM PDT 24 |
Jul 28 08:20:21 PM PDT 24 |
3301934372 ps |
| T355 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.3848344242 |
|
|
Jul 28 08:21:27 PM PDT 24 |
Jul 28 08:25:19 PM PDT 24 |
2684735650 ps |
| T1301 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3694400277 |
|
|
Jul 28 08:22:52 PM PDT 24 |
Jul 28 08:35:14 PM PDT 24 |
4922132749 ps |
| T846 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.330179006 |
|
|
Jul 28 08:36:12 PM PDT 24 |
Jul 28 08:48:53 PM PDT 24 |
5856709032 ps |
| T1302 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3286909232 |
|
|
Jul 28 08:32:39 PM PDT 24 |
Jul 28 08:39:52 PM PDT 24 |
4220772212 ps |
| T1303 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.1465411511 |
|
|
Jul 28 08:15:24 PM PDT 24 |
Jul 28 08:21:23 PM PDT 24 |
3309162040 ps |
| T326 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.176148486 |
|
|
Jul 28 08:16:22 PM PDT 24 |
Jul 28 08:30:05 PM PDT 24 |
4612303700 ps |
| T150 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3128573154 |
|
|
Jul 28 08:24:30 PM PDT 24 |
Jul 28 08:26:25 PM PDT 24 |
2504460457 ps |
| T1304 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.1044816480 |
|
|
Jul 28 08:07:06 PM PDT 24 |
Jul 28 08:13:55 PM PDT 24 |
3858704824 ps |
| T1305 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.1895354625 |
|
|
Jul 28 08:13:39 PM PDT 24 |
Jul 28 08:29:33 PM PDT 24 |
5545356250 ps |
| T1306 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.1207849680 |
|
|
Jul 28 08:09:34 PM PDT 24 |
Jul 28 08:14:29 PM PDT 24 |
2442287520 ps |
| T1307 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3616093685 |
|
|
Jul 28 08:22:16 PM PDT 24 |
Jul 28 08:29:13 PM PDT 24 |
3641480184 ps |
| T1308 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1375267670 |
|
|
Jul 28 08:31:43 PM PDT 24 |
Jul 28 08:47:29 PM PDT 24 |
11668953838 ps |
| T1309 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1599420968 |
|
|
Jul 28 08:26:48 PM PDT 24 |
Jul 28 09:11:43 PM PDT 24 |
37138821372 ps |
| T311 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3015142783 |
|
|
Jul 28 08:36:46 PM PDT 24 |
Jul 28 08:42:51 PM PDT 24 |
3689610750 ps |
| T1310 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.533882620 |
|
|
Jul 28 08:36:23 PM PDT 24 |
Jul 28 08:41:58 PM PDT 24 |
3430003064 ps |
| T1311 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3003041015 |
|
|
Jul 28 08:27:12 PM PDT 24 |
Jul 28 08:39:29 PM PDT 24 |
3640523456 ps |
| T27 |
/workspace/coverage/default/1.chip_sw_gpio.2337809370 |
|
|
Jul 28 08:10:39 PM PDT 24 |
Jul 28 08:18:36 PM PDT 24 |
3330377414 ps |
| T1312 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.72472775 |
|
|
Jul 28 08:08:52 PM PDT 24 |
Jul 28 08:35:09 PM PDT 24 |
9348849482 ps |
| T1313 |
/workspace/coverage/default/1.chip_sw_hmac_smoketest.4196578491 |
|
|
Jul 28 08:19:15 PM PDT 24 |
Jul 28 08:25:42 PM PDT 24 |
3154999816 ps |
| T1314 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.150454507 |
|
|
Jul 28 08:11:06 PM PDT 24 |
Jul 28 08:50:24 PM PDT 24 |
10796230280 ps |
| T1315 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2425004721 |
|
|
Jul 28 08:25:02 PM PDT 24 |
Jul 28 09:00:34 PM PDT 24 |
9138507304 ps |
| T1316 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.813825999 |
|
|
Jul 28 08:11:17 PM PDT 24 |
Jul 28 08:37:03 PM PDT 24 |
7958116344 ps |
| T55 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.2073865619 |
|
|
Jul 28 08:22:41 PM PDT 24 |
Jul 28 08:29:40 PM PDT 24 |
4901259576 ps |
| T823 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.1214002031 |
|
|
Jul 28 08:39:13 PM PDT 24 |
Jul 28 08:48:04 PM PDT 24 |
4457692620 ps |
| T834 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.578862150 |
|
|
Jul 28 08:38:15 PM PDT 24 |
Jul 28 08:44:18 PM PDT 24 |
4222578368 ps |
| T1317 |
/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3006973706 |
|
|
Jul 28 08:14:16 PM PDT 24 |
Jul 28 08:19:26 PM PDT 24 |
3195755682 ps |
| T819 |
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1788453283 |
|
|
Jul 28 08:32:03 PM PDT 24 |
Jul 28 08:37:31 PM PDT 24 |
3612166330 ps |
| T717 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1567885269 |
|
|
Jul 28 08:27:17 PM PDT 24 |
Jul 28 08:40:21 PM PDT 24 |
5514138736 ps |
| T1318 |
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2245386044 |
|
|
Jul 28 08:31:31 PM PDT 24 |
Jul 28 09:49:59 PM PDT 24 |
22423315656 ps |
| T842 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.3727133102 |
|
|
Jul 28 08:36:20 PM PDT 24 |
Jul 28 08:44:23 PM PDT 24 |
4554272184 ps |
| T349 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1614188015 |
|
|
Jul 28 08:15:34 PM PDT 24 |
Jul 28 08:27:35 PM PDT 24 |
4237428600 ps |
| T1319 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2682031815 |
|
|
Jul 28 08:07:46 PM PDT 24 |
Jul 28 08:39:22 PM PDT 24 |
8460776140 ps |
| T1320 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter.651601515 |
|
|
Jul 28 08:18:20 PM PDT 24 |
Jul 28 08:22:14 PM PDT 24 |
2889941056 ps |
| T769 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.1306654235 |
|
|
Jul 28 08:32:20 PM PDT 24 |
Jul 28 08:42:14 PM PDT 24 |
5229976376 ps |
| T1321 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2191318070 |
|
|
Jul 28 08:29:57 PM PDT 24 |
Jul 28 08:40:54 PM PDT 24 |
4235774986 ps |
| T1322 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.308654133 |
|
|
Jul 28 08:10:34 PM PDT 24 |
Jul 28 08:24:28 PM PDT 24 |
5333388412 ps |
| T1323 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.538389281 |
|
|
Jul 28 08:26:37 PM PDT 24 |
Jul 28 09:05:08 PM PDT 24 |
12268102036 ps |
| T1324 |
/workspace/coverage/default/1.chip_sw_aes_idle.313982588 |
|
|
Jul 28 08:13:03 PM PDT 24 |
Jul 28 08:16:24 PM PDT 24 |
2505694200 ps |
| T794 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.237803987 |
|
|
Jul 28 08:33:28 PM PDT 24 |
Jul 28 08:44:32 PM PDT 24 |
6039126724 ps |
| T1325 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.3545931163 |
|
|
Jul 28 08:35:19 PM PDT 24 |
Jul 28 08:46:25 PM PDT 24 |
4792609284 ps |
| T1326 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3072221116 |
|
|
Jul 28 08:28:25 PM PDT 24 |
Jul 28 08:37:07 PM PDT 24 |
5512781206 ps |
| T839 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.3680922758 |
|
|
Jul 28 08:33:03 PM PDT 24 |
Jul 28 08:41:08 PM PDT 24 |
4650698482 ps |
| T1327 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3873122420 |
|
|
Jul 28 08:23:52 PM PDT 24 |
Jul 28 09:14:11 PM PDT 24 |
10756366229 ps |
| T1328 |
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1255357977 |
|
|
Jul 28 08:31:14 PM PDT 24 |
Jul 28 09:46:32 PM PDT 24 |
22143604856 ps |
| T1329 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2154020667 |
|
|
Jul 28 08:20:59 PM PDT 24 |
Jul 28 08:29:25 PM PDT 24 |
4129807152 ps |
| T1330 |
/workspace/coverage/default/1.chip_tap_straps_prod.513142031 |
|
|
Jul 28 08:17:30 PM PDT 24 |
Jul 28 08:53:31 PM PDT 24 |
19993672057 ps |
| T1331 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.56993095 |
|
|
Jul 28 08:33:36 PM PDT 24 |
Jul 28 09:03:16 PM PDT 24 |
8397583800 ps |
| T1332 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3474663178 |
|
|
Jul 28 08:27:52 PM PDT 24 |
Jul 28 08:47:27 PM PDT 24 |
5679525048 ps |
| T824 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3584309810 |
|
|
Jul 28 08:35:11 PM PDT 24 |
Jul 28 08:42:34 PM PDT 24 |
3934914840 ps |
| T378 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3727377188 |
|
|
Jul 28 08:33:59 PM PDT 24 |
Jul 28 08:39:50 PM PDT 24 |
3902816894 ps |
| T803 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.2230564489 |
|
|
Jul 28 08:35:24 PM PDT 24 |
Jul 28 08:42:56 PM PDT 24 |
4696017552 ps |
| T1333 |
/workspace/coverage/default/1.rom_e2e_smoke.1159667490 |
|
|
Jul 28 08:23:24 PM PDT 24 |
Jul 28 09:32:41 PM PDT 24 |
14991750606 ps |
| T1334 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.691247584 |
|
|
Jul 28 08:06:40 PM PDT 24 |
Jul 28 08:08:35 PM PDT 24 |
2734577061 ps |
| T188 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1806634225 |
|
|
Jul 28 08:21:58 PM PDT 24 |
Jul 28 08:33:28 PM PDT 24 |
4276036208 ps |
| T276 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.4270661260 |
|
|
Jul 28 08:30:41 PM PDT 24 |
Jul 28 08:47:51 PM PDT 24 |
5716592142 ps |
| T1335 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2153467285 |
|
|
Jul 28 08:37:15 PM PDT 24 |
Jul 28 08:45:20 PM PDT 24 |
3844572294 ps |
| T224 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2921940282 |
|
|
Jul 28 08:16:15 PM PDT 24 |
Jul 28 08:46:43 PM PDT 24 |
9269600200 ps |
| T1336 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3960431973 |
|
|
Jul 28 08:31:19 PM PDT 24 |
Jul 28 08:38:14 PM PDT 24 |
4494722447 ps |
| T807 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1726603601 |
|
|
Jul 28 08:35:28 PM PDT 24 |
Jul 28 08:40:50 PM PDT 24 |
3300646110 ps |
| T1337 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.3397405540 |
|
|
Jul 28 08:33:08 PM PDT 24 |
Jul 28 09:38:06 PM PDT 24 |
16351466880 ps |
| T1338 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1234314725 |
|
|
Jul 28 08:30:27 PM PDT 24 |
Jul 28 08:37:45 PM PDT 24 |
5571833530 ps |
| T1339 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1446629987 |
|
|
Jul 28 08:28:05 PM PDT 24 |
Jul 28 08:32:14 PM PDT 24 |
2742014891 ps |
| T1340 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3283793293 |
|
|
Jul 28 08:15:26 PM PDT 24 |
Jul 28 09:26:32 PM PDT 24 |
14990035908 ps |
| T1341 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3378010032 |
|
|
Jul 28 08:27:01 PM PDT 24 |
Jul 28 08:39:46 PM PDT 24 |
4363822520 ps |
| T141 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.701721791 |
|
|
Jul 28 08:25:04 PM PDT 24 |
Jul 28 08:36:50 PM PDT 24 |
4237760820 ps |
| T1342 |
/workspace/coverage/default/1.chip_sw_flash_crash_alert.2114632138 |
|
|
Jul 28 08:19:17 PM PDT 24 |
Jul 28 08:30:33 PM PDT 24 |
5949773970 ps |
| T767 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.660700651 |
|
|
Jul 28 08:37:14 PM PDT 24 |
Jul 28 08:48:00 PM PDT 24 |
4505120060 ps |
| T304 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1336936445 |
|
|
Jul 28 08:07:26 PM PDT 24 |
Jul 28 08:13:05 PM PDT 24 |
2484802072 ps |
| T1343 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.2743225384 |
|
|
Jul 28 08:23:16 PM PDT 24 |
Jul 28 09:21:12 PM PDT 24 |
14323973643 ps |
| T343 |
/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2323017709 |
|
|
Jul 28 08:09:57 PM PDT 24 |
Jul 28 08:19:16 PM PDT 24 |
4457833428 ps |
| T1344 |
/workspace/coverage/default/1.chip_sw_otbn_randomness.2967042351 |
|
|
Jul 28 08:14:16 PM PDT 24 |
Jul 28 08:27:49 PM PDT 24 |
5928476528 ps |
| T455 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.2437708393 |
|
|
Jul 28 08:10:52 PM PDT 24 |
Jul 28 08:45:16 PM PDT 24 |
25089576842 ps |
| T1345 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.750604134 |
|
|
Jul 28 08:19:27 PM PDT 24 |
Jul 28 08:34:30 PM PDT 24 |
4540196435 ps |
| T400 |
/workspace/coverage/default/0.chip_sw_alert_handler_entropy.1944339100 |
|
|
Jul 28 08:12:21 PM PDT 24 |
Jul 28 08:17:48 PM PDT 24 |
3085064273 ps |
| T1346 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.1987179772 |
|
|
Jul 28 08:09:47 PM PDT 24 |
Jul 28 08:15:47 PM PDT 24 |
3941175580 ps |
| T848 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2906635415 |
|
|
Jul 28 08:33:16 PM PDT 24 |
Jul 28 08:39:27 PM PDT 24 |
4010154690 ps |
| T456 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.3218416706 |
|
|
Jul 28 08:10:48 PM PDT 24 |
Jul 28 08:49:43 PM PDT 24 |
24363546449 ps |
| T328 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.931914832 |
|
|
Jul 28 08:26:42 PM PDT 24 |
Jul 28 08:45:57 PM PDT 24 |
6563488100 ps |
| T36 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3200722000 |
|
|
Jul 28 08:16:44 PM PDT 24 |
Jul 28 08:25:48 PM PDT 24 |
5768189650 ps |
| T840 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.2135601128 |
|
|
Jul 28 08:36:48 PM PDT 24 |
Jul 28 08:47:08 PM PDT 24 |
4877401632 ps |
| T1347 |
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1188099548 |
|
|
Jul 28 08:35:02 PM PDT 24 |
Jul 28 08:40:38 PM PDT 24 |
4082552984 ps |
| T1348 |
/workspace/coverage/default/0.chip_sw_aes_smoketest.2249062622 |
|
|
Jul 28 08:11:41 PM PDT 24 |
Jul 28 08:16:23 PM PDT 24 |
2796132872 ps |
| T1349 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3928279045 |
|
|
Jul 28 08:33:52 PM PDT 24 |
Jul 28 08:41:07 PM PDT 24 |
4130896100 ps |
| T1350 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3932433162 |
|
|
Jul 28 08:07:51 PM PDT 24 |
Jul 28 08:17:12 PM PDT 24 |
6882604312 ps |
| T33 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2451233270 |
|
|
Jul 28 08:06:52 PM PDT 24 |
Jul 28 08:11:29 PM PDT 24 |
2456135230 ps |
| T1351 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.1078922116 |
|
|
Jul 28 08:17:07 PM PDT 24 |
Jul 28 09:17:58 PM PDT 24 |
15439985557 ps |
| T797 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.502995106 |
|
|
Jul 28 08:34:40 PM PDT 24 |
Jul 28 08:45:04 PM PDT 24 |
5855216824 ps |
| T1352 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2116516724 |
|
|
Jul 28 08:12:18 PM PDT 24 |
Jul 28 09:16:51 PM PDT 24 |
16110411050 ps |
| T1353 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.989151065 |
|
|
Jul 28 08:28:33 PM PDT 24 |
Jul 28 09:31:13 PM PDT 24 |
21214218450 ps |
| T260 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.808213291 |
|
|
Jul 28 08:39:10 PM PDT 24 |
Jul 28 08:47:36 PM PDT 24 |
5891745016 ps |
| T155 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.339006908 |
|
|
Jul 28 08:09:39 PM PDT 24 |
Jul 28 08:19:42 PM PDT 24 |
4876348366 ps |
| T1354 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1321711466 |
|
|
Jul 28 08:08:33 PM PDT 24 |
Jul 28 08:41:43 PM PDT 24 |
21487725193 ps |
| T1355 |
/workspace/coverage/default/2.chip_sw_csrng_kat_test.3722610518 |
|
|
Jul 28 08:25:58 PM PDT 24 |
Jul 28 08:29:47 PM PDT 24 |
2593384772 ps |
| T1356 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2281406472 |
|
|
Jul 28 08:25:40 PM PDT 24 |
Jul 28 08:43:53 PM PDT 24 |
5519874078 ps |
| T63 |
/workspace/coverage/default/3.chip_tap_straps_testunlock0.3735154799 |
|
|
Jul 28 08:30:07 PM PDT 24 |
Jul 28 08:39:45 PM PDT 24 |
6393346560 ps |
| T1357 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1642788918 |
|
|
Jul 28 08:23:34 PM PDT 24 |
Jul 28 08:35:31 PM PDT 24 |
4540623080 ps |
| T1358 |
/workspace/coverage/default/0.chip_sw_aes_entropy.65298090 |
|
|
Jul 28 08:09:02 PM PDT 24 |
Jul 28 08:13:14 PM PDT 24 |
2641089764 ps |
| T1359 |
/workspace/coverage/default/3.chip_tap_straps_prod.1468466516 |
|
|
Jul 28 08:31:29 PM PDT 24 |
Jul 28 08:57:04 PM PDT 24 |
16076278910 ps |
| T373 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3578303246 |
|
|
Jul 28 08:06:57 PM PDT 24 |
Jul 28 08:14:01 PM PDT 24 |
6362669270 ps |
| T189 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.4274010518 |
|
|
Jul 28 08:10:56 PM PDT 24 |
Jul 28 08:24:25 PM PDT 24 |
6443698863 ps |
| T1360 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.704012038 |
|
|
Jul 28 08:16:44 PM PDT 24 |
Jul 28 08:28:52 PM PDT 24 |
5067590920 ps |
| T1361 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.1438768236 |
|
|
Jul 28 08:13:20 PM PDT 24 |
Jul 28 08:44:44 PM PDT 24 |
8819441146 ps |
| T1362 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.995072897 |
|
|
Jul 28 08:22:30 PM PDT 24 |
Jul 28 08:45:16 PM PDT 24 |
9527169152 ps |
| T312 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1079658981 |
|
|
Jul 28 08:30:38 PM PDT 24 |
Jul 28 08:39:11 PM PDT 24 |
4088889980 ps |
| T1363 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.2266618701 |
|
|
Jul 28 08:16:29 PM PDT 24 |
Jul 28 08:26:11 PM PDT 24 |
7505679192 ps |
| T56 |
/workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.4231763693 |
|
|
Jul 28 08:23:22 PM PDT 24 |
Jul 28 08:28:13 PM PDT 24 |
3111619827 ps |
| T1364 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.1596306361 |
|
|
Jul 28 08:19:33 PM PDT 24 |
Jul 28 08:23:45 PM PDT 24 |
2823351466 ps |
| T1365 |
/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.4061814577 |
|
|
Jul 28 08:20:25 PM PDT 24 |
Jul 28 08:26:26 PM PDT 24 |
2934454294 ps |
| T1366 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1326357953 |
|
|
Jul 28 08:20:58 PM PDT 24 |
Jul 28 08:25:49 PM PDT 24 |
2635971671 ps |
| T1367 |
/workspace/coverage/default/1.chip_sw_hmac_multistream.278453802 |
|
|
Jul 28 08:17:04 PM PDT 24 |
Jul 28 08:52:17 PM PDT 24 |
6539321128 ps |
| T1368 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3533368625 |
|
|
Jul 28 08:06:39 PM PDT 24 |
Jul 28 08:13:12 PM PDT 24 |
10111667705 ps |
| T1369 |
/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.681324905 |
|
|
Jul 28 08:26:06 PM PDT 24 |
Jul 28 08:35:11 PM PDT 24 |
5394155942 ps |
| T1370 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3872048435 |
|
|
Jul 28 08:18:43 PM PDT 24 |
Jul 28 08:41:14 PM PDT 24 |
9400384272 ps |
| T190 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1973482685 |
|
|
Jul 28 08:12:04 PM PDT 24 |
Jul 28 08:22:43 PM PDT 24 |
4407889802 ps |
| T811 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.1553451362 |
|
|
Jul 28 08:21:23 PM PDT 24 |
Jul 28 08:30:24 PM PDT 24 |
5623866910 ps |
| T1371 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1416988729 |
|
|
Jul 28 08:37:59 PM PDT 24 |
Jul 28 08:44:16 PM PDT 24 |
3670057464 ps |
| T1372 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.598489918 |
|
|
Jul 28 08:16:22 PM PDT 24 |
Jul 28 08:24:42 PM PDT 24 |
7802445023 ps |
| T1373 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.383548776 |
|
|
Jul 28 08:11:33 PM PDT 24 |
Jul 28 08:35:14 PM PDT 24 |
8944000932 ps |
| T833 |
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.796152030 |
|
|
Jul 28 08:35:46 PM PDT 24 |
Jul 28 08:42:16 PM PDT 24 |
3494209088 ps |
| T1374 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.726127849 |
|
|
Jul 28 08:13:52 PM PDT 24 |
Jul 28 08:56:55 PM PDT 24 |
21096102514 ps |
| T1375 |
/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2591624481 |
|
|
Jul 28 08:32:24 PM PDT 24 |
Jul 28 08:43:10 PM PDT 24 |
3824365750 ps |
| T1376 |
/workspace/coverage/default/2.chip_tap_straps_testunlock0.4734094 |
|
|
Jul 28 08:29:50 PM PDT 24 |
Jul 28 08:37:16 PM PDT 24 |
5487066337 ps |
| T91 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.4048497817 |
|
|
Jul 28 08:39:50 PM PDT 24 |
Jul 28 08:50:40 PM PDT 24 |
5850179326 ps |
| T1377 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3561315724 |
|
|
Jul 28 08:29:25 PM PDT 24 |
Jul 28 08:54:17 PM PDT 24 |
10186069942 ps |
| T1378 |
/workspace/coverage/default/1.chip_sw_power_idle_load.1720780136 |
|
|
Jul 28 08:21:18 PM PDT 24 |
Jul 28 08:32:29 PM PDT 24 |
4033725304 ps |
| T1379 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.4011281683 |
|
|
Jul 28 08:13:17 PM PDT 24 |
Jul 28 08:19:53 PM PDT 24 |
7510800696 ps |
| T805 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2756322082 |
|
|
Jul 28 08:38:17 PM PDT 24 |
Jul 28 08:42:55 PM PDT 24 |
3607037324 ps |
| T313 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.1964096369 |
|
|
Jul 28 08:39:01 PM PDT 24 |
Jul 28 08:46:53 PM PDT 24 |
5444847372 ps |
| T1380 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1082306474 |
|
|
Jul 28 08:38:04 PM PDT 24 |
Jul 28 08:44:27 PM PDT 24 |
3601642048 ps |
| T1381 |
/workspace/coverage/default/2.chip_sw_example_concurrency.4274967507 |
|
|
Jul 28 08:22:42 PM PDT 24 |
Jul 28 08:26:37 PM PDT 24 |
2910065128 ps |
| T1382 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.4011847128 |
|
|
Jul 28 08:08:22 PM PDT 24 |
Jul 28 08:25:58 PM PDT 24 |
6229410912 ps |
| T1383 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1373058746 |
|
|
Jul 28 08:13:38 PM PDT 24 |
Jul 28 08:25:43 PM PDT 24 |
9634443868 ps |
| T845 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.1363553620 |
|
|
Jul 28 08:32:00 PM PDT 24 |
Jul 28 08:41:34 PM PDT 24 |
5302509060 ps |
| T1384 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.564787127 |
|
|
Jul 28 08:20:31 PM PDT 24 |
Jul 28 08:29:05 PM PDT 24 |
9837492724 ps |
| T1385 |
/workspace/coverage/default/2.rom_e2e_static_critical.4120684622 |
|
|
Jul 28 08:32:59 PM PDT 24 |
Jul 28 09:31:22 PM PDT 24 |
17895372080 ps |
| T1386 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.641383049 |
|
|
Jul 28 08:37:15 PM PDT 24 |
Jul 28 08:44:12 PM PDT 24 |
4749567596 ps |
| T123 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2347736345 |
|
|
Jul 28 08:27:55 PM PDT 24 |
Jul 28 08:35:25 PM PDT 24 |
4714167000 ps |
| T1387 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1194206244 |
|
|
Jul 28 08:12:35 PM PDT 24 |
Jul 28 08:14:23 PM PDT 24 |
2361065952 ps |
| T1388 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3893326729 |
|
|
Jul 28 08:07:34 PM PDT 24 |
Jul 28 08:33:25 PM PDT 24 |
13032597896 ps |
| T363 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.968647997 |
|
|
Jul 28 08:28:50 PM PDT 24 |
Jul 28 08:40:38 PM PDT 24 |
5194567732 ps |
| T191 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1875197634 |
|
|
Jul 28 08:06:01 PM PDT 24 |
Jul 28 08:15:50 PM PDT 24 |
4599930619 ps |
| T1389 |
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1481556370 |
|
|
Jul 28 08:33:09 PM PDT 24 |
Jul 28 09:55:06 PM PDT 24 |
23677013586 ps |
| T1390 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.220404142 |
|
|
Jul 28 08:06:49 PM PDT 24 |
Jul 28 08:40:16 PM PDT 24 |
10614689000 ps |