| T1071 |
/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3882805399 |
|
|
Jul 28 08:20:06 PM PDT 24 |
Jul 28 08:31:33 PM PDT 24 |
4078916840 ps |
| T850 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.4038100944 |
|
|
Jul 28 08:33:44 PM PDT 24 |
Jul 28 08:43:21 PM PDT 24 |
5782301038 ps |
| T789 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.382217682 |
|
|
Jul 28 08:38:35 PM PDT 24 |
Jul 28 08:45:26 PM PDT 24 |
3879212354 ps |
| T1072 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1825541645 |
|
|
Jul 28 08:31:51 PM PDT 24 |
Jul 28 08:38:06 PM PDT 24 |
6703263492 ps |
| T1073 |
/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.3547351446 |
|
|
Jul 28 08:30:50 PM PDT 24 |
Jul 28 09:38:04 PM PDT 24 |
19951740096 ps |
| T82 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.2413972691 |
|
|
Jul 28 08:14:21 PM PDT 24 |
Jul 28 08:18:58 PM PDT 24 |
3042718029 ps |
| T785 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1098938789 |
|
|
Jul 28 08:38:35 PM PDT 24 |
Jul 28 08:46:01 PM PDT 24 |
3535641366 ps |
| T1074 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.515354569 |
|
|
Jul 28 08:07:27 PM PDT 24 |
Jul 28 08:11:54 PM PDT 24 |
3341464890 ps |
| T1075 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3334021260 |
|
|
Jul 28 08:14:12 PM PDT 24 |
Jul 28 09:07:37 PM PDT 24 |
15383515901 ps |
| T1076 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.3627927587 |
|
|
Jul 28 08:10:10 PM PDT 24 |
Jul 28 08:18:32 PM PDT 24 |
4218473904 ps |
| T1077 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access.2755322244 |
|
|
Jul 28 08:11:48 PM PDT 24 |
Jul 28 08:30:06 PM PDT 24 |
5853252626 ps |
| T1078 |
/workspace/coverage/default/0.chip_sw_otbn_randomness.1748425393 |
|
|
Jul 28 08:08:08 PM PDT 24 |
Jul 28 08:21:43 PM PDT 24 |
5915997700 ps |
| T1079 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.3909526864 |
|
|
Jul 28 08:30:15 PM PDT 24 |
Jul 28 08:35:29 PM PDT 24 |
2663381884 ps |
| T1080 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1262567463 |
|
|
Jul 28 08:27:38 PM PDT 24 |
Jul 28 08:32:18 PM PDT 24 |
2707507279 ps |
| T1081 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.4249178276 |
|
|
Jul 28 08:07:20 PM PDT 24 |
Jul 28 08:21:49 PM PDT 24 |
9574957000 ps |
| T1082 |
/workspace/coverage/default/2.chip_sw_example_rom.3615724000 |
|
|
Jul 28 08:19:54 PM PDT 24 |
Jul 28 08:22:01 PM PDT 24 |
2480885930 ps |
| T1083 |
/workspace/coverage/default/0.rom_e2e_static_critical.1623218532 |
|
|
Jul 28 08:15:17 PM PDT 24 |
Jul 28 09:20:05 PM PDT 24 |
16851342348 ps |
| T1084 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.773843152 |
|
|
Jul 28 08:24:16 PM PDT 24 |
Jul 28 08:34:52 PM PDT 24 |
5529713848 ps |
| T338 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.29532274 |
|
|
Jul 28 08:20:20 PM PDT 24 |
Jul 28 08:34:06 PM PDT 24 |
4833238648 ps |
| T1085 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.41167297 |
|
|
Jul 28 08:29:11 PM PDT 24 |
Jul 28 08:40:16 PM PDT 24 |
4662517180 ps |
| T806 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.1629574876 |
|
|
Jul 28 08:32:34 PM PDT 24 |
Jul 28 08:44:36 PM PDT 24 |
5563185332 ps |
| T1086 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.3419444118 |
|
|
Jul 28 08:10:06 PM PDT 24 |
Jul 28 08:15:14 PM PDT 24 |
3788819925 ps |
| T1087 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.25336646 |
|
|
Jul 28 08:12:21 PM PDT 24 |
Jul 28 08:25:01 PM PDT 24 |
5879549968 ps |
| T286 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.897728656 |
|
|
Jul 28 08:15:32 PM PDT 24 |
Jul 28 08:25:20 PM PDT 24 |
5763149169 ps |
| T1088 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.4176726662 |
|
|
Jul 28 08:07:35 PM PDT 24 |
Jul 28 08:12:18 PM PDT 24 |
3183554300 ps |
| T57 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.3308580163 |
|
|
Jul 28 08:06:22 PM PDT 24 |
Jul 28 08:12:00 PM PDT 24 |
3544776872 ps |
| T430 |
/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1339519471 |
|
|
Jul 28 08:07:04 PM PDT 24 |
Jul 28 08:15:56 PM PDT 24 |
4414594082 ps |
| T431 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.2652996390 |
|
|
Jul 28 08:24:34 PM PDT 24 |
Jul 28 08:30:07 PM PDT 24 |
3736480489 ps |
| T432 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2788991387 |
|
|
Jul 28 08:05:36 PM PDT 24 |
Jul 28 08:12:19 PM PDT 24 |
3466972408 ps |
| T433 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.71394044 |
|
|
Jul 28 08:33:40 PM PDT 24 |
Jul 28 08:44:37 PM PDT 24 |
5941173496 ps |
| T434 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.4136618636 |
|
|
Jul 28 08:36:56 PM PDT 24 |
Jul 28 08:39:43 PM PDT 24 |
3214234968 ps |
| T435 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.424449836 |
|
|
Jul 28 08:35:56 PM PDT 24 |
Jul 28 08:44:38 PM PDT 24 |
4365834070 ps |
| T436 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1344470135 |
|
|
Jul 28 08:15:49 PM PDT 24 |
Jul 28 08:27:03 PM PDT 24 |
5152640816 ps |
| T437 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.2363890867 |
|
|
Jul 28 08:36:23 PM PDT 24 |
Jul 28 08:47:44 PM PDT 24 |
5891770360 ps |
| T53 |
/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.2876379229 |
|
|
Jul 28 08:06:13 PM PDT 24 |
Jul 28 08:09:57 PM PDT 24 |
3575116634 ps |
| T1089 |
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2600366607 |
|
|
Jul 28 08:31:48 PM PDT 24 |
Jul 28 08:57:06 PM PDT 24 |
8982271180 ps |
| T1090 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.3759415109 |
|
|
Jul 28 08:26:01 PM PDT 24 |
Jul 28 08:44:06 PM PDT 24 |
6194240818 ps |
| T1091 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.754539339 |
|
|
Jul 28 08:29:57 PM PDT 24 |
Jul 28 08:35:36 PM PDT 24 |
2447255496 ps |
| T1092 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.943346660 |
|
|
Jul 28 08:17:43 PM PDT 24 |
Jul 28 08:36:52 PM PDT 24 |
6903891612 ps |
| T1093 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3111569027 |
|
|
Jul 28 08:11:23 PM PDT 24 |
Jul 28 08:41:19 PM PDT 24 |
8483845227 ps |
| T1094 |
/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.678091662 |
|
|
Jul 28 08:09:47 PM PDT 24 |
Jul 28 08:15:12 PM PDT 24 |
3142988606 ps |
| T1095 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1133508703 |
|
|
Jul 28 08:20:28 PM PDT 24 |
Jul 28 08:24:46 PM PDT 24 |
2683007234 ps |
| T801 |
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.512420414 |
|
|
Jul 28 08:38:32 PM PDT 24 |
Jul 28 08:46:31 PM PDT 24 |
4030886216 ps |
| T1096 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2134176105 |
|
|
Jul 28 08:31:21 PM PDT 24 |
Jul 28 08:59:07 PM PDT 24 |
8239983720 ps |
| T1097 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2880584152 |
|
|
Jul 28 08:31:52 PM PDT 24 |
Jul 28 08:46:18 PM PDT 24 |
9981818885 ps |
| T173 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1092600732 |
|
|
Jul 28 08:27:14 PM PDT 24 |
Jul 28 08:36:06 PM PDT 24 |
5623092169 ps |
| T174 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3659284845 |
|
|
Jul 28 08:16:02 PM PDT 24 |
Jul 28 08:35:51 PM PDT 24 |
9142325546 ps |
| T1098 |
/workspace/coverage/default/2.chip_sival_flash_info_access.1717230767 |
|
|
Jul 28 08:20:21 PM PDT 24 |
Jul 28 08:25:20 PM PDT 24 |
2412399440 ps |
| T1099 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1885184522 |
|
|
Jul 28 08:35:42 PM PDT 24 |
Jul 28 08:43:29 PM PDT 24 |
7101922730 ps |
| T714 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3384536407 |
|
|
Jul 28 08:17:38 PM PDT 24 |
Jul 28 09:46:38 PM PDT 24 |
24275265267 ps |
| T287 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.2232208482 |
|
|
Jul 28 08:21:59 PM PDT 24 |
Jul 28 08:35:48 PM PDT 24 |
4958254104 ps |
| T1100 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4071201064 |
|
|
Jul 28 08:10:06 PM PDT 24 |
Jul 28 08:21:29 PM PDT 24 |
4904951406 ps |
| T1101 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.2484639593 |
|
|
Jul 28 08:38:09 PM PDT 24 |
Jul 28 08:47:01 PM PDT 24 |
5551939040 ps |
| T348 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.4274166766 |
|
|
Jul 28 08:22:19 PM PDT 24 |
Jul 28 08:34:08 PM PDT 24 |
3503348616 ps |
| T1102 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3237755667 |
|
|
Jul 28 08:21:18 PM PDT 24 |
Jul 28 09:16:10 PM PDT 24 |
14864328402 ps |
| T1103 |
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3031116672 |
|
|
Jul 28 08:30:39 PM PDT 24 |
Jul 28 09:48:28 PM PDT 24 |
22237808740 ps |
| T1104 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.4028980837 |
|
|
Jul 28 08:17:25 PM PDT 24 |
Jul 28 09:15:04 PM PDT 24 |
15575218684 ps |
| T1105 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.2783834054 |
|
|
Jul 28 08:37:30 PM PDT 24 |
Jul 28 08:48:55 PM PDT 24 |
4952123412 ps |
| T796 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1243175637 |
|
|
Jul 28 08:33:33 PM PDT 24 |
Jul 28 08:39:04 PM PDT 24 |
3528950314 ps |
| T790 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2165309273 |
|
|
Jul 28 08:38:30 PM PDT 24 |
Jul 28 08:44:41 PM PDT 24 |
3931415946 ps |
| T1106 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2125594808 |
|
|
Jul 28 08:30:37 PM PDT 24 |
Jul 28 08:43:35 PM PDT 24 |
4707895968 ps |
| T1107 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3600922523 |
|
|
Jul 28 08:29:44 PM PDT 24 |
Jul 28 08:55:18 PM PDT 24 |
9261330360 ps |
| T817 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.2486727520 |
|
|
Jul 28 08:34:30 PM PDT 24 |
Jul 28 08:42:28 PM PDT 24 |
5324334876 ps |
| T54 |
/workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.3123335738 |
|
|
Jul 28 08:13:41 PM PDT 24 |
Jul 28 08:18:17 PM PDT 24 |
3277771047 ps |
| T837 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.543023414 |
|
|
Jul 28 08:31:21 PM PDT 24 |
Jul 28 08:37:50 PM PDT 24 |
4142458630 ps |
| T1108 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1156902654 |
|
|
Jul 28 08:10:56 PM PDT 24 |
Jul 28 08:14:09 PM PDT 24 |
2555438936 ps |
| T1109 |
/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.861035731 |
|
|
Jul 28 08:10:28 PM PDT 24 |
Jul 28 08:14:03 PM PDT 24 |
2898529056 ps |
| T844 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.2680856324 |
|
|
Jul 28 08:13:05 PM PDT 24 |
Jul 28 08:23:36 PM PDT 24 |
5091467752 ps |
| T1110 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.2313918803 |
|
|
Jul 28 08:15:20 PM PDT 24 |
Jul 28 09:48:41 PM PDT 24 |
23189225374 ps |
| T245 |
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1354738225 |
|
|
Jul 28 08:35:25 PM PDT 24 |
Jul 28 08:42:44 PM PDT 24 |
3878388200 ps |
| T1111 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.811346877 |
|
|
Jul 28 08:16:45 PM PDT 24 |
Jul 28 08:24:04 PM PDT 24 |
4164458464 ps |
| T1112 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3450818535 |
|
|
Jul 28 08:09:39 PM PDT 24 |
Jul 28 08:20:01 PM PDT 24 |
5917020732 ps |
| T1113 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access.388229088 |
|
|
Jul 28 08:21:59 PM PDT 24 |
Jul 28 08:39:04 PM PDT 24 |
5847692820 ps |
| T1114 |
/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3552525433 |
|
|
Jul 28 08:37:52 PM PDT 24 |
Jul 28 08:46:48 PM PDT 24 |
3656912400 ps |
| T1115 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3320004971 |
|
|
Jul 28 08:12:08 PM PDT 24 |
Jul 28 09:11:02 PM PDT 24 |
15203989810 ps |
| T306 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2732703278 |
|
|
Jul 28 08:08:55 PM PDT 24 |
Jul 28 08:14:17 PM PDT 24 |
5388887600 ps |
| T719 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.146545359 |
|
|
Jul 28 08:06:21 PM PDT 24 |
Jul 28 08:09:09 PM PDT 24 |
3326258210 ps |
| T192 |
/workspace/coverage/default/2.chip_jtag_mem_access.3689504777 |
|
|
Jul 28 08:19:23 PM PDT 24 |
Jul 28 08:43:24 PM PDT 24 |
13429333624 ps |
| T1116 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3169803527 |
|
|
Jul 28 08:09:09 PM PDT 24 |
Jul 28 08:30:43 PM PDT 24 |
6248119602 ps |
| T1117 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1492943954 |
|
|
Jul 28 08:13:14 PM PDT 24 |
Jul 28 09:42:35 PM PDT 24 |
18228131632 ps |
| T1118 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.3139287650 |
|
|
Jul 28 08:41:12 PM PDT 24 |
Jul 28 08:50:03 PM PDT 24 |
4916326740 ps |
| T375 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3009891162 |
|
|
Jul 28 08:38:51 PM PDT 24 |
Jul 28 08:45:02 PM PDT 24 |
3199895944 ps |
| T813 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3630504241 |
|
|
Jul 28 08:37:58 PM PDT 24 |
Jul 28 08:43:13 PM PDT 24 |
3280065704 ps |
| T1119 |
/workspace/coverage/default/1.rom_e2e_asm_init_dev.3068585687 |
|
|
Jul 28 08:23:55 PM PDT 24 |
Jul 28 09:25:17 PM PDT 24 |
15580774468 ps |
| T822 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2967490705 |
|
|
Jul 28 08:35:24 PM PDT 24 |
Jul 28 08:42:15 PM PDT 24 |
4476503112 ps |
| T1120 |
/workspace/coverage/default/0.chip_tap_straps_prod.4012820016 |
|
|
Jul 28 08:07:02 PM PDT 24 |
Jul 28 08:21:19 PM PDT 24 |
8397329485 ps |
| T1121 |
/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.3610418007 |
|
|
Jul 28 08:33:51 PM PDT 24 |
Jul 28 08:40:27 PM PDT 24 |
7163639930 ps |
| T1122 |
/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1409898125 |
|
|
Jul 28 08:29:26 PM PDT 24 |
Jul 28 08:38:47 PM PDT 24 |
4142386920 ps |
| T1123 |
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2515062745 |
|
|
Jul 28 08:21:29 PM PDT 24 |
Jul 28 08:45:09 PM PDT 24 |
8707555560 ps |
| T371 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.1447682215 |
|
|
Jul 28 08:22:19 PM PDT 24 |
Jul 28 11:42:01 PM PDT 24 |
63748936915 ps |
| T153 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.4014383758 |
|
|
Jul 28 08:28:36 PM PDT 24 |
Jul 28 08:39:35 PM PDT 24 |
4660341760 ps |
| T1124 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.710803364 |
|
|
Jul 28 08:14:28 PM PDT 24 |
Jul 28 08:29:33 PM PDT 24 |
5452788653 ps |
| T1125 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1232905124 |
|
|
Jul 28 08:08:20 PM PDT 24 |
Jul 28 08:51:40 PM PDT 24 |
26106104730 ps |
| T1126 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.1310862336 |
|
|
Jul 28 08:15:28 PM PDT 24 |
Jul 28 09:16:17 PM PDT 24 |
14129895975 ps |
| T1127 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2566118852 |
|
|
Jul 28 08:08:47 PM PDT 24 |
Jul 28 08:14:31 PM PDT 24 |
3123468986 ps |
| T1128 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.106603456 |
|
|
Jul 28 08:20:51 PM PDT 24 |
Jul 28 08:32:01 PM PDT 24 |
3775285896 ps |
| T68 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.3550856477 |
|
|
Jul 28 08:05:49 PM PDT 24 |
Jul 28 08:12:15 PM PDT 24 |
3592570626 ps |
| T1129 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.636557889 |
|
|
Jul 28 08:20:43 PM PDT 24 |
Jul 28 08:24:51 PM PDT 24 |
2765917380 ps |
| T100 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.920796570 |
|
|
Jul 28 08:08:32 PM PDT 24 |
Jul 28 08:39:33 PM PDT 24 |
20949316536 ps |
| T1130 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3997673610 |
|
|
Jul 28 08:24:30 PM PDT 24 |
Jul 28 08:45:17 PM PDT 24 |
7979906766 ps |
| T1131 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2935845820 |
|
|
Jul 28 08:30:14 PM PDT 24 |
Jul 28 08:51:08 PM PDT 24 |
8423951180 ps |
| T1132 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1484959536 |
|
|
Jul 28 08:26:15 PM PDT 24 |
Jul 28 08:30:55 PM PDT 24 |
3666088257 ps |
| T832 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.154440509 |
|
|
Jul 28 08:37:49 PM PDT 24 |
Jul 28 08:41:55 PM PDT 24 |
3895256692 ps |
| T288 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4244572931 |
|
|
Jul 28 08:28:00 PM PDT 24 |
Jul 28 08:40:59 PM PDT 24 |
5608251560 ps |
| T1133 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.789355327 |
|
|
Jul 28 08:24:17 PM PDT 24 |
Jul 28 08:32:15 PM PDT 24 |
3713158340 ps |
| T1134 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.3675250096 |
|
|
Jul 28 08:33:51 PM PDT 24 |
Jul 28 09:28:08 PM PDT 24 |
15158949939 ps |
| T49 |
/workspace/coverage/default/0.chip_sw_alert_test.353070962 |
|
|
Jul 28 08:08:10 PM PDT 24 |
Jul 28 08:12:32 PM PDT 24 |
3165924646 ps |
| T753 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_dev.3048574627 |
|
|
Jul 28 08:11:51 PM PDT 24 |
Jul 28 09:15:58 PM PDT 24 |
27278024181 ps |
| T1135 |
/workspace/coverage/default/1.chip_sw_aes_entropy.2690036509 |
|
|
Jul 28 08:13:41 PM PDT 24 |
Jul 28 08:19:59 PM PDT 24 |
3180269576 ps |
| T1136 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.4267950113 |
|
|
Jul 28 08:24:02 PM PDT 24 |
Jul 28 09:18:33 PM PDT 24 |
15565876716 ps |
| T1137 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2312300818 |
|
|
Jul 28 08:16:12 PM PDT 24 |
Jul 28 09:16:56 PM PDT 24 |
15413615000 ps |
| T1138 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1050807899 |
|
|
Jul 28 08:06:32 PM PDT 24 |
Jul 28 11:51:08 PM PDT 24 |
77990200987 ps |
| T66 |
/workspace/coverage/default/2.chip_tap_straps_rma.3103340418 |
|
|
Jul 28 08:29:06 PM PDT 24 |
Jul 28 08:34:53 PM PDT 24 |
3898797753 ps |
| T1139 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.3568553108 |
|
|
Jul 28 08:18:03 PM PDT 24 |
Jul 28 09:19:28 PM PDT 24 |
14993701644 ps |
| T1140 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1209569832 |
|
|
Jul 28 08:40:02 PM PDT 24 |
Jul 28 08:46:09 PM PDT 24 |
3446824000 ps |
| T47 |
/workspace/coverage/default/1.chip_jtag_csr_rw.1459372303 |
|
|
Jul 28 08:09:36 PM PDT 24 |
Jul 28 08:29:22 PM PDT 24 |
11286296588 ps |
| T324 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.1928488423 |
|
|
Jul 28 08:09:22 PM PDT 24 |
Jul 28 08:27:37 PM PDT 24 |
6457531712 ps |
| T228 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.778391961 |
|
|
Jul 28 08:22:22 PM PDT 24 |
Jul 28 09:49:23 PM PDT 24 |
47820096919 ps |
| T1141 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.1883095656 |
|
|
Jul 28 08:32:03 PM PDT 24 |
Jul 28 09:44:12 PM PDT 24 |
15377148328 ps |
| T225 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1673764917 |
|
|
Jul 28 08:16:03 PM PDT 24 |
Jul 28 09:24:41 PM PDT 24 |
15731518604 ps |
| T1142 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1256274765 |
|
|
Jul 28 08:14:27 PM PDT 24 |
Jul 28 09:13:37 PM PDT 24 |
14888530070 ps |
| T795 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.1758632282 |
|
|
Jul 28 08:33:25 PM PDT 24 |
Jul 28 08:45:34 PM PDT 24 |
5924215054 ps |
| T233 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2622846916 |
|
|
Jul 28 08:08:27 PM PDT 24 |
Jul 28 08:15:18 PM PDT 24 |
3645831496 ps |
| T1143 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2633394326 |
|
|
Jul 28 08:27:17 PM PDT 24 |
Jul 28 09:27:08 PM PDT 24 |
24339594742 ps |
| T1144 |
/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2859819822 |
|
|
Jul 28 08:25:26 PM PDT 24 |
Jul 28 09:27:32 PM PDT 24 |
14186606152 ps |
| T1145 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1286720775 |
|
|
Jul 28 08:30:13 PM PDT 24 |
Jul 28 08:44:09 PM PDT 24 |
5696991288 ps |
| T799 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.618246306 |
|
|
Jul 28 08:35:51 PM PDT 24 |
Jul 28 08:42:02 PM PDT 24 |
4132689400 ps |
| T1146 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.32651872 |
|
|
Jul 28 08:15:00 PM PDT 24 |
Jul 28 09:20:40 PM PDT 24 |
20088641726 ps |
| T1147 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.1720413747 |
|
|
Jul 28 08:23:37 PM PDT 24 |
Jul 28 08:28:05 PM PDT 24 |
2417851890 ps |
| T1148 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2177477760 |
|
|
Jul 28 08:08:16 PM PDT 24 |
Jul 28 08:17:30 PM PDT 24 |
3930115554 ps |
| T1149 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.151029286 |
|
|
Jul 28 08:07:59 PM PDT 24 |
Jul 28 08:12:46 PM PDT 24 |
3453645107 ps |
| T1150 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.1539788589 |
|
|
Jul 28 08:30:29 PM PDT 24 |
Jul 28 08:39:06 PM PDT 24 |
3679834256 ps |
| T1151 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1404878231 |
|
|
Jul 28 08:21:12 PM PDT 24 |
Jul 28 08:39:09 PM PDT 24 |
6345964867 ps |
| T1152 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2943853317 |
|
|
Jul 28 08:06:09 PM PDT 24 |
Jul 28 08:40:22 PM PDT 24 |
25075597144 ps |
| T1153 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.957983594 |
|
|
Jul 28 08:09:51 PM PDT 24 |
Jul 28 08:19:17 PM PDT 24 |
4780465900 ps |
| T1154 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.63135708 |
|
|
Jul 28 08:07:14 PM PDT 24 |
Jul 28 08:52:17 PM PDT 24 |
29711166548 ps |
| T1155 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.4073751768 |
|
|
Jul 28 08:16:24 PM PDT 24 |
Jul 28 09:20:37 PM PDT 24 |
14075737728 ps |
| T303 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3067937481 |
|
|
Jul 28 08:07:16 PM PDT 24 |
Jul 28 08:11:24 PM PDT 24 |
2716025451 ps |
| T750 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1230703256 |
|
|
Jul 28 08:14:26 PM PDT 24 |
Jul 28 08:27:44 PM PDT 24 |
4095178244 ps |
| T1156 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3018550647 |
|
|
Jul 28 08:11:02 PM PDT 24 |
Jul 28 08:15:01 PM PDT 24 |
2914334283 ps |
| T1157 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1671761563 |
|
|
Jul 28 08:26:41 PM PDT 24 |
Jul 28 09:11:58 PM PDT 24 |
10422912200 ps |
| T332 |
/workspace/coverage/default/2.chip_sw_entropy_src_csrng.2348961466 |
|
|
Jul 28 08:27:37 PM PDT 24 |
Jul 28 08:56:22 PM PDT 24 |
7505683516 ps |
| T1158 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.2697250343 |
|
|
Jul 28 08:14:29 PM PDT 24 |
Jul 28 08:19:45 PM PDT 24 |
2996762098 ps |
| T1159 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.989088183 |
|
|
Jul 28 08:13:03 PM PDT 24 |
Jul 28 09:20:25 PM PDT 24 |
15549718360 ps |
| T1160 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2227686345 |
|
|
Jul 28 08:12:13 PM PDT 24 |
Jul 28 09:52:01 PM PDT 24 |
49432475776 ps |
| T1161 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.284270640 |
|
|
Jul 28 08:24:18 PM PDT 24 |
Jul 28 08:31:05 PM PDT 24 |
5572203456 ps |
| T8 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3451791358 |
|
|
Jul 28 08:21:54 PM PDT 24 |
Jul 28 08:27:06 PM PDT 24 |
3115309848 ps |
| T1162 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2695469847 |
|
|
Jul 28 08:12:16 PM PDT 24 |
Jul 28 11:12:13 PM PDT 24 |
58426203576 ps |
| T1163 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.3102268992 |
|
|
Jul 28 08:06:55 PM PDT 24 |
Jul 28 09:35:39 PM PDT 24 |
27054214524 ps |
| T1164 |
/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1497263187 |
|
|
Jul 28 08:27:50 PM PDT 24 |
Jul 28 08:31:33 PM PDT 24 |
2655543736 ps |
| T1165 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.196809337 |
|
|
Jul 28 08:20:36 PM PDT 24 |
Jul 28 08:31:59 PM PDT 24 |
4186948992 ps |
| T1166 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.259664177 |
|
|
Jul 28 08:09:32 PM PDT 24 |
Jul 28 08:14:51 PM PDT 24 |
3427321167 ps |
| T768 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2025965199 |
|
|
Jul 28 08:34:09 PM PDT 24 |
Jul 28 08:42:54 PM PDT 24 |
4281816750 ps |
| T1167 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.463378528 |
|
|
Jul 28 08:13:49 PM PDT 24 |
Jul 28 08:20:18 PM PDT 24 |
3532207932 ps |
| T309 |
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2124876824 |
|
|
Jul 28 08:35:33 PM PDT 24 |
Jul 28 08:41:49 PM PDT 24 |
3635980052 ps |
| T417 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1094263128 |
|
|
Jul 28 08:07:40 PM PDT 24 |
Jul 28 08:34:10 PM PDT 24 |
24518143100 ps |
| T187 |
/workspace/coverage/default/2.chip_sw_power_virus.2507157175 |
|
|
Jul 28 08:37:00 PM PDT 24 |
Jul 28 08:59:52 PM PDT 24 |
5782636688 ps |
| T1168 |
/workspace/coverage/default/0.chip_sw_kmac_idle.1747129738 |
|
|
Jul 28 08:07:58 PM PDT 24 |
Jul 28 08:12:10 PM PDT 24 |
2928851692 ps |
| T787 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.200643165 |
|
|
Jul 28 08:39:17 PM PDT 24 |
Jul 28 08:47:16 PM PDT 24 |
5870119328 ps |
| T143 |
/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4012792765 |
|
|
Jul 28 08:13:19 PM PDT 24 |
Jul 28 11:31:48 PM PDT 24 |
256022916292 ps |
| T1169 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2062601739 |
|
|
Jul 28 08:30:30 PM PDT 24 |
Jul 28 09:18:09 PM PDT 24 |
13088328895 ps |
| T809 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.482829051 |
|
|
Jul 28 08:35:34 PM PDT 24 |
Jul 28 08:46:22 PM PDT 24 |
5071731432 ps |
| T816 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.1480488793 |
|
|
Jul 28 08:33:15 PM PDT 24 |
Jul 28 08:43:42 PM PDT 24 |
4819958248 ps |
| T1170 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.344863799 |
|
|
Jul 28 08:15:09 PM PDT 24 |
Jul 28 09:56:05 PM PDT 24 |
24092138860 ps |
| T259 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3351707907 |
|
|
Jul 28 08:09:46 PM PDT 24 |
Jul 28 08:17:20 PM PDT 24 |
5885405320 ps |
| T800 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3356097433 |
|
|
Jul 28 08:32:31 PM PDT 24 |
Jul 28 08:37:20 PM PDT 24 |
3350882360 ps |
| T1171 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.3500489340 |
|
|
Jul 28 08:06:56 PM PDT 24 |
Jul 28 08:17:12 PM PDT 24 |
6842678596 ps |
| T1172 |
/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3698550823 |
|
|
Jul 28 08:25:24 PM PDT 24 |
Jul 28 08:36:22 PM PDT 24 |
6834369750 ps |
| T1173 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.968162936 |
|
|
Jul 28 08:24:41 PM PDT 24 |
Jul 28 08:31:48 PM PDT 24 |
6170839276 ps |
| T1174 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.4014550654 |
|
|
Jul 28 08:23:45 PM PDT 24 |
Jul 28 09:21:35 PM PDT 24 |
15047541996 ps |
| T1175 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.3700947224 |
|
|
Jul 28 08:16:11 PM PDT 24 |
Jul 28 08:28:35 PM PDT 24 |
4106741100 ps |
| T1176 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2140972127 |
|
|
Jul 28 08:18:14 PM PDT 24 |
Jul 28 08:28:53 PM PDT 24 |
4426939906 ps |
| T1177 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1367315655 |
|
|
Jul 28 08:26:25 PM PDT 24 |
Jul 28 08:37:41 PM PDT 24 |
6844747112 ps |
| T1178 |
/workspace/coverage/default/2.chip_sw_kmac_idle.2538788188 |
|
|
Jul 28 08:25:41 PM PDT 24 |
Jul 28 08:30:36 PM PDT 24 |
2987134568 ps |
| T1179 |
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.553512407 |
|
|
Jul 28 08:30:11 PM PDT 24 |
Jul 28 08:42:08 PM PDT 24 |
5825921237 ps |
| T1180 |
/workspace/coverage/default/2.chip_sw_hmac_oneshot.3646491830 |
|
|
Jul 28 08:26:30 PM PDT 24 |
Jul 28 08:33:03 PM PDT 24 |
3086561984 ps |
| T1181 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4231756129 |
|
|
Jul 28 08:29:10 PM PDT 24 |
Jul 28 08:47:01 PM PDT 24 |
6757188955 ps |
| T229 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1394233149 |
|
|
Jul 28 08:06:02 PM PDT 24 |
Jul 28 09:34:15 PM PDT 24 |
47738077064 ps |
| T1182 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.2586710017 |
|
|
Jul 28 08:14:48 PM PDT 24 |
Jul 28 08:21:17 PM PDT 24 |
6980348648 ps |
| T1183 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.339886094 |
|
|
Jul 28 08:28:32 PM PDT 24 |
Jul 28 08:50:57 PM PDT 24 |
6895753594 ps |
| T841 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.404187830 |
|
|
Jul 28 08:38:54 PM PDT 24 |
Jul 28 08:45:57 PM PDT 24 |
3454405858 ps |
| T1184 |
/workspace/coverage/default/2.chip_sw_example_flash.3869577874 |
|
|
Jul 28 08:22:21 PM PDT 24 |
Jul 28 08:27:09 PM PDT 24 |
3357512630 ps |
| T1185 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2669066876 |
|
|
Jul 28 08:26:27 PM PDT 24 |
Jul 28 08:35:52 PM PDT 24 |
7195862936 ps |
| T354 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.2101586440 |
|
|
Jul 28 08:12:06 PM PDT 24 |
Jul 28 08:17:33 PM PDT 24 |
2828158314 ps |
| T1186 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1407178243 |
|
|
Jul 28 08:06:54 PM PDT 24 |
Jul 28 08:20:56 PM PDT 24 |
6544748636 ps |
| T39 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.3243616693 |
|
|
Jul 28 08:07:16 PM PDT 24 |
Jul 28 08:14:43 PM PDT 24 |
3985025076 ps |
| T1187 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.1453253675 |
|
|
Jul 28 08:39:43 PM PDT 24 |
Jul 28 08:51:04 PM PDT 24 |
5235619444 ps |
| T1188 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3071366916 |
|
|
Jul 28 08:10:23 PM PDT 24 |
Jul 28 08:22:32 PM PDT 24 |
4648760960 ps |
| T1189 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3522869005 |
|
|
Jul 28 08:10:05 PM PDT 24 |
Jul 28 08:28:14 PM PDT 24 |
5262876560 ps |
| T1190 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.622328471 |
|
|
Jul 28 08:21:23 PM PDT 24 |
Jul 28 08:30:16 PM PDT 24 |
4139785600 ps |
| T1191 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3376990815 |
|
|
Jul 28 08:23:18 PM PDT 24 |
Jul 28 09:07:20 PM PDT 24 |
24972058878 ps |
| T735 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.2867555816 |
|
|
Jul 28 08:09:37 PM PDT 24 |
Jul 28 08:15:12 PM PDT 24 |
3326189268 ps |
| T544 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1931096446 |
|
|
Jul 28 08:16:48 PM PDT 24 |
Jul 28 08:27:58 PM PDT 24 |
5623851400 ps |
| T1192 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1612954954 |
|
|
Jul 28 08:09:13 PM PDT 24 |
Jul 28 08:22:58 PM PDT 24 |
4058955000 ps |
| T1193 |
/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.3791871212 |
|
|
Jul 28 08:06:28 PM PDT 24 |
Jul 28 08:18:51 PM PDT 24 |
6881336556 ps |
| T716 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.4071554587 |
|
|
Jul 28 08:18:53 PM PDT 24 |
Jul 28 08:27:49 PM PDT 24 |
3859682259 ps |
| T826 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.859662798 |
|
|
Jul 28 08:36:41 PM PDT 24 |
Jul 28 08:50:18 PM PDT 24 |
4722412738 ps |
| T1194 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.665175267 |
|
|
Jul 28 08:09:15 PM PDT 24 |
Jul 28 09:11:04 PM PDT 24 |
24752452053 ps |
| T1195 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4256421575 |
|
|
Jul 28 08:12:15 PM PDT 24 |
Jul 28 08:36:38 PM PDT 24 |
15656352831 ps |
| T1196 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1088421470 |
|
|
Jul 28 08:19:03 PM PDT 24 |
Jul 28 08:34:53 PM PDT 24 |
7264517279 ps |
| T1197 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.4047726613 |
|
|
Jul 28 08:21:24 PM PDT 24 |
Jul 28 09:34:53 PM PDT 24 |
14817371820 ps |
| T1198 |
/workspace/coverage/default/2.chip_sw_hmac_multistream.1379490325 |
|
|
Jul 28 08:25:27 PM PDT 24 |
Jul 28 08:52:40 PM PDT 24 |
8551855516 ps |
| T814 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.1756282078 |
|
|
Jul 28 08:39:46 PM PDT 24 |
Jul 28 08:47:48 PM PDT 24 |
4097267420 ps |
| T1199 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2050156489 |
|
|
Jul 28 08:24:14 PM PDT 24 |
Jul 28 08:35:33 PM PDT 24 |
19589748034 ps |
| T52 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.2117052186 |
|
|
Jul 28 08:06:15 PM PDT 24 |
Jul 28 08:10:21 PM PDT 24 |
2858603738 ps |
| T1200 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.989364658 |
|
|
Jul 28 08:13:34 PM PDT 24 |
Jul 28 08:22:59 PM PDT 24 |
4588052808 ps |
| T121 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1170240848 |
|
|
Jul 28 08:09:51 PM PDT 24 |
Jul 28 08:17:42 PM PDT 24 |
5676192790 ps |
| T1201 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.64276512 |
|
|
Jul 28 08:18:37 PM PDT 24 |
Jul 28 09:06:07 PM PDT 24 |
11179882940 ps |
| T1202 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.816699288 |
|
|
Jul 28 08:27:48 PM PDT 24 |
Jul 28 09:19:43 PM PDT 24 |
15288436044 ps |
| T295 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.3770412825 |
|
|
Jul 28 08:34:40 PM PDT 24 |
Jul 28 08:42:08 PM PDT 24 |
4896564436 ps |
| T1203 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2207988641 |
|
|
Jul 28 08:06:40 PM PDT 24 |
Jul 28 08:11:03 PM PDT 24 |
2525829479 ps |
| T1204 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3452000622 |
|
|
Jul 28 08:29:43 PM PDT 24 |
Jul 28 08:34:29 PM PDT 24 |
3075261074 ps |
| T1205 |
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.4212505191 |
|
|
Jul 28 08:31:30 PM PDT 24 |
Jul 28 09:48:36 PM PDT 24 |
22465918484 ps |
| T1206 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3638578735 |
|
|
Jul 28 08:15:27 PM PDT 24 |
Jul 28 08:25:20 PM PDT 24 |
5965741786 ps |
| T1207 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.1941787764 |
|
|
Jul 28 08:20:00 PM PDT 24 |
Jul 28 08:24:09 PM PDT 24 |
2608399384 ps |
| T1208 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.4148388773 |
|
|
Jul 28 08:10:47 PM PDT 24 |
Jul 28 08:29:02 PM PDT 24 |
6079194100 ps |
| T1209 |
/workspace/coverage/default/3.chip_tap_straps_dev.3381022084 |
|
|
Jul 28 08:29:37 PM PDT 24 |
Jul 28 08:34:33 PM PDT 24 |
3717931143 ps |
| T1210 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.3206325459 |
|
|
Jul 28 08:24:33 PM PDT 24 |
Jul 28 08:29:52 PM PDT 24 |
3856792320 ps |
| T1211 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.390111027 |
|
|
Jul 28 08:10:39 PM PDT 24 |
Jul 28 08:15:01 PM PDT 24 |
2859170564 ps |
| T122 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.515457394 |
|
|
Jul 28 08:20:49 PM PDT 24 |
Jul 28 08:29:15 PM PDT 24 |
5164663180 ps |
| T1212 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1744200177 |
|
|
Jul 28 08:25:53 PM PDT 24 |
Jul 28 08:31:21 PM PDT 24 |
3480779286 ps |
| T9 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3534948180 |
|
|
Jul 28 08:09:18 PM PDT 24 |
Jul 28 08:15:38 PM PDT 24 |
3471146255 ps |
| T50 |
/workspace/coverage/default/1.chip_sw_alert_test.2450645308 |
|
|
Jul 28 08:17:21 PM PDT 24 |
Jul 28 08:21:36 PM PDT 24 |
3368521800 ps |
| T818 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.517685811 |
|
|
Jul 28 08:36:20 PM PDT 24 |
Jul 28 08:47:21 PM PDT 24 |
5046553120 ps |
| T1213 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3351145706 |
|
|
Jul 28 08:20:21 PM PDT 24 |
Jul 28 08:25:52 PM PDT 24 |
3108623065 ps |
| T720 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.3006595609 |
|
|
Jul 28 08:22:47 PM PDT 24 |
Jul 28 08:24:41 PM PDT 24 |
2363647687 ps |
| T1214 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.131566206 |
|
|
Jul 28 08:36:25 PM PDT 24 |
Jul 28 08:44:28 PM PDT 24 |
5027151768 ps |
| T376 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3623066091 |
|
|
Jul 28 08:38:52 PM PDT 24 |
Jul 28 08:45:15 PM PDT 24 |
4094521978 ps |
| T1215 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1775510846 |
|
|
Jul 28 08:33:00 PM PDT 24 |
Jul 28 09:28:43 PM PDT 24 |
15128597584 ps |
| T1216 |
/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.2069986990 |
|
|
Jul 28 08:32:50 PM PDT 24 |
Jul 28 08:43:11 PM PDT 24 |
4319124772 ps |
| T1217 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3539929052 |
|
|
Jul 28 08:26:48 PM PDT 24 |
Jul 28 08:30:49 PM PDT 24 |
2531992503 ps |
| T1218 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.968663959 |
|
|
Jul 28 08:27:06 PM PDT 24 |
Jul 28 08:34:15 PM PDT 24 |
4201025852 ps |
| T1219 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.3390354626 |
|
|
Jul 28 08:19:07 PM PDT 24 |
Jul 28 08:24:18 PM PDT 24 |
3251071672 ps |
| T798 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.4060554692 |
|
|
Jul 28 08:38:20 PM PDT 24 |
Jul 28 08:44:39 PM PDT 24 |
3564546040 ps |
| T1220 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.1762937392 |
|
|
Jul 28 08:16:43 PM PDT 24 |
Jul 28 08:34:07 PM PDT 24 |
7733101896 ps |
| T762 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.716585427 |
|
|
Jul 28 08:38:01 PM PDT 24 |
Jul 28 08:46:50 PM PDT 24 |
5042761356 ps |
| T1221 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3595366915 |
|
|
Jul 28 08:25:24 PM PDT 24 |
Jul 28 08:31:53 PM PDT 24 |
2991093024 ps |
| T1222 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.1439372759 |
|
|
Jul 28 08:13:51 PM PDT 24 |
Jul 28 08:37:35 PM PDT 24 |
8088746878 ps |
| T1223 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2259314341 |
|
|
Jul 28 08:25:12 PM PDT 24 |
Jul 28 08:38:41 PM PDT 24 |
5024521136 ps |
| T411 |
/workspace/coverage/default/1.chip_sw_kmac_app_rom.3716518802 |
|
|
Jul 28 08:15:40 PM PDT 24 |
Jul 28 08:19:11 PM PDT 24 |
2688323648 ps |
| T1224 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.1512818909 |
|
|
Jul 28 08:16:52 PM PDT 24 |
Jul 28 08:39:24 PM PDT 24 |
11950661150 ps |
| T1225 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3035119295 |
|
|
Jul 28 08:14:31 PM PDT 24 |
Jul 28 08:23:38 PM PDT 24 |
4097537190 ps |
| T1226 |
/workspace/coverage/default/0.chip_sw_coremark.2691312382 |
|
|
Jul 28 08:10:19 PM PDT 24 |
Jul 29 12:27:50 AM PDT 24 |
72002987240 ps |
| T111 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.436245665 |
|
|
Jul 28 08:20:17 PM PDT 24 |
Jul 28 10:42:28 PM PDT 24 |
54035782792 ps |
| T1227 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.299997513 |
|
|
Jul 28 08:33:21 PM PDT 24 |
Jul 28 09:25:40 PM PDT 24 |
14804200840 ps |
| T1228 |
/workspace/coverage/default/1.chip_sw_example_flash.3322365046 |
|
|
Jul 28 08:11:31 PM PDT 24 |
Jul 28 08:14:47 PM PDT 24 |
2689435054 ps |
| T1229 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3071078838 |
|
|
Jul 28 08:30:19 PM PDT 24 |
Jul 28 08:40:17 PM PDT 24 |
4243187340 ps |
| T226 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.867685271 |
|
|
Jul 28 08:13:29 PM PDT 24 |
Jul 28 09:17:55 PM PDT 24 |
14343279940 ps |
| T802 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.3358063346 |
|
|
Jul 28 08:35:01 PM PDT 24 |
Jul 28 08:47:51 PM PDT 24 |
5482338304 ps |
| T1230 |
/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1887648728 |
|
|
Jul 28 08:08:45 PM PDT 24 |
Jul 28 08:14:58 PM PDT 24 |
3257053260 ps |