Line Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Module :
prim_fifo_sync
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
188173774 |
0 |
0 |
T1 |
4229030 |
33930 |
0 |
0 |
T2 |
1282370 |
35258 |
0 |
0 |
T3 |
2788560 |
102740 |
0 |
0 |
T4 |
7573340 |
2057368 |
0 |
0 |
T5 |
6541570 |
253685 |
0 |
0 |
T6 |
2497350 |
63697 |
0 |
0 |
T7 |
559980 |
0 |
0 |
0 |
T8 |
1555110 |
699183 |
0 |
0 |
T43 |
0 |
125791 |
0 |
0 |
T80 |
2080160 |
54001 |
0 |
0 |
T81 |
1626240 |
52630 |
0 |
0 |
T195 |
0 |
54 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
4229030 |
4228450 |
0 |
0 |
T2 |
1282370 |
1281310 |
0 |
0 |
T3 |
2788560 |
2787360 |
0 |
0 |
T4 |
7573340 |
7573230 |
0 |
0 |
T5 |
6541570 |
6541020 |
0 |
0 |
T6 |
2497350 |
2495180 |
0 |
0 |
T7 |
559980 |
558810 |
0 |
0 |
T8 |
1555110 |
1554990 |
0 |
0 |
T80 |
2080160 |
2079000 |
0 |
0 |
T81 |
1626240 |
1625690 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
4229030 |
4228450 |
0 |
0 |
T2 |
1282370 |
1281310 |
0 |
0 |
T3 |
2788560 |
2787360 |
0 |
0 |
T4 |
7573340 |
7573230 |
0 |
0 |
T5 |
6541570 |
6541020 |
0 |
0 |
T6 |
2497350 |
2495180 |
0 |
0 |
T7 |
559980 |
558810 |
0 |
0 |
T8 |
1555110 |
1554990 |
0 |
0 |
T80 |
2080160 |
2079000 |
0 |
0 |
T81 |
1626240 |
1625690 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
4229030 |
4228450 |
0 |
0 |
T2 |
1282370 |
1281310 |
0 |
0 |
T3 |
2788560 |
2787360 |
0 |
0 |
T4 |
7573340 |
7573230 |
0 |
0 |
T5 |
6541570 |
6541020 |
0 |
0 |
T6 |
2497350 |
2495180 |
0 |
0 |
T7 |
559980 |
558810 |
0 |
0 |
T8 |
1555110 |
1554990 |
0 |
0 |
T80 |
2080160 |
2079000 |
0 |
0 |
T81 |
1626240 |
1625690 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
21734 |
21734 |
0 |
0 |
T1 |
10 |
10 |
0 |
0 |
T2 |
10 |
10 |
0 |
0 |
T3 |
10 |
10 |
0 |
0 |
T4 |
10 |
10 |
0 |
0 |
T5 |
10 |
10 |
0 |
0 |
T6 |
10 |
10 |
0 |
0 |
T7 |
10 |
10 |
0 |
0 |
T8 |
10 |
10 |
0 |
0 |
T80 |
10 |
10 |
0 |
0 |
T81 |
10 |
10 |
0 |
0 |