Module Definition
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Line Coverage for Module : prim_fifo_sync
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 188173774 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_passthru_fifo.paramCheckPass 21734 21734 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 188173774 0 0
T1 4229030 33930 0 0
T2 1282370 35258 0 0
T3 2788560 102740 0 0
T4 7573340 2057368 0 0
T5 6541570 253685 0 0
T6 2497350 63697 0 0
T7 559980 0 0 0
T8 1555110 699183 0 0
T43 0 125791 0 0
T80 2080160 54001 0 0
T81 1626240 52630 0 0
T195 0 54 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4229030 4228450 0 0
T2 1282370 1281310 0 0
T3 2788560 2787360 0 0
T4 7573340 7573230 0 0
T5 6541570 6541020 0 0
T6 2497350 2495180 0 0
T7 559980 558810 0 0
T8 1555110 1554990 0 0
T80 2080160 2079000 0 0
T81 1626240 1625690 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4229030 4228450 0 0
T2 1282370 1281310 0 0
T3 2788560 2787360 0 0
T4 7573340 7573230 0 0
T5 6541570 6541020 0 0
T6 2497350 2495180 0 0
T7 559980 558810 0 0
T8 1555110 1554990 0 0
T80 2080160 2079000 0 0
T81 1626240 1625690 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 4229030 4228450 0 0
T2 1282370 1281310 0 0
T3 2788560 2787360 0 0
T4 7573340 7573230 0 0
T5 6541570 6541020 0 0
T6 2497350 2495180 0 0
T7 559980 558810 0 0
T8 1555110 1554990 0 0
T80 2080160 2079000 0 0
T81 1626240 1625690 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 21734 21734 0 0
T1 10 10 0 0
T2 10 10 0 0
T3 10 10 0 0
T4 10 10 0 0
T5 10 10 0 0
T6 10 10 0 0
T7 10 10 0 0
T8 10 10 0 0
T80 10 10 0 0
T81 10 10 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%