Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522076652	60589267	0	0
DepthKnown_A	522076652	521967428	0	0
RvalidKnown_A	522076652	521967428	0	0
WreadyKnown_A	522076652	521967428	0	0
gen_passthru_fifo.paramCheckPass	1028	1028	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	60589267	0	0
T1	422903	11797	0	0
T2	128237	12179	0	0
T3	278856	36845	0	0
T4	757334	486814	0	0
T5	654157	58003	0	0
T6	249735	22049	0	0
T7	55998	0	0	0
T8	155511	175021	0	0
T43	0	72245	0	0
T80	208016	18778	0	0
T81	162624	20470	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	521967428	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	521967428	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	521967428	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522076652	46702212	0	0
DepthKnown_A	522076652	521967428	0	0
RvalidKnown_A	522076652	521967428	0	0
WreadyKnown_A	522076652	521967428	0	0
gen_passthru_fifo.paramCheckPass	1028	1028	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	46702212	0	0
T1	422903	8946	0	0
T2	128237	8856	0	0
T3	278856	27122	0	0
T4	757334	481155	0	0
T5	654157	54079	0	0
T6	249735	16313	0	0
T7	55998	0	0	0
T8	155511	156922	0	0
T43	0	36780	0	0
T80	208016	14590	0	0
T81	162624	17937	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	521967428	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	521967428	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	521967428	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522076652	43807054	0	0
DepthKnown_A	522076652	521967428	0	0
RvalidKnown_A	522076652	521967428	0	0
WreadyKnown_A	522076652	521967428	0	0
gen_passthru_fifo.paramCheckPass	1028	1028	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	43807054	0	0
T1	422903	6656	0	0
T2	128237	7174	0	0
T3	278856	19279	0	0
T4	757334	545257	0	0
T5	654157	70798	0	0
T6	249735	12774	0	0
T7	55998	0	0	0
T8	155511	212821	0	0
T43	0	9138	0	0
T80	208016	10361	0	0
T81	162624	7104	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	521967428	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	521967428	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	521967428	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522076652	36704795	0	0
DepthKnown_A	522076652	521967428	0	0
RvalidKnown_A	522076652	521967428	0	0
WreadyKnown_A	522076652	521967428	0	0
gen_passthru_fifo.paramCheckPass	1028	1028	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	36704795	0	0
T1	422903	6483	0	0
T2	128237	6945	0	0
T3	278856	18890	0	0
T4	757334	543902	0	0
T5	654157	70593	0	0
T6	249735	12365	0	0
T7	55998	0	0	0
T8	155511	154223	0	0
T43	0	7488	0	0
T80	208016	10096	0	0
T81	162624	6927	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	521967428	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	521967428	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	521967428	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	592562647	90818	0	0
DepthKnown_A	592562647	592437812	0	0
RvalidKnown_A	592562647	592437812	0	0
WreadyKnown_A	592562647	592437812	0	0
gen_passthru_fifo.paramCheckPass	2937	2937	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592562647	90818	0	0
T1	422903	12	0	0
T2	128237	26	0	0
T3	278856	151	0	0
T4	757334	60	0	0
T5	654157	53	0	0
T6	249735	49	0	0
T7	55998	0	0	0
T8	155511	49	0	0
T43	0	35	0	0
T80	208016	44	0	0
T81	162624	48	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592562647	592437812	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592562647	592437812	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592562647	592437812	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2937	2937	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	592562647	94405	0	0
DepthKnown_A	592562647	592437812	0	0
RvalidKnown_A	592562647	592437812	0	0
WreadyKnown_A	592562647	592437812	0	0
gen_passthru_fifo.paramCheckPass	2937	2937	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592562647	94405	0	0
T1	422903	12	0	0
T2	128237	26	0	0
T3	278856	151	0	0
T4	757334	60	0	0
T5	654157	53	0	0
T6	249735	49	0	0
T7	55998	0	0	0
T8	155511	49	0	0
T43	0	35	0	0
T80	208016	44	0	0
T81	162624	48	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592562647	592437812	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592562647	592437812	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592562647	592437812	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2937	2937	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	592562647	53974	0	0
DepthKnown_A	592562647	592437812	0	0
RvalidKnown_A	592562647	592437812	0	0
WreadyKnown_A	592562647	592437812	0	0
gen_passthru_fifo.paramCheckPass	2937	2937	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592562647	53974	0	0
T1	422903	11	0	0
T2	128237	24	0	0
T3	278856	95	0	0
T4	757334	58	0	0
T5	654157	52	0	0
T6	249735	46	0	0
T7	55998	0	0	0
T8	155511	0	0	0
T43	0	35	0	0
T80	208016	42	0	0
T81	162624	47	0	0
T195	0	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592562647	592437812	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592562647	592437812	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592562647	592437812	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2937	2937	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	592562647	53974	0	0
DepthKnown_A	592562647	592437812	0	0
RvalidKnown_A	592562647	592437812	0	0
WreadyKnown_A	592562647	592437812	0	0
gen_passthru_fifo.paramCheckPass	2937	2937	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592562647	53974	0	0
T1	422903	11	0	0
T2	128237	24	0	0
T3	278856	95	0	0
T4	757334	58	0	0
T5	654157	52	0	0
T6	249735	46	0	0
T7	55998	0	0	0
T8	155511	0	0	0
T43	0	35	0	0
T80	208016	42	0	0
T81	162624	47	0	0
T195	0	25	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592562647	592437812	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592562647	592437812	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592562647	592437812	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2937	2937	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	592562647	36844	0	0
DepthKnown_A	592562647	592437812	0	0
RvalidKnown_A	592562647	592437812	0	0
WreadyKnown_A	592562647	592437812	0	0
gen_passthru_fifo.paramCheckPass	2937	2937	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592562647	36844	0	0
T1	422903	1	0	0
T2	128237	2	0	0
T3	278856	56	0	0
T4	757334	2	0	0
T5	654157	1	0	0
T6	249735	3	0	0
T7	55998	0	0	0
T8	155511	49	0	0
T80	208016	2	0	0
T81	162624	1	0	0
T195	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592562647	592437812	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592562647	592437812	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592562647	592437812	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2937	2937	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	592562647	40431	0	0
DepthKnown_A	592562647	592437812	0	0
RvalidKnown_A	592562647	592437812	0	0
WreadyKnown_A	592562647	592437812	0	0
gen_passthru_fifo.paramCheckPass	2937	2937	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592562647	40431	0	0
T1	422903	1	0	0
T2	128237	2	0	0
T3	278856	56	0	0
T4	757334	2	0	0
T5	654157	1	0	0
T6	249735	3	0	0
T7	55998	0	0	0
T8	155511	49	0	0
T80	208016	2	0	0
T81	162624	1	0	0
T195	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592562647	592437812	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592562647	592437812	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592562647	592437812	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2937	2937	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0