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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.15 95.49 94.05 95.34 94.90 97.53 99.61


Total test records in report: 2935
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T1013 /workspace/coverage/default/0.rom_e2e_static_critical.3743223108 Aug 01 08:21:15 PM PDT 24 Aug 01 09:29:05 PM PDT 24 17160612168 ps
T1014 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3236119832 Aug 01 08:20:18 PM PDT 24 Aug 01 08:27:23 PM PDT 24 3707870600 ps
T29 /workspace/coverage/default/0.chip_sw_gpio.3577168072 Aug 01 08:14:18 PM PDT 24 Aug 01 08:22:22 PM PDT 24 3914139768 ps
T754 /workspace/coverage/default/57.chip_sw_all_escalation_resets.1052864630 Aug 01 08:48:30 PM PDT 24 Aug 01 08:57:00 PM PDT 24 5662118588 ps
T1015 /workspace/coverage/default/0.chip_sw_kmac_idle.3397406753 Aug 01 08:22:38 PM PDT 24 Aug 01 08:25:43 PM PDT 24 3234872408 ps
T224 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.333265549 Aug 01 08:34:24 PM PDT 24 Aug 01 09:29:14 PM PDT 24 20405046052 ps
T1016 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1260196392 Aug 01 08:20:44 PM PDT 24 Aug 01 08:38:37 PM PDT 24 8961241750 ps
T111 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1008425463 Aug 01 08:29:58 PM PDT 24 Aug 01 08:55:39 PM PDT 24 23911189608 ps
T1017 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.349178297 Aug 01 08:13:35 PM PDT 24 Aug 01 08:16:58 PM PDT 24 2451219047 ps
T1018 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3878861574 Aug 01 08:28:37 PM PDT 24 Aug 01 08:49:43 PM PDT 24 9821316104 ps
T247 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.4073047542 Aug 01 08:21:14 PM PDT 24 Aug 01 08:29:48 PM PDT 24 4287007500 ps
T1019 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2598478657 Aug 01 08:14:52 PM PDT 24 Aug 01 08:32:44 PM PDT 24 6757323801 ps
T147 /workspace/coverage/default/0.rom_raw_unlock.528300018 Aug 01 08:18:47 PM PDT 24 Aug 01 08:24:03 PM PDT 24 5341320248 ps
T1020 /workspace/coverage/default/0.chip_sival_flash_info_access.1648379760 Aug 01 08:13:07 PM PDT 24 Aug 01 08:18:49 PM PDT 24 3048977916 ps
T1021 /workspace/coverage/default/0.chip_sw_aes_masking_off.2104671615 Aug 01 08:15:38 PM PDT 24 Aug 01 08:22:52 PM PDT 24 3242267085 ps
T768 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3513694134 Aug 01 08:51:08 PM PDT 24 Aug 01 08:58:56 PM PDT 24 3966597480 ps
T1022 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2436530534 Aug 01 08:34:02 PM PDT 24 Aug 02 12:16:13 AM PDT 24 255340703614 ps
T759 /workspace/coverage/default/37.chip_sw_all_escalation_resets.1566306432 Aug 01 08:47:31 PM PDT 24 Aug 01 08:58:56 PM PDT 24 4486677744 ps
T1023 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1099531604 Aug 01 08:15:19 PM PDT 24 Aug 01 09:19:31 PM PDT 24 16408776440 ps
T528 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1663128510 Aug 01 08:24:28 PM PDT 24 Aug 01 08:39:43 PM PDT 24 5097810200 ps
T1024 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3377613933 Aug 01 08:16:42 PM PDT 24 Aug 01 08:27:04 PM PDT 24 4933089190 ps
T1025 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1150434607 Aug 01 08:23:44 PM PDT 24 Aug 01 09:38:11 PM PDT 24 15183519096 ps
T812 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2758434002 Aug 01 08:46:06 PM PDT 24 Aug 01 08:52:45 PM PDT 24 3328732536 ps
T689 /workspace/coverage/default/1.chip_sw_power_sleep_load.711167623 Aug 01 08:29:59 PM PDT 24 Aug 01 08:34:38 PM PDT 24 4092628362 ps
T1026 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2295424037 Aug 01 08:42:38 PM PDT 24 Aug 01 08:53:45 PM PDT 24 3726525926 ps
T1027 /workspace/coverage/default/2.chip_sw_example_concurrency.4066723912 Aug 01 08:31:41 PM PDT 24 Aug 01 08:36:33 PM PDT 24 3178243284 ps
T1028 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.3778527360 Aug 01 08:13:04 PM PDT 24 Aug 01 08:16:35 PM PDT 24 2569835207 ps
T1029 /workspace/coverage/default/2.chip_sw_kmac_idle.2196154221 Aug 01 08:37:06 PM PDT 24 Aug 01 08:41:30 PM PDT 24 2871005532 ps
T662 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3260365095 Aug 01 08:14:23 PM PDT 24 Aug 01 08:16:21 PM PDT 24 2738174503 ps
T1030 /workspace/coverage/default/1.chip_sw_csrng_smoketest.2924028993 Aug 01 08:29:49 PM PDT 24 Aug 01 08:34:33 PM PDT 24 3245786568 ps
T1031 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.4064124916 Aug 01 08:31:18 PM PDT 24 Aug 01 08:37:24 PM PDT 24 2954099284 ps
T1032 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2604175013 Aug 01 08:37:51 PM PDT 24 Aug 01 08:45:11 PM PDT 24 3853658072 ps
T1033 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3449608044 Aug 01 08:22:12 PM PDT 24 Aug 01 09:21:58 PM PDT 24 14835936580 ps
T1034 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2418287406 Aug 01 08:38:00 PM PDT 24 Aug 01 08:46:24 PM PDT 24 3846478360 ps
T1035 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3401875374 Aug 01 08:43:19 PM PDT 24 Aug 01 08:55:47 PM PDT 24 3995036328 ps
T806 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1123154695 Aug 01 08:45:55 PM PDT 24 Aug 01 08:52:48 PM PDT 24 4183530718 ps
T681 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3686146654 Aug 01 08:15:04 PM PDT 24 Aug 01 08:19:39 PM PDT 24 3167040232 ps
T1036 /workspace/coverage/default/2.rom_e2e_asm_init_prod.3254921494 Aug 01 08:44:59 PM PDT 24 Aug 01 09:37:04 PM PDT 24 15668897213 ps
T1037 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.3934842870 Aug 01 08:33:45 PM PDT 24 Aug 01 08:38:19 PM PDT 24 3978293904 ps
T1038 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.2517856341 Aug 01 08:46:09 PM PDT 24 Aug 01 09:21:40 PM PDT 24 13014273750 ps
T1039 /workspace/coverage/default/1.chip_sw_edn_auto_mode.2156452655 Aug 01 08:24:58 PM PDT 24 Aug 01 08:36:33 PM PDT 24 3395644666 ps
T1040 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3732342288 Aug 01 08:40:05 PM PDT 24 Aug 01 08:59:46 PM PDT 24 6917163958 ps
T1041 /workspace/coverage/default/0.chip_sw_aes_idle.1499674443 Aug 01 08:16:16 PM PDT 24 Aug 01 08:19:52 PM PDT 24 2599721160 ps
T252 /workspace/coverage/default/77.chip_sw_all_escalation_resets.1651214394 Aug 01 08:52:18 PM PDT 24 Aug 01 09:01:43 PM PDT 24 5276132534 ps
T1042 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1149036550 Aug 01 08:14:21 PM PDT 24 Aug 01 08:21:30 PM PDT 24 3746886874 ps
T1043 /workspace/coverage/default/0.chip_sw_hmac_oneshot.232138804 Aug 01 08:12:45 PM PDT 24 Aug 01 08:17:40 PM PDT 24 3473803306 ps
T1044 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.161739460 Aug 01 08:14:16 PM PDT 24 Aug 01 08:43:49 PM PDT 24 10519159408 ps
T364 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1738060070 Aug 01 08:19:54 PM PDT 24 Aug 01 08:32:03 PM PDT 24 4022906866 ps
T1045 /workspace/coverage/default/0.rom_e2e_shutdown_output.3564635773 Aug 01 08:18:39 PM PDT 24 Aug 01 09:25:36 PM PDT 24 28185873399 ps
T763 /workspace/coverage/default/79.chip_sw_all_escalation_resets.588826502 Aug 01 08:51:07 PM PDT 24 Aug 01 09:00:41 PM PDT 24 5095953072 ps
T774 /workspace/coverage/default/91.chip_sw_all_escalation_resets.4191030735 Aug 01 08:52:16 PM PDT 24 Aug 01 09:02:21 PM PDT 24 4781194180 ps
T360 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.616859370 Aug 01 08:32:19 PM PDT 24 Aug 01 08:43:40 PM PDT 24 4119271795 ps
T1046 /workspace/coverage/default/0.chip_sw_example_manufacturer.387842308 Aug 01 08:12:22 PM PDT 24 Aug 01 08:14:52 PM PDT 24 2292739006 ps
T1047 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2128279039 Aug 01 08:29:55 PM PDT 24 Aug 01 08:34:24 PM PDT 24 2894672190 ps
T1048 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.743746491 Aug 01 08:15:04 PM PDT 24 Aug 01 08:33:09 PM PDT 24 5971387304 ps
T781 /workspace/coverage/default/13.chip_sw_all_escalation_resets.916723573 Aug 01 08:45:19 PM PDT 24 Aug 01 08:54:04 PM PDT 24 5045944172 ps
T1049 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3651434915 Aug 01 08:34:37 PM PDT 24 Aug 01 08:44:58 PM PDT 24 5606693212 ps
T1050 /workspace/coverage/default/0.chip_sw_rv_timer_irq.3271052337 Aug 01 08:14:24 PM PDT 24 Aug 01 08:17:43 PM PDT 24 2597586520 ps
T1051 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3204125799 Aug 01 08:47:27 PM PDT 24 Aug 01 08:56:19 PM PDT 24 4091529312 ps
T1052 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3535614897 Aug 01 08:30:50 PM PDT 24 Aug 01 08:35:49 PM PDT 24 3368414118 ps
T1053 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2244765507 Aug 01 08:42:39 PM PDT 24 Aug 01 08:55:47 PM PDT 24 4278337808 ps
T39 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2837995485 Aug 01 08:33:02 PM PDT 24 Aug 01 08:41:16 PM PDT 24 6897591110 ps
T1054 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2526751943 Aug 01 08:22:42 PM PDT 24 Aug 01 08:34:21 PM PDT 24 4810729642 ps
T1055 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.4008634209 Aug 01 08:22:31 PM PDT 24 Aug 01 10:14:48 PM PDT 24 24315090140 ps
T1056 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.520301260 Aug 01 08:19:26 PM PDT 24 Aug 01 08:29:43 PM PDT 24 4005804892 ps
T358 /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3706425316 Aug 01 08:18:27 PM PDT 24 Aug 01 08:25:26 PM PDT 24 3807699946 ps
T339 /workspace/coverage/default/2.chip_plic_all_irqs_20.640077352 Aug 01 08:37:38 PM PDT 24 Aug 01 08:49:41 PM PDT 24 4911203766 ps
T378 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3942602114 Aug 01 08:20:00 PM PDT 24 Aug 01 08:31:17 PM PDT 24 3694276556 ps
T778 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1487508949 Aug 01 08:49:44 PM PDT 24 Aug 01 08:56:17 PM PDT 24 3772902896 ps
T27 /workspace/coverage/default/0.chip_sw_usbdev_config_host.707651804 Aug 01 08:12:30 PM PDT 24 Aug 01 08:46:40 PM PDT 24 8398655092 ps
T811 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.4023193352 Aug 01 08:47:20 PM PDT 24 Aug 01 08:52:45 PM PDT 24 4004562292 ps
T284 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1721739266 Aug 01 08:26:32 PM PDT 24 Aug 01 08:38:25 PM PDT 24 8864830311 ps
T245 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.503591886 Aug 01 08:19:31 PM PDT 24 Aug 01 09:44:14 PM PDT 24 47241346300 ps
T384 /workspace/coverage/default/26.chip_sw_all_escalation_resets.2543536734 Aug 01 08:46:59 PM PDT 24 Aug 01 08:59:57 PM PDT 24 5491543292 ps
T1057 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1986431913 Aug 01 08:42:28 PM PDT 24 Aug 01 08:53:07 PM PDT 24 4332332574 ps
T1058 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1210267210 Aug 01 08:21:41 PM PDT 24 Aug 01 09:15:17 PM PDT 24 11413882580 ps
T266 /workspace/coverage/default/58.chip_sw_all_escalation_resets.2540436573 Aug 01 08:49:53 PM PDT 24 Aug 01 09:00:02 PM PDT 24 4721962502 ps
T1059 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3318456662 Aug 01 08:21:39 PM PDT 24 Aug 01 08:28:32 PM PDT 24 4935503256 ps
T72 /workspace/coverage/default/3.chip_tap_straps_testunlock0.2021251692 Aug 01 08:40:56 PM PDT 24 Aug 01 08:44:38 PM PDT 24 3692532257 ps
T1060 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.1738245821 Aug 01 08:35:59 PM PDT 24 Aug 01 08:43:14 PM PDT 24 4804314968 ps
T54 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.4237320922 Aug 01 08:19:22 PM PDT 24 Aug 01 08:24:18 PM PDT 24 3239103160 ps
T799 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2809330443 Aug 01 08:44:18 PM PDT 24 Aug 01 08:51:48 PM PDT 24 3586251980 ps
T1061 /workspace/coverage/default/1.chip_sw_uart_tx_rx.474896625 Aug 01 08:21:16 PM PDT 24 Aug 01 08:33:49 PM PDT 24 3757412640 ps
T1062 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2343840201 Aug 01 08:15:32 PM PDT 24 Aug 01 08:44:17 PM PDT 24 14808687673 ps
T1063 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3123921088 Aug 01 08:43:33 PM PDT 24 Aug 01 09:05:43 PM PDT 24 7965517484 ps
T1064 /workspace/coverage/default/2.chip_sw_example_rom.3168676526 Aug 01 08:29:42 PM PDT 24 Aug 01 08:32:20 PM PDT 24 2400039336 ps
T42 /workspace/coverage/default/0.chip_sw_spi_device_tpm.3062995066 Aug 01 08:13:31 PM PDT 24 Aug 01 08:19:22 PM PDT 24 3216792617 ps
T1065 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.457320896 Aug 01 08:20:43 PM PDT 24 Aug 01 08:30:20 PM PDT 24 4533500167 ps
T1066 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2453849217 Aug 01 08:27:11 PM PDT 24 Aug 01 08:34:55 PM PDT 24 5166282530 ps
T1067 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.4210154795 Aug 01 08:11:59 PM PDT 24 Aug 01 08:36:10 PM PDT 24 7924603069 ps
T172 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.3704499105 Aug 01 08:12:38 PM PDT 24 Aug 01 08:14:40 PM PDT 24 4137955526 ps
T1068 /workspace/coverage/default/1.chip_sw_gpio_smoketest.649572924 Aug 01 08:30:34 PM PDT 24 Aug 01 08:35:32 PM PDT 24 2129697695 ps
T1069 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1387256162 Aug 01 08:31:40 PM PDT 24 Aug 01 08:41:36 PM PDT 24 4790176984 ps
T1070 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1411438271 Aug 01 08:35:06 PM PDT 24 Aug 01 09:34:21 PM PDT 24 19299221757 ps
T658 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2334589931 Aug 01 08:28:11 PM PDT 24 Aug 01 08:37:30 PM PDT 24 5639137419 ps
T529 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3938314180 Aug 01 08:38:27 PM PDT 24 Aug 01 08:51:55 PM PDT 24 5431689016 ps
T140 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.3518554419 Aug 01 08:13:38 PM PDT 24 Aug 01 08:22:54 PM PDT 24 3758180304 ps
T331 /workspace/coverage/default/83.chip_sw_all_escalation_resets.2245403373 Aug 01 08:51:54 PM PDT 24 Aug 01 09:00:19 PM PDT 24 4704279492 ps
T1071 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.2395596429 Aug 01 08:26:08 PM PDT 24 Aug 01 08:41:05 PM PDT 24 8079580924 ps
T53 /workspace/coverage/default/1.chip_sw_alert_test.2994942755 Aug 01 08:25:14 PM PDT 24 Aug 01 08:31:28 PM PDT 24 2891135222 ps
T1072 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.657582157 Aug 01 08:26:46 PM PDT 24 Aug 01 08:33:50 PM PDT 24 3604806120 ps
T1073 /workspace/coverage/default/1.chip_sw_aes_idle.1597178254 Aug 01 08:23:29 PM PDT 24 Aug 01 08:26:42 PM PDT 24 2157772640 ps
T663 /workspace/coverage/default/2.rom_volatile_raw_unlock.3104996850 Aug 01 08:40:13 PM PDT 24 Aug 01 08:42:08 PM PDT 24 2512539570 ps
T1074 /workspace/coverage/default/2.chip_sw_flash_crash_alert.3239102003 Aug 01 08:38:34 PM PDT 24 Aug 01 08:50:07 PM PDT 24 4893329202 ps
T1075 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1203649348 Aug 01 08:33:43 PM PDT 24 Aug 01 09:23:31 PM PDT 24 33162603470 ps
T400 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.87314733 Aug 01 08:15:50 PM PDT 24 Aug 01 08:20:17 PM PDT 24 2837181240 ps
T1076 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3209530250 Aug 01 08:18:56 PM PDT 24 Aug 01 08:25:08 PM PDT 24 3630012135 ps
T1077 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1949943542 Aug 01 08:21:40 PM PDT 24 Aug 01 08:35:19 PM PDT 24 7653793492 ps
T336 /workspace/coverage/default/1.chip_plic_all_irqs_0.234717568 Aug 01 08:27:15 PM PDT 24 Aug 01 08:43:56 PM PDT 24 6066844524 ps
T1078 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1226847105 Aug 01 08:35:38 PM PDT 24 Aug 01 08:52:35 PM PDT 24 6021168693 ps
T59 /workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.488514725 Aug 01 08:31:23 PM PDT 24 Aug 01 08:37:11 PM PDT 24 3693704869 ps
T1079 /workspace/coverage/default/3.chip_tap_straps_dev.3459631962 Aug 01 08:40:54 PM PDT 24 Aug 01 08:57:00 PM PDT 24 9267823681 ps
T1080 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3245061666 Aug 01 08:41:11 PM PDT 24 Aug 01 08:47:48 PM PDT 24 6777998260 ps
T765 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3138023364 Aug 01 08:52:36 PM PDT 24 Aug 01 08:58:05 PM PDT 24 3599413308 ps
T751 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3192775780 Aug 01 08:51:42 PM PDT 24 Aug 01 08:58:25 PM PDT 24 3284399352 ps
T173 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2374573250 Aug 01 08:32:40 PM PDT 24 Aug 01 09:11:56 PM PDT 24 31856095700 ps
T1081 /workspace/coverage/default/0.chip_sw_usbdev_vbus.4175156322 Aug 01 08:13:33 PM PDT 24 Aug 01 08:17:39 PM PDT 24 2865789460 ps
T1082 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3003584681 Aug 01 08:16:39 PM PDT 24 Aug 01 09:09:01 PM PDT 24 31349877224 ps
T1083 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3201411715 Aug 01 08:16:33 PM PDT 24 Aug 01 09:15:03 PM PDT 24 18813338579 ps
T1084 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3019868447 Aug 01 08:22:56 PM PDT 24 Aug 01 08:41:43 PM PDT 24 5730427464 ps
T1085 /workspace/coverage/default/2.chip_sw_example_flash.3955752895 Aug 01 08:31:22 PM PDT 24 Aug 01 08:35:11 PM PDT 24 2833649280 ps
T199 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.655375283 Aug 01 08:13:52 PM PDT 24 Aug 01 08:24:51 PM PDT 24 4369507217 ps
T1086 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3593709840 Aug 01 08:17:24 PM PDT 24 Aug 01 08:20:49 PM PDT 24 3366739122 ps
T1087 /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.158645075 Aug 01 08:42:26 PM PDT 24 Aug 01 09:58:22 PM PDT 24 15784918910 ps
T1088 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.4076156603 Aug 01 08:35:36 PM PDT 24 Aug 01 09:01:28 PM PDT 24 10521882672 ps
T1089 /workspace/coverage/default/15.chip_sw_all_escalation_resets.4231735241 Aug 01 08:45:04 PM PDT 24 Aug 01 08:54:39 PM PDT 24 4855094654 ps
T156 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3181078885 Aug 01 08:24:12 PM PDT 24 Aug 01 08:28:06 PM PDT 24 2948283953 ps
T186 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1785633779 Aug 01 08:19:11 PM PDT 24 Aug 01 09:41:08 PM PDT 24 42450386949 ps
T695 /workspace/coverage/default/2.rom_raw_unlock.3682190954 Aug 01 08:42:24 PM PDT 24 Aug 01 08:48:15 PM PDT 24 6107848974 ps
T234 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2639555282 Aug 01 08:36:53 PM PDT 24 Aug 01 09:43:12 PM PDT 24 13220015714 ps
T723 /workspace/coverage/default/78.chip_sw_all_escalation_resets.2584772017 Aug 01 08:50:53 PM PDT 24 Aug 01 09:00:50 PM PDT 24 5179918160 ps
T703 /workspace/coverage/default/49.chip_sw_all_escalation_resets.1746301724 Aug 01 08:48:15 PM PDT 24 Aug 01 08:55:00 PM PDT 24 4614380162 ps
T1090 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.3849032063 Aug 01 08:16:04 PM PDT 24 Aug 01 08:25:33 PM PDT 24 5217364104 ps
T1091 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.616968850 Aug 01 08:27:48 PM PDT 24 Aug 01 08:33:25 PM PDT 24 2618179094 ps
T1092 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.4217238716 Aug 01 08:21:36 PM PDT 24 Aug 01 08:29:46 PM PDT 24 4859792868 ps
T740 /workspace/coverage/default/23.chip_sw_all_escalation_resets.3752853234 Aug 01 08:47:52 PM PDT 24 Aug 01 08:58:31 PM PDT 24 5975143984 ps
T396 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3299784350 Aug 01 08:33:23 PM PDT 24 Aug 01 08:51:03 PM PDT 24 5584959784 ps
T307 /workspace/coverage/default/42.chip_sw_all_escalation_resets.3510441330 Aug 01 08:47:18 PM PDT 24 Aug 01 08:55:50 PM PDT 24 4051398000 ps
T57 /workspace/coverage/default/0.chip_jtag_csr_rw.3530239673 Aug 01 08:06:48 PM PDT 24 Aug 01 08:26:25 PM PDT 24 12669738840 ps
T416 /workspace/coverage/default/31.chip_sw_all_escalation_resets.494760497 Aug 01 08:48:17 PM PDT 24 Aug 01 08:59:21 PM PDT 24 4818749872 ps
T417 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2998500178 Aug 01 08:15:21 PM PDT 24 Aug 01 08:52:09 PM PDT 24 9471888632 ps
T418 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3334786031 Aug 01 08:35:33 PM PDT 24 Aug 01 08:39:46 PM PDT 24 3422306558 ps
T419 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.2245299357 Aug 01 08:25:10 PM PDT 24 Aug 01 09:10:43 PM PDT 24 11732320010 ps
T420 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.4153795505 Aug 01 08:47:26 PM PDT 24 Aug 01 08:52:45 PM PDT 24 4342110312 ps
T421 /workspace/coverage/default/2.chip_sw_aes_smoketest.647350971 Aug 01 08:39:33 PM PDT 24 Aug 01 08:44:38 PM PDT 24 2324361700 ps
T422 /workspace/coverage/default/2.chip_sw_aes_idle.1731793940 Aug 01 08:38:15 PM PDT 24 Aug 01 08:42:54 PM PDT 24 2808691560 ps
T210 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.2716666534 Aug 01 08:15:20 PM PDT 24 Aug 01 08:22:12 PM PDT 24 3201538150 ps
T423 /workspace/coverage/default/84.chip_sw_all_escalation_resets.656635197 Aug 01 08:51:59 PM PDT 24 Aug 01 09:04:23 PM PDT 24 4769937190 ps
T1093 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.111388858 Aug 01 08:30:20 PM PDT 24 Aug 01 08:38:16 PM PDT 24 3567147264 ps
T1094 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.784014107 Aug 01 08:16:13 PM PDT 24 Aug 01 08:34:06 PM PDT 24 4857650036 ps
T1095 /workspace/coverage/default/0.chip_sw_usbdev_dpi.3985068731 Aug 01 08:12:03 PM PDT 24 Aug 01 09:07:19 PM PDT 24 11961143900 ps
T1096 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2965581369 Aug 01 08:15:18 PM PDT 24 Aug 01 08:27:39 PM PDT 24 9666779200 ps
T1097 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3718353540 Aug 01 08:19:55 PM PDT 24 Aug 01 08:40:12 PM PDT 24 6701445095 ps
T349 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.2377744663 Aug 01 08:36:22 PM PDT 24 Aug 01 09:01:56 PM PDT 24 6636680360 ps
T342 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1097720059 Aug 01 08:13:59 PM PDT 24 Aug 01 08:39:52 PM PDT 24 9856860504 ps
T438 /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.935739050 Aug 01 08:18:29 PM PDT 24 Aug 01 09:11:51 PM PDT 24 31164777389 ps
T40 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1539225849 Aug 01 08:22:59 PM PDT 24 Aug 01 08:36:05 PM PDT 24 7011523700 ps
T332 /workspace/coverage/default/63.chip_sw_all_escalation_resets.3687609085 Aug 01 08:50:41 PM PDT 24 Aug 01 09:04:00 PM PDT 24 5225132728 ps
T1098 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.4043421416 Aug 01 08:38:15 PM PDT 24 Aug 01 08:47:45 PM PDT 24 4644873172 ps
T1099 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2642109712 Aug 01 08:35:18 PM PDT 24 Aug 01 09:01:04 PM PDT 24 6484381528 ps
T122 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2025943266 Aug 01 08:28:00 PM PDT 24 Aug 01 08:35:30 PM PDT 24 4824600456 ps
T333 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2806627978 Aug 01 08:48:37 PM PDT 24 Aug 01 08:56:53 PM PDT 24 4546035658 ps
T1100 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.731384648 Aug 01 08:18:24 PM PDT 24 Aug 01 08:22:17 PM PDT 24 3012080714 ps
T664 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2835138978 Aug 01 08:14:10 PM PDT 24 Aug 01 08:15:57 PM PDT 24 1976730286 ps
T1101 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.541028907 Aug 01 08:43:27 PM PDT 24 Aug 01 09:26:15 PM PDT 24 10851166859 ps
T747 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2546303233 Aug 01 08:51:24 PM PDT 24 Aug 01 08:57:13 PM PDT 24 3281455484 ps
T409 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2658695897 Aug 01 08:27:30 PM PDT 24 Aug 01 08:35:59 PM PDT 24 4307076510 ps
T1102 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2626534725 Aug 01 08:14:38 PM PDT 24 Aug 01 08:23:56 PM PDT 24 5200319536 ps
T1103 /workspace/coverage/default/0.chip_sw_otbn_smoketest.1653143468 Aug 01 08:21:10 PM PDT 24 Aug 01 09:01:17 PM PDT 24 9756249748 ps
T30 /workspace/coverage/default/1.chip_sw_gpio.181200019 Aug 01 08:23:29 PM PDT 24 Aug 01 08:30:48 PM PDT 24 4293876364 ps
T211 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.3760712544 Aug 01 08:33:22 PM PDT 24 Aug 01 08:39:57 PM PDT 24 3869192544 ps
T433 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1764647458 Aug 01 08:18:17 PM PDT 24 Aug 01 08:24:48 PM PDT 24 7632140646 ps
T343 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1967156093 Aug 01 08:33:55 PM PDT 24 Aug 01 09:02:12 PM PDT 24 14098382600 ps
T1104 /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.116852300 Aug 01 08:42:22 PM PDT 24 Aug 01 10:03:23 PM PDT 24 22347268946 ps
T1105 /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2380944888 Aug 01 08:14:31 PM PDT 24 Aug 01 08:24:13 PM PDT 24 5044208712 ps
T127 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.166422820 Aug 01 08:43:12 PM PDT 24 Aug 01 08:55:21 PM PDT 24 7206582826 ps
T1106 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.732530847 Aug 01 08:33:04 PM PDT 24 Aug 01 09:20:02 PM PDT 24 9241590788 ps
T1107 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1504348722 Aug 01 08:46:19 PM PDT 24 Aug 01 08:53:55 PM PDT 24 4289348482 ps
T734 /workspace/coverage/default/12.chip_sw_all_escalation_resets.3352940287 Aug 01 08:45:19 PM PDT 24 Aug 01 08:55:50 PM PDT 24 5120460936 ps
T43 /workspace/coverage/default/1.chip_sw_spi_device_tpm.442984167 Aug 01 08:20:18 PM PDT 24 Aug 01 08:25:31 PM PDT 24 3172556947 ps
T55 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.4283601254 Aug 01 08:31:44 PM PDT 24 Aug 01 08:37:33 PM PDT 24 4244359536 ps
T246 /workspace/coverage/default/0.chip_sw_flash_init.1525055954 Aug 01 08:12:26 PM PDT 24 Aug 01 08:39:11 PM PDT 24 21734583206 ps
T1108 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.1199754217 Aug 01 08:44:48 PM PDT 24 Aug 01 08:58:19 PM PDT 24 11150253164 ps
T755 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.441821373 Aug 01 08:45:49 PM PDT 24 Aug 01 08:52:18 PM PDT 24 3673561802 ps
T200 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.264049723 Aug 01 08:19:52 PM PDT 24 Aug 01 08:29:19 PM PDT 24 4090433184 ps
T316 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.120755799 Aug 01 08:19:03 PM PDT 24 Aug 01 08:24:48 PM PDT 24 2795173436 ps
T1109 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.867821108 Aug 01 08:20:06 PM PDT 24 Aug 01 09:28:00 PM PDT 24 15328887230 ps
T157 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3232615029 Aug 01 08:13:27 PM PDT 24 Aug 01 08:18:06 PM PDT 24 2422044866 ps
T775 /workspace/coverage/default/10.chip_sw_all_escalation_resets.4100693695 Aug 01 08:43:31 PM PDT 24 Aug 01 08:54:17 PM PDT 24 4360854232 ps
T31 /workspace/coverage/default/2.chip_sw_gpio.959274534 Aug 01 08:31:32 PM PDT 24 Aug 01 08:39:04 PM PDT 24 4062297410 ps
T1110 /workspace/coverage/default/2.chip_sw_aes_enc.232299499 Aug 01 08:37:47 PM PDT 24 Aug 01 08:42:09 PM PDT 24 2892513520 ps
T1111 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.804594628 Aug 01 08:34:34 PM PDT 24 Aug 01 08:46:40 PM PDT 24 4474293420 ps
T1112 /workspace/coverage/default/1.chip_sw_csrng_kat_test.4128970281 Aug 01 08:25:16 PM PDT 24 Aug 01 08:30:57 PM PDT 24 2962287616 ps
T1113 /workspace/coverage/default/2.chip_sw_hmac_oneshot.3144347726 Aug 01 08:36:31 PM PDT 24 Aug 01 08:42:28 PM PDT 24 3779725000 ps
T1114 /workspace/coverage/default/2.rom_keymgr_functest.1450873298 Aug 01 08:39:58 PM PDT 24 Aug 01 08:48:07 PM PDT 24 3856507958 ps
T1115 /workspace/coverage/default/2.chip_sw_csrng_kat_test.3662015754 Aug 01 08:35:11 PM PDT 24 Aug 01 08:39:17 PM PDT 24 3130021460 ps
T1116 /workspace/coverage/default/1.chip_sw_hmac_oneshot.2830793903 Aug 01 08:24:31 PM PDT 24 Aug 01 08:28:41 PM PDT 24 3108103070 ps
T1117 /workspace/coverage/default/2.chip_sw_uart_smoketest.3364923829 Aug 01 08:40:21 PM PDT 24 Aug 01 08:44:43 PM PDT 24 3239000476 ps
T1118 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3392101116 Aug 01 08:31:10 PM PDT 24 Aug 01 08:44:03 PM PDT 24 4689732064 ps
T704 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1877919756 Aug 01 08:49:39 PM PDT 24 Aug 01 08:54:44 PM PDT 24 3552307720 ps
T1119 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1311874266 Aug 01 08:13:03 PM PDT 24 Aug 01 09:35:02 PM PDT 24 49783959566 ps
T738 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1011395456 Aug 01 08:44:08 PM PDT 24 Aug 01 08:51:54 PM PDT 24 3522739930 ps
T1120 /workspace/coverage/default/0.chip_sw_uart_smoketest.1790196055 Aug 01 08:18:25 PM PDT 24 Aug 01 08:22:26 PM PDT 24 2501122670 ps
T1121 /workspace/coverage/default/2.chip_tap_straps_dev.1647910898 Aug 01 08:38:01 PM PDT 24 Aug 01 08:55:01 PM PDT 24 8831976750 ps
T1122 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1838589153 Aug 01 08:37:16 PM PDT 24 Aug 01 08:46:04 PM PDT 24 6275932357 ps
T128 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1806646582 Aug 01 08:25:34 PM PDT 24 Aug 01 08:42:54 PM PDT 24 9134838578 ps
T153 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.2901992281 Aug 01 08:30:43 PM PDT 24 Aug 01 08:36:50 PM PDT 24 3023881906 ps
T750 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1479386618 Aug 01 08:49:53 PM PDT 24 Aug 01 08:56:33 PM PDT 24 3843005320 ps
T782 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.937091090 Aug 01 08:51:47 PM PDT 24 Aug 01 08:57:51 PM PDT 24 4276683528 ps
T1123 /workspace/coverage/default/1.rom_e2e_asm_init_dev.626546864 Aug 01 08:34:36 PM PDT 24 Aug 01 09:36:32 PM PDT 24 15211567026 ps
T1124 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3318435509 Aug 01 08:21:21 PM PDT 24 Aug 01 08:33:39 PM PDT 24 5742222426 ps
T1125 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3940889363 Aug 01 08:15:22 PM PDT 24 Aug 01 08:21:37 PM PDT 24 4170649664 ps
T1126 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.497648507 Aug 01 08:26:08 PM PDT 24 Aug 01 08:30:25 PM PDT 24 3287458880 ps
T365 /workspace/coverage/default/1.chip_sw_pattgen_ios.2160451185 Aug 01 08:21:31 PM PDT 24 Aug 01 08:25:22 PM PDT 24 2796436528 ps
T1127 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1731205711 Aug 01 08:32:40 PM PDT 24 Aug 01 10:09:12 PM PDT 24 48670179920 ps
T1128 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3817958862 Aug 01 08:44:35 PM PDT 24 Aug 01 08:51:44 PM PDT 24 3638616508 ps
T212 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.793970697 Aug 01 08:21:10 PM PDT 24 Aug 01 08:31:14 PM PDT 24 4996314944 ps
T1129 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.937059484 Aug 01 08:43:49 PM PDT 24 Aug 01 09:04:45 PM PDT 24 8893731332 ps
T1130 /workspace/coverage/default/0.rom_volatile_raw_unlock.621138354 Aug 01 08:18:58 PM PDT 24 Aug 01 08:21:03 PM PDT 24 2544166115 ps
T1131 /workspace/coverage/default/2.rom_e2e_smoke.3245716100 Aug 01 08:44:22 PM PDT 24 Aug 01 09:38:55 PM PDT 24 15336863046 ps
T1132 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.2783577436 Aug 01 08:26:28 PM PDT 24 Aug 01 09:03:46 PM PDT 24 23552623684 ps
T769 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1309646153 Aug 01 08:52:04 PM PDT 24 Aug 01 08:57:33 PM PDT 24 3875844912 ps
T1133 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3832398292 Aug 01 08:31:31 PM PDT 24 Aug 01 08:56:30 PM PDT 24 8911486390 ps
T82 /workspace/coverage/default/0.chip_jtag_mem_access.1286215448 Aug 01 08:06:49 PM PDT 24 Aug 01 08:30:50 PM PDT 24 13636961166 ps
T1134 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3793835153 Aug 01 08:15:48 PM PDT 24 Aug 01 08:29:44 PM PDT 24 5066395140 ps
T201 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.3328437445 Aug 01 08:32:09 PM PDT 24 Aug 01 08:46:15 PM PDT 24 7563647883 ps
T1135 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.436163062 Aug 01 08:23:50 PM PDT 24 Aug 01 08:32:47 PM PDT 24 4268847760 ps
T1136 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.1965867063 Aug 01 08:20:08 PM PDT 24 Aug 01 08:36:20 PM PDT 24 5196359074 ps
T366 /workspace/coverage/default/2.chip_sw_pattgen_ios.2166218473 Aug 01 08:31:25 PM PDT 24 Aug 01 08:35:55 PM PDT 24 3240235390 ps
T1137 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.104647218 Aug 01 08:39:01 PM PDT 24 Aug 01 08:43:55 PM PDT 24 3601968755 ps
T37 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1717672185 Aug 01 08:30:41 PM PDT 24 Aug 01 08:34:43 PM PDT 24 3394799978 ps
T794 /workspace/coverage/default/34.chip_sw_all_escalation_resets.831307207 Aug 01 08:46:47 PM PDT 24 Aug 01 08:57:30 PM PDT 24 6284272440 ps
T1138 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.3933723862 Aug 01 08:30:22 PM PDT 24 Aug 01 08:33:24 PM PDT 24 2582421464 ps
T1139 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.2860994451 Aug 01 08:42:44 PM PDT 24 Aug 01 09:09:57 PM PDT 24 8033634398 ps
T705 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2793436096 Aug 01 08:50:43 PM PDT 24 Aug 01 08:58:20 PM PDT 24 3998152434 ps
T653 /workspace/coverage/default/2.chip_sw_edn_boot_mode.3590318738 Aug 01 08:34:18 PM PDT 24 Aug 01 08:44:02 PM PDT 24 2601353320 ps
T1140 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.303204765 Aug 01 08:35:45 PM PDT 24 Aug 01 08:41:27 PM PDT 24 2587857558 ps
T698 /workspace/coverage/default/0.chip_sw_pattgen_ios.165215482 Aug 01 08:12:40 PM PDT 24 Aug 01 08:16:52 PM PDT 24 2279340054 ps
T654 /workspace/coverage/default/0.chip_sw_edn_boot_mode.3762551056 Aug 01 08:16:47 PM PDT 24 Aug 01 08:25:52 PM PDT 24 3163029988 ps
T158 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.4075889613 Aug 01 08:33:32 PM PDT 24 Aug 01 08:35:25 PM PDT 24 2664008651 ps
T1141 /workspace/coverage/default/1.chip_sival_flash_info_access.2571773557 Aug 01 08:24:46 PM PDT 24 Aug 01 08:29:37 PM PDT 24 3841032480 ps
T1142 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.333594221 Aug 01 08:15:09 PM PDT 24 Aug 01 08:22:31 PM PDT 24 4444461280 ps
T1143 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2130269641 Aug 01 08:12:53 PM PDT 24 Aug 02 12:01:54 AM PDT 24 77416716690 ps
T787 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2723820525 Aug 01 08:51:42 PM PDT 24 Aug 01 08:57:43 PM PDT 24 4410359480 ps
T129 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1942135069 Aug 01 08:43:18 PM PDT 24 Aug 01 08:58:44 PM PDT 24 8996071684 ps
T797 /workspace/coverage/default/71.chip_sw_all_escalation_resets.185833240 Aug 01 08:50:13 PM PDT 24 Aug 01 09:01:56 PM PDT 24 6492781040 ps
T1144 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3976396350 Aug 01 08:27:12 PM PDT 24 Aug 01 08:36:07 PM PDT 24 4773293464 ps
T659 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2153667602 Aug 01 08:17:27 PM PDT 24 Aug 01 08:25:55 PM PDT 24 4952497605 ps
T699 /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.3369298291 Aug 01 08:18:20 PM PDT 24 Aug 01 08:50:55 PM PDT 24 11092204579 ps
T756 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2535075940 Aug 01 08:49:01 PM PDT 24 Aug 01 08:55:55 PM PDT 24 3921927800 ps
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