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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.15 95.49 94.05 95.34 94.90 97.53 99.61


Total test records in report: 2935
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T1145 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1435788487 Aug 01 08:13:59 PM PDT 24 Aug 01 08:38:11 PM PDT 24 6982711438 ps
T1146 /workspace/coverage/default/0.chip_sw_hmac_smoketest.249146216 Aug 01 08:18:45 PM PDT 24 Aug 01 08:25:10 PM PDT 24 2850497904 ps
T1147 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.1009259251 Aug 01 08:38:39 PM PDT 24 Aug 01 08:42:21 PM PDT 24 2991544534 ps
T1148 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1033972970 Aug 01 08:39:30 PM PDT 24 Aug 01 08:45:20 PM PDT 24 2989260141 ps
T1149 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.552649944 Aug 01 08:29:09 PM PDT 24 Aug 01 08:34:56 PM PDT 24 3241706328 ps
T1150 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3751364376 Aug 01 08:31:23 PM PDT 24 Aug 01 08:34:43 PM PDT 24 2578395700 ps
T1151 /workspace/coverage/default/97.chip_sw_all_escalation_resets.1755074569 Aug 01 08:52:16 PM PDT 24 Aug 01 09:01:01 PM PDT 24 4855399196 ps
T308 /workspace/coverage/default/69.chip_sw_all_escalation_resets.658650446 Aug 01 08:50:24 PM PDT 24 Aug 01 08:57:29 PM PDT 24 4101913168 ps
T1152 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1087263233 Aug 01 08:24:36 PM PDT 24 Aug 01 09:31:42 PM PDT 24 15424549500 ps
T721 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3952670985 Aug 01 08:46:51 PM PDT 24 Aug 01 08:53:33 PM PDT 24 4416785640 ps
T1153 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.90924490 Aug 01 08:35:03 PM PDT 24 Aug 01 09:35:53 PM PDT 24 14702364658 ps
T779 /workspace/coverage/default/50.chip_sw_all_escalation_resets.3646508132 Aug 01 08:48:39 PM PDT 24 Aug 01 09:03:17 PM PDT 24 6036104432 ps
T1154 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.407079654 Aug 01 08:30:57 PM PDT 24 Aug 01 08:38:03 PM PDT 24 5057236640 ps
T1155 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1791813252 Aug 01 08:15:40 PM PDT 24 Aug 01 08:19:35 PM PDT 24 2330475536 ps
T11 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.335583917 Aug 01 08:13:06 PM PDT 24 Aug 01 08:19:02 PM PDT 24 3098295708 ps
T764 /workspace/coverage/default/96.chip_sw_all_escalation_resets.4113792740 Aug 01 08:52:45 PM PDT 24 Aug 01 09:02:53 PM PDT 24 6000689300 ps
T267 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2085007002 Aug 01 08:13:24 PM PDT 24 Aug 01 08:24:22 PM PDT 24 6123159148 ps
T1156 /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.1375352045 Aug 01 08:15:16 PM PDT 24 Aug 01 08:38:53 PM PDT 24 8230607860 ps
T1157 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1592373954 Aug 01 08:19:45 PM PDT 24 Aug 01 08:31:40 PM PDT 24 4523042402 ps
T724 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.584416358 Aug 01 08:46:23 PM PDT 24 Aug 01 08:54:08 PM PDT 24 4472429708 ps
T1158 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1168444700 Aug 01 08:21:04 PM PDT 24 Aug 01 08:33:49 PM PDT 24 4580264280 ps
T1159 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1043468763 Aug 01 08:13:20 PM PDT 24 Aug 01 08:26:23 PM PDT 24 8162960024 ps
T739 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.754396398 Aug 01 08:53:23 PM PDT 24 Aug 01 08:59:12 PM PDT 24 4218315394 ps
T1160 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1858868139 Aug 01 08:36:05 PM PDT 24 Aug 01 08:43:30 PM PDT 24 8853646743 ps
T338 /workspace/coverage/default/2.chip_plic_all_irqs_0.1783395660 Aug 01 08:38:47 PM PDT 24 Aug 01 09:03:41 PM PDT 24 6299616348 ps
T790 /workspace/coverage/default/0.chip_sw_all_escalation_resets.2874236515 Aug 01 08:13:04 PM PDT 24 Aug 01 08:24:02 PM PDT 24 5834566680 ps
T1161 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.717098871 Aug 01 08:34:49 PM PDT 24 Aug 01 08:40:10 PM PDT 24 3055375101 ps
T1162 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3422796938 Aug 01 08:22:55 PM PDT 24 Aug 01 08:30:25 PM PDT 24 3947340420 ps
T1163 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1856147565 Aug 01 08:13:12 PM PDT 24 Aug 01 08:25:09 PM PDT 24 5179819520 ps
T1164 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2400367827 Aug 01 08:19:14 PM PDT 24 Aug 01 08:35:51 PM PDT 24 6342430394 ps
T1165 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.4238111402 Aug 01 08:23:43 PM PDT 24 Aug 01 09:22:35 PM PDT 24 18508290486 ps
T1166 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.59212119 Aug 01 08:37:03 PM PDT 24 Aug 01 08:55:29 PM PDT 24 7081603309 ps
T1167 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3540009542 Aug 01 08:21:32 PM PDT 24 Aug 01 08:29:06 PM PDT 24 4964234904 ps
T532 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.60529806 Aug 01 08:15:51 PM PDT 24 Aug 01 08:24:56 PM PDT 24 5447376319 ps
T1168 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.569533035 Aug 01 08:14:25 PM PDT 24 Aug 01 08:23:59 PM PDT 24 3436676568 ps
T1169 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3383718051 Aug 01 08:26:00 PM PDT 24 Aug 01 08:30:34 PM PDT 24 2923422792 ps
T1170 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1055977776 Aug 01 08:42:46 PM PDT 24 Aug 01 08:51:55 PM PDT 24 4323772158 ps
T1171 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1992794341 Aug 01 08:32:45 PM PDT 24 Aug 01 08:57:34 PM PDT 24 11683183262 ps
T1172 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.970308759 Aug 01 08:30:16 PM PDT 24 Aug 01 08:40:14 PM PDT 24 6574814834 ps
T748 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1564864765 Aug 01 08:47:15 PM PDT 24 Aug 01 08:53:04 PM PDT 24 3601190780 ps
T1173 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.2524070562 Aug 01 08:43:38 PM PDT 24 Aug 01 08:53:26 PM PDT 24 6353115386 ps
T1174 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.2325788637 Aug 01 08:38:44 PM PDT 24 Aug 01 08:43:14 PM PDT 24 2416870841 ps
T1175 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.850651806 Aug 01 08:23:37 PM PDT 24 Aug 01 08:31:10 PM PDT 24 6608578840 ps
T731 /workspace/coverage/default/47.chip_sw_all_escalation_resets.883994089 Aug 01 08:50:13 PM PDT 24 Aug 01 08:57:59 PM PDT 24 3757171576 ps
T736 /workspace/coverage/default/80.chip_sw_all_escalation_resets.256987433 Aug 01 08:51:07 PM PDT 24 Aug 01 09:03:27 PM PDT 24 5481204440 ps
T1176 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2367609366 Aug 01 08:13:57 PM PDT 24 Aug 01 08:32:22 PM PDT 24 7759760020 ps
T83 /workspace/coverage/default/1.chip_jtag_mem_access.3940102468 Aug 01 08:20:15 PM PDT 24 Aug 01 08:43:29 PM PDT 24 13895273984 ps
T1177 /workspace/coverage/default/2.chip_sw_kmac_app_rom.3374641181 Aug 01 08:36:18 PM PDT 24 Aug 01 08:41:06 PM PDT 24 3584941224 ps
T1178 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.4149307620 Aug 01 08:45:15 PM PDT 24 Aug 01 09:41:45 PM PDT 24 14581663560 ps
T1179 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2713079135 Aug 01 08:13:43 PM PDT 24 Aug 01 08:28:32 PM PDT 24 4650545100 ps
T804 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3327350044 Aug 01 08:47:49 PM PDT 24 Aug 01 08:55:08 PM PDT 24 3945800440 ps
T533 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3695510820 Aug 01 08:25:28 PM PDT 24 Aug 01 08:34:32 PM PDT 24 3384500600 ps
T1180 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1038558079 Aug 01 08:20:53 PM PDT 24 Aug 01 09:26:19 PM PDT 24 15531625344 ps
T1181 /workspace/coverage/default/1.chip_sw_kmac_idle.2535691485 Aug 01 08:25:59 PM PDT 24 Aug 01 08:30:40 PM PDT 24 3097123952 ps
T1182 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.3591549430 Aug 01 08:17:34 PM PDT 24 Aug 01 08:23:18 PM PDT 24 3382342034 ps
T174 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3659893529 Aug 01 08:13:09 PM PDT 24 Aug 01 08:15:10 PM PDT 24 3999245636 ps
T1183 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2815752504 Aug 01 08:14:56 PM PDT 24 Aug 01 08:18:37 PM PDT 24 2980367960 ps
T1184 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3126645449 Aug 01 08:13:18 PM PDT 24 Aug 01 08:24:10 PM PDT 24 5058999278 ps
T1185 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3619349591 Aug 01 08:32:32 PM PDT 24 Aug 01 08:40:16 PM PDT 24 6568078516 ps
T1186 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3296525442 Aug 01 08:30:05 PM PDT 24 Aug 01 08:34:58 PM PDT 24 2685723143 ps
T757 /workspace/coverage/default/4.chip_sw_all_escalation_resets.4209220021 Aug 01 08:41:41 PM PDT 24 Aug 01 08:53:45 PM PDT 24 6054724396 ps
T1187 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2586902270 Aug 01 08:14:57 PM PDT 24 Aug 01 08:22:57 PM PDT 24 4185619500 ps
T123 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3241286222 Aug 01 08:36:10 PM PDT 24 Aug 01 08:44:04 PM PDT 24 4571183680 ps
T1188 /workspace/coverage/default/2.chip_sw_aes_entropy.915133477 Aug 01 08:34:57 PM PDT 24 Aug 01 08:40:02 PM PDT 24 2728308840 ps
T800 /workspace/coverage/default/98.chip_sw_all_escalation_resets.3559106946 Aug 01 08:54:02 PM PDT 24 Aug 01 09:03:38 PM PDT 24 6462081520 ps
T1189 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.111184753 Aug 01 08:13:38 PM PDT 24 Aug 01 08:31:15 PM PDT 24 6778201836 ps
T1190 /workspace/coverage/default/88.chip_sw_all_escalation_resets.98537592 Aug 01 08:52:03 PM PDT 24 Aug 01 09:00:27 PM PDT 24 5511393030 ps
T1191 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.1445427054 Aug 01 08:13:33 PM PDT 24 Aug 01 08:23:29 PM PDT 24 8080324273 ps
T802 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.728204819 Aug 01 08:49:59 PM PDT 24 Aug 01 08:56:30 PM PDT 24 3796874000 ps
T735 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3714819694 Aug 01 08:51:44 PM PDT 24 Aug 01 08:57:16 PM PDT 24 3191914952 ps
T1192 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2851345080 Aug 01 08:29:41 PM PDT 24 Aug 01 08:37:45 PM PDT 24 6120619152 ps
T213 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.4263373848 Aug 01 08:15:24 PM PDT 24 Aug 01 08:20:52 PM PDT 24 3129974097 ps
T1193 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.35404810 Aug 01 08:22:33 PM PDT 24 Aug 01 08:55:51 PM PDT 24 24789330174 ps
T1194 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.508146372 Aug 01 08:22:57 PM PDT 24 Aug 01 08:27:03 PM PDT 24 2683866580 ps
T1195 /workspace/coverage/default/0.chip_sw_kmac_smoketest.3420412194 Aug 01 08:19:22 PM PDT 24 Aug 01 08:23:29 PM PDT 24 2754052472 ps
T1196 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3687309213 Aug 01 08:21:28 PM PDT 24 Aug 01 08:46:59 PM PDT 24 8380901716 ps
T1197 /workspace/coverage/default/3.chip_tap_straps_prod.435857045 Aug 01 08:40:54 PM PDT 24 Aug 01 09:12:45 PM PDT 24 18605864440 ps
T1198 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.551167758 Aug 01 08:14:28 PM PDT 24 Aug 01 08:20:09 PM PDT 24 3800987235 ps
T671 /workspace/coverage/default/44.chip_sw_all_escalation_resets.2875276449 Aug 01 08:48:10 PM PDT 24 Aug 01 09:00:32 PM PDT 24 6289309282 ps
T758 /workspace/coverage/default/65.chip_sw_all_escalation_resets.238475816 Aug 01 08:50:37 PM PDT 24 Aug 01 09:02:44 PM PDT 24 6309653320 ps
T1199 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2222976139 Aug 01 08:44:30 PM PDT 24 Aug 01 08:54:27 PM PDT 24 4687938792 ps
T1200 /workspace/coverage/default/1.chip_sw_example_rom.1017060900 Aug 01 08:19:39 PM PDT 24 Aug 01 08:21:39 PM PDT 24 1960745256 ps
T1201 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1186976150 Aug 01 08:42:16 PM PDT 24 Aug 01 09:37:35 PM PDT 24 25046600462 ps
T110 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.640968959 Aug 01 08:15:55 PM PDT 24 Aug 01 08:22:47 PM PDT 24 4209429592 ps
T770 /workspace/coverage/default/59.chip_sw_all_escalation_resets.2872067234 Aug 01 08:49:44 PM PDT 24 Aug 01 08:59:03 PM PDT 24 5853224752 ps
T1202 /workspace/coverage/default/2.chip_tap_straps_prod.164447507 Aug 01 08:38:36 PM PDT 24 Aug 01 08:41:41 PM PDT 24 2870132003 ps
T1203 /workspace/coverage/default/2.chip_sw_kmac_entropy.2651816374 Aug 01 08:32:58 PM PDT 24 Aug 01 08:37:35 PM PDT 24 2894012682 ps
T437 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.1546777977 Aug 01 08:38:41 PM PDT 24 Aug 01 08:43:29 PM PDT 24 3535866664 ps
T1204 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2111464028 Aug 01 08:18:42 PM PDT 24 Aug 01 08:27:15 PM PDT 24 4735515708 ps
T1205 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2524920989 Aug 01 08:15:41 PM PDT 24 Aug 01 08:24:27 PM PDT 24 4591625743 ps
T733 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3009906036 Aug 01 08:46:57 PM PDT 24 Aug 01 08:53:23 PM PDT 24 3571551836 ps
T1206 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.1986699286 Aug 01 08:17:01 PM PDT 24 Aug 01 08:36:49 PM PDT 24 7356733394 ps
T1207 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2409877643 Aug 01 08:20:14 PM PDT 24 Aug 02 12:19:22 AM PDT 24 78292536640 ps
T244 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.1915919656 Aug 01 08:20:59 PM PDT 24 Aug 01 09:54:54 PM PDT 24 51666311540 ps
T1208 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2455875058 Aug 01 08:41:48 PM PDT 24 Aug 01 08:51:03 PM PDT 24 7266183136 ps
T202 /workspace/coverage/default/2.chip_sw_power_virus.2437525473 Aug 01 08:44:25 PM PDT 24 Aug 01 09:06:23 PM PDT 24 5634784280 ps
T1209 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3176224189 Aug 01 08:39:05 PM PDT 24 Aug 01 08:48:22 PM PDT 24 6663217940 ps
T1210 /workspace/coverage/default/1.chip_tap_straps_dev.2532049542 Aug 01 08:27:17 PM PDT 24 Aug 01 08:29:33 PM PDT 24 2486231759 ps
T1211 /workspace/coverage/default/0.chip_sw_example_rom.857998809 Aug 01 08:11:39 PM PDT 24 Aug 01 08:13:26 PM PDT 24 2195292912 ps
T340 /workspace/coverage/default/0.chip_plic_all_irqs_20.2969318521 Aug 01 08:18:09 PM PDT 24 Aug 01 08:32:24 PM PDT 24 4475798320 ps
T752 /workspace/coverage/default/45.chip_sw_all_escalation_resets.83396894 Aug 01 08:48:18 PM PDT 24 Aug 01 08:57:46 PM PDT 24 3955645300 ps
T1212 /workspace/coverage/default/0.chip_sw_power_idle_load.4166792220 Aug 01 08:18:45 PM PDT 24 Aug 01 08:32:08 PM PDT 24 3761868996 ps
T813 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.148218700 Aug 01 08:51:19 PM PDT 24 Aug 01 08:58:26 PM PDT 24 3942378450 ps
T1213 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.107659784 Aug 01 08:29:29 PM PDT 24 Aug 01 09:31:54 PM PDT 24 25029640630 ps
T1214 /workspace/coverage/default/1.rom_keymgr_functest.2865660575 Aug 01 08:29:51 PM PDT 24 Aug 01 08:40:11 PM PDT 24 5232257440 ps
T1215 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.3023711328 Aug 01 08:21:49 PM PDT 24 Aug 01 09:52:05 PM PDT 24 22883130209 ps
T1216 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.74971896 Aug 01 08:18:55 PM PDT 24 Aug 01 09:01:34 PM PDT 24 12701418664 ps
T1217 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.430729999 Aug 01 08:22:49 PM PDT 24 Aug 01 08:27:40 PM PDT 24 2285756855 ps
T1218 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.2269730163 Aug 01 08:45:39 PM PDT 24 Aug 01 09:07:07 PM PDT 24 8764505160 ps
T1219 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1138846623 Aug 01 08:44:39 PM PDT 24 Aug 01 08:53:50 PM PDT 24 4046414104 ps
T1220 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2631672860 Aug 01 08:17:26 PM PDT 24 Aug 01 08:30:56 PM PDT 24 5494292520 ps
T1221 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3536437338 Aug 01 08:46:09 PM PDT 24 Aug 01 09:10:38 PM PDT 24 8212927260 ps
T285 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.640383983 Aug 01 08:12:53 PM PDT 24 Aug 01 08:27:19 PM PDT 24 5879105016 ps
T287 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.815217842 Aug 01 08:48:30 PM PDT 24 Aug 01 08:53:45 PM PDT 24 3367537300 ps
T288 /workspace/coverage/default/1.chip_sw_hmac_multistream.1384929359 Aug 01 08:25:49 PM PDT 24 Aug 01 09:01:42 PM PDT 24 8440216950 ps
T289 /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.794055230 Aug 01 08:19:27 PM PDT 24 Aug 01 09:10:33 PM PDT 24 33646333103 ps
T290 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2297686666 Aug 01 08:26:49 PM PDT 24 Aug 01 08:35:34 PM PDT 24 4516520900 ps
T291 /workspace/coverage/default/2.chip_sw_power_idle_load.597459194 Aug 01 08:39:33 PM PDT 24 Aug 01 08:50:00 PM PDT 24 4831671960 ps
T292 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2893396971 Aug 01 08:21:11 PM PDT 24 Aug 01 08:30:14 PM PDT 24 4331097356 ps
T293 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1941456961 Aug 01 08:13:29 PM PDT 24 Aug 01 08:46:51 PM PDT 24 32407300620 ps
T294 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1559333839 Aug 01 08:22:52 PM PDT 24 Aug 01 09:18:49 PM PDT 24 15261006672 ps
T295 /workspace/coverage/default/24.chip_sw_all_escalation_resets.1338779904 Aug 01 08:47:07 PM PDT 24 Aug 01 08:57:47 PM PDT 24 6320711852 ps
T1222 /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.469747594 Aug 01 08:46:08 PM PDT 24 Aug 01 10:35:38 PM PDT 24 32624156126 ps
T268 /workspace/coverage/default/67.chip_sw_all_escalation_resets.1311795821 Aug 01 08:50:52 PM PDT 24 Aug 01 09:02:10 PM PDT 24 5470251050 ps
T792 /workspace/coverage/default/61.chip_sw_all_escalation_resets.513623833 Aug 01 08:49:55 PM PDT 24 Aug 01 09:01:34 PM PDT 24 4844762976 ps
T1223 /workspace/coverage/default/1.chip_sw_aes_smoketest.3118315445 Aug 01 08:29:51 PM PDT 24 Aug 01 08:35:17 PM PDT 24 2964545570 ps
T786 /workspace/coverage/default/85.chip_sw_all_escalation_resets.1294220605 Aug 01 08:52:15 PM PDT 24 Aug 01 09:01:17 PM PDT 24 5673914880 ps
T1224 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3023494702 Aug 01 08:41:53 PM PDT 24 Aug 01 08:45:42 PM PDT 24 3012377650 ps
T793 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.840061911 Aug 01 08:48:48 PM PDT 24 Aug 01 08:54:05 PM PDT 24 3787867352 ps
T784 /workspace/coverage/default/74.chip_sw_all_escalation_resets.3928117749 Aug 01 08:51:04 PM PDT 24 Aug 01 09:01:41 PM PDT 24 6263487616 ps
T1225 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.497208546 Aug 01 08:44:46 PM PDT 24 Aug 01 09:05:31 PM PDT 24 7669154640 ps
T204 /workspace/coverage/default/2.chip_jtag_mem_access.2834946319 Aug 01 08:31:17 PM PDT 24 Aug 01 08:57:30 PM PDT 24 13811397690 ps
T1226 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3300242237 Aug 01 08:34:26 PM PDT 24 Aug 01 09:31:41 PM PDT 24 17215352840 ps
T1227 /workspace/coverage/default/0.chip_sw_coremark.1994295527 Aug 01 08:21:11 PM PDT 24 Aug 02 12:29:23 AM PDT 24 71443234934 ps
T1228 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2021331165 Aug 01 08:23:42 PM PDT 24 Aug 01 11:25:59 PM PDT 24 255518280464 ps
T1229 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2685701432 Aug 01 08:39:36 PM PDT 24 Aug 01 08:57:03 PM PDT 24 5527344128 ps
T1230 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1837223779 Aug 01 08:19:55 PM PDT 24 Aug 01 08:25:09 PM PDT 24 3789013138 ps
T1231 /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.2353601015 Aug 01 08:43:56 PM PDT 24 Aug 01 09:23:35 PM PDT 24 10883012216 ps
T1232 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.1522384907 Aug 01 08:39:55 PM PDT 24 Aug 01 08:45:00 PM PDT 24 2581687070 ps
T1233 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.740681021 Aug 01 08:46:08 PM PDT 24 Aug 01 08:53:39 PM PDT 24 6286464207 ps
T286 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.3367800092 Aug 01 08:20:01 PM PDT 24 Aug 01 08:35:29 PM PDT 24 6541387260 ps
T1234 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3505308786 Aug 01 08:22:50 PM PDT 24 Aug 01 09:34:10 PM PDT 24 15601376550 ps
T1235 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2666047788 Aug 01 08:22:01 PM PDT 24 Aug 01 09:26:10 PM PDT 24 14870927266 ps
T1236 /workspace/coverage/default/1.chip_sw_kmac_app_rom.470692373 Aug 01 08:27:29 PM PDT 24 Aug 01 08:31:48 PM PDT 24 2787337736 ps
T1237 /workspace/coverage/default/2.rom_e2e_asm_init_rma.2608494234 Aug 01 08:44:52 PM PDT 24 Aug 01 09:34:56 PM PDT 24 14851566365 ps
T124 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2254691533 Aug 01 08:18:17 PM PDT 24 Aug 01 08:25:19 PM PDT 24 5637533080 ps
T1238 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.89522281 Aug 01 08:26:16 PM PDT 24 Aug 01 08:31:13 PM PDT 24 3374604180 ps
T1239 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.607370685 Aug 01 08:32:57 PM PDT 24 Aug 01 09:17:11 PM PDT 24 13465344530 ps
T1240 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1190599039 Aug 01 08:46:34 PM PDT 24 Aug 01 08:52:22 PM PDT 24 4547617908 ps
T1241 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3752395037 Aug 01 08:21:04 PM PDT 24 Aug 01 08:33:29 PM PDT 24 9926771900 ps
T1242 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1386007052 Aug 01 08:15:23 PM PDT 24 Aug 01 08:22:42 PM PDT 24 17939034586 ps
T203 /workspace/coverage/default/1.chip_sw_power_virus.656455052 Aug 01 08:33:15 PM PDT 24 Aug 01 08:56:23 PM PDT 24 5646975546 ps
T1243 /workspace/coverage/default/1.chip_sw_aes_masking_off.55072953 Aug 01 08:23:16 PM PDT 24 Aug 01 08:28:57 PM PDT 24 2990353383 ps
T788 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3891095799 Aug 01 08:44:15 PM PDT 24 Aug 01 08:51:02 PM PDT 24 3579859680 ps
T1244 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.34078572 Aug 01 08:15:01 PM PDT 24 Aug 01 08:23:55 PM PDT 24 5358737580 ps
T1245 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.1447154247 Aug 01 08:22:00 PM PDT 24 Aug 01 10:00:03 PM PDT 24 23449885950 ps
T1246 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.1397885795 Aug 01 08:25:53 PM PDT 24 Aug 01 09:10:27 PM PDT 24 12960481176 ps
T1247 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.2670155970 Aug 01 08:22:49 PM PDT 24 Aug 01 09:23:18 PM PDT 24 14423173392 ps
T205 /workspace/coverage/default/2.chip_jtag_csr_rw.3257079660 Aug 01 08:31:24 PM PDT 24 Aug 01 08:54:41 PM PDT 24 10921747590 ps
T51 /workspace/coverage/default/1.chip_jtag_csr_rw.3983648974 Aug 01 08:20:08 PM PDT 24 Aug 01 08:52:52 PM PDT 24 15769355941 ps
T1248 /workspace/coverage/default/0.rom_e2e_asm_init_dev.407578268 Aug 01 08:20:49 PM PDT 24 Aug 01 09:36:10 PM PDT 24 15492258905 ps
T745 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1263361899 Aug 01 08:48:36 PM PDT 24 Aug 01 08:56:17 PM PDT 24 3604543496 ps
T1249 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.3430514758 Aug 01 08:36:17 PM PDT 24 Aug 01 09:25:48 PM PDT 24 12625805912 ps
T1250 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.993023005 Aug 01 08:17:03 PM PDT 24 Aug 01 08:26:36 PM PDT 24 4668557915 ps
T1251 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1278733534 Aug 01 08:20:40 PM PDT 24 Aug 01 08:44:49 PM PDT 24 7816847592 ps
T1252 /workspace/coverage/default/48.chip_sw_all_escalation_resets.2974887345 Aug 01 08:47:56 PM PDT 24 Aug 01 08:56:15 PM PDT 24 4167270790 ps
T1253 /workspace/coverage/default/53.chip_sw_all_escalation_resets.2647799107 Aug 01 08:48:31 PM PDT 24 Aug 01 08:59:10 PM PDT 24 6109806206 ps
T1254 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3971189776 Aug 01 08:15:24 PM PDT 24 Aug 01 08:22:32 PM PDT 24 3486717488 ps
T1255 /workspace/coverage/default/1.chip_sw_kmac_smoketest.3770409646 Aug 01 08:29:39 PM PDT 24 Aug 01 08:34:47 PM PDT 24 3567812056 ps
T60 /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.3821553572 Aug 01 08:13:54 PM PDT 24 Aug 01 08:20:54 PM PDT 24 3490319618 ps
T814 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3575545202 Aug 01 08:47:26 PM PDT 24 Aug 01 08:53:21 PM PDT 24 3176807778 ps
T1256 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.2872531695 Aug 01 08:14:50 PM PDT 24 Aug 01 08:22:18 PM PDT 24 4815194759 ps
T798 /workspace/coverage/default/95.chip_sw_all_escalation_resets.1036277573 Aug 01 08:52:44 PM PDT 24 Aug 01 09:03:01 PM PDT 24 5229890870 ps
T1257 /workspace/coverage/default/0.chip_tap_straps_testunlock0.3793203518 Aug 01 08:14:57 PM PDT 24 Aug 01 08:29:26 PM PDT 24 8950476752 ps
T725 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3588104614 Aug 01 08:49:51 PM PDT 24 Aug 01 08:57:25 PM PDT 24 4202134870 ps
T1258 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.900165897 Aug 01 08:27:13 PM PDT 24 Aug 01 08:38:24 PM PDT 24 5025612460 ps
T777 /workspace/coverage/default/1.chip_sw_all_escalation_resets.148817669 Aug 01 08:21:10 PM PDT 24 Aug 01 08:33:09 PM PDT 24 5341966432 ps
T1259 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1170710314 Aug 01 08:15:11 PM PDT 24 Aug 01 08:23:02 PM PDT 24 3015544912 ps
T1260 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.2583913939 Aug 01 08:20:43 PM PDT 24 Aug 01 11:14:22 PM PDT 24 63217616283 ps
T345 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.3958781930 Aug 01 08:16:34 PM PDT 24 Aug 01 08:34:49 PM PDT 24 6610129504 ps
T385 /workspace/coverage/default/81.chip_sw_all_escalation_resets.3325597656 Aug 01 08:51:30 PM PDT 24 Aug 01 08:59:21 PM PDT 24 4941942274 ps
T1261 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.2198745783 Aug 01 08:26:06 PM PDT 24 Aug 01 08:30:37 PM PDT 24 2283143336 ps
T58 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.1311764767 Aug 01 08:12:31 PM PDT 24 Aug 01 08:18:19 PM PDT 24 3991845928 ps
T1262 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2822330649 Aug 01 08:25:24 PM PDT 24 Aug 01 08:44:17 PM PDT 24 10295423686 ps
T1263 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3003872271 Aug 01 08:22:24 PM PDT 24 Aug 01 08:40:41 PM PDT 24 10063709928 ps
T656 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.67746985 Aug 01 08:32:18 PM PDT 24 Aug 01 09:45:48 PM PDT 24 27104504658 ps
T1264 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1367307848 Aug 01 08:38:51 PM PDT 24 Aug 01 08:50:09 PM PDT 24 6371287360 ps
T1265 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3542449532 Aug 01 08:16:37 PM PDT 24 Aug 01 08:49:55 PM PDT 24 9828986218 ps
T1266 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3070178192 Aug 01 08:13:40 PM PDT 24 Aug 01 11:14:55 PM PDT 24 59838303750 ps
T1267 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1220518644 Aug 01 08:25:27 PM PDT 24 Aug 01 09:01:49 PM PDT 24 29514210011 ps
T726 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3054292716 Aug 01 08:52:44 PM PDT 24 Aug 01 08:58:02 PM PDT 24 3530812936 ps
T1268 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.1185647092 Aug 01 08:23:32 PM PDT 24 Aug 01 08:30:23 PM PDT 24 4124578109 ps
T1269 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2918214097 Aug 01 08:14:21 PM PDT 24 Aug 01 08:56:15 PM PDT 24 26577049007 ps
T1270 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3982402502 Aug 01 08:22:38 PM PDT 24 Aug 01 09:30:27 PM PDT 24 15540737337 ps
T1271 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.637293486 Aug 01 08:22:58 PM PDT 24 Aug 01 08:31:14 PM PDT 24 7176860540 ps
T696 /workspace/coverage/default/1.rom_raw_unlock.3876097548 Aug 01 08:30:13 PM PDT 24 Aug 01 08:34:18 PM PDT 24 6064446011 ps
T65 /workspace/coverage/default/0.chip_tap_straps_rma.3864744002 Aug 01 08:18:32 PM PDT 24 Aug 01 08:24:35 PM PDT 24 4312991756 ps
T1272 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2129685818 Aug 01 08:14:53 PM PDT 24 Aug 01 09:16:46 PM PDT 24 21157626824 ps
T1273 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.1848790062 Aug 01 08:16:57 PM PDT 24 Aug 01 09:53:12 PM PDT 24 24569275644 ps
T727 /workspace/coverage/default/51.chip_sw_all_escalation_resets.3682686395 Aug 01 08:48:46 PM PDT 24 Aug 01 08:56:50 PM PDT 24 4898478540 ps
T766 /workspace/coverage/default/21.chip_sw_all_escalation_resets.2153297441 Aug 01 08:46:07 PM PDT 24 Aug 01 08:56:58 PM PDT 24 4419798292 ps
T1274 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.1292096123 Aug 01 08:33:13 PM PDT 24 Aug 01 08:37:56 PM PDT 24 3782271128 ps
T1275 /workspace/coverage/default/1.chip_sw_flash_init.697882228 Aug 01 08:19:35 PM PDT 24 Aug 01 08:51:29 PM PDT 24 19028582246 ps
T269 /workspace/coverage/default/33.chip_sw_all_escalation_resets.312026494 Aug 01 08:46:16 PM PDT 24 Aug 01 08:56:25 PM PDT 24 5488668264 ps
T1276 /workspace/coverage/default/1.rom_e2e_asm_init_prod.3911972051 Aug 01 08:33:47 PM PDT 24 Aug 01 09:36:35 PM PDT 24 16018648257 ps
T66 /workspace/coverage/default/1.chip_tap_straps_testunlock0.2889775256 Aug 01 08:27:45 PM PDT 24 Aug 01 08:32:57 PM PDT 24 3698335469 ps
T1277 /workspace/coverage/default/1.chip_sw_uart_smoketest.3702840003 Aug 01 08:30:23 PM PDT 24 Aug 01 08:35:59 PM PDT 24 3612889844 ps
T1278 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2520524235 Aug 01 08:44:32 PM PDT 24 Aug 01 08:54:46 PM PDT 24 6766251412 ps
T1279 /workspace/coverage/default/86.chip_sw_all_escalation_resets.1933318145 Aug 01 08:53:25 PM PDT 24 Aug 01 09:04:23 PM PDT 24 5422481592 ps
T1280 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1493877109 Aug 01 08:12:44 PM PDT 24 Aug 01 08:26:54 PM PDT 24 5604346600 ps
T722 /workspace/coverage/default/55.chip_sw_all_escalation_resets.3267756937 Aug 01 08:49:07 PM PDT 24 Aug 01 09:01:31 PM PDT 24 6330374836 ps
T1281 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1540384006 Aug 01 08:31:42 PM PDT 24 Aug 01 08:35:40 PM PDT 24 3191154658 ps
T732 /workspace/coverage/default/56.chip_sw_all_escalation_resets.4294903054 Aug 01 08:49:29 PM PDT 24 Aug 01 09:03:09 PM PDT 24 4843895160 ps
T1282 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2779050921 Aug 01 08:21:17 PM PDT 24 Aug 01 09:06:34 PM PDT 24 10404377802 ps
T1283 /workspace/coverage/default/28.chip_sw_all_escalation_resets.2572188758 Aug 01 08:45:49 PM PDT 24 Aug 01 08:57:12 PM PDT 24 4991458720 ps
T1284 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1587014921 Aug 01 08:42:02 PM PDT 24 Aug 01 08:49:52 PM PDT 24 5730135453 ps
T1285 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.4103466394 Aug 01 08:14:55 PM PDT 24 Aug 01 08:26:35 PM PDT 24 6830579940 ps
T753 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3226264815 Aug 01 08:46:58 PM PDT 24 Aug 01 08:53:59 PM PDT 24 4167151368 ps
T1286 /workspace/coverage/default/76.chip_sw_all_escalation_resets.2447054694 Aug 01 08:52:14 PM PDT 24 Aug 01 09:00:22 PM PDT 24 6227292536 ps
T1287 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1165023329 Aug 01 08:42:37 PM PDT 24 Aug 01 08:51:44 PM PDT 24 6918645856 ps
T1288 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.4089346967 Aug 01 08:21:56 PM PDT 24 Aug 01 08:30:22 PM PDT 24 6930480756 ps
T1289 /workspace/coverage/default/3.chip_sw_uart_tx_rx.2916358199 Aug 01 08:42:27 PM PDT 24 Aug 01 08:54:07 PM PDT 24 4306285440 ps
T1290 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1175635264 Aug 01 08:41:09 PM PDT 24 Aug 01 09:08:34 PM PDT 24 9981417704 ps
T1291 /workspace/coverage/default/3.chip_tap_straps_rma.3230835637 Aug 01 08:41:42 PM PDT 24 Aug 01 08:47:09 PM PDT 24 4445181634 ps
T1292 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3550029293 Aug 01 08:49:26 PM PDT 24 Aug 01 08:56:51 PM PDT 24 3779989730 ps
T1293 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2793742579 Aug 01 08:22:21 PM PDT 24 Aug 01 08:26:11 PM PDT 24 2659712009 ps
T1294 /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.1177640356 Aug 01 08:33:29 PM PDT 24 Aug 01 08:38:24 PM PDT 24 2870330251 ps
T1295 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.3542315550 Aug 01 08:12:24 PM PDT 24 Aug 01 11:31:36 PM PDT 24 63842630323 ps
T1296 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3187810871 Aug 01 08:39:53 PM PDT 24 Aug 01 08:53:44 PM PDT 24 4157499936 ps
T1297 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.2632947235 Aug 01 08:34:39 PM PDT 24 Aug 01 08:44:39 PM PDT 24 3628686808 ps
T1298 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3948255245 Aug 01 08:37:26 PM PDT 24 Aug 01 08:52:27 PM PDT 24 7817396006 ps
T1299 /workspace/coverage/default/0.chip_sw_aes_entropy.3821235117 Aug 01 08:13:53 PM PDT 24 Aug 01 08:18:06 PM PDT 24 2327215380 ps
T317 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.698561849 Aug 01 08:38:54 PM PDT 24 Aug 01 08:45:42 PM PDT 24 3135095128 ps
T1300 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2930105440 Aug 01 08:25:00 PM PDT 24 Aug 01 09:23:35 PM PDT 24 14499246184 ps
T1301 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3536692805 Aug 01 08:21:33 PM PDT 24 Aug 01 10:03:17 PM PDT 24 17553441018 ps
T1302 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.3028477483 Aug 01 08:25:15 PM PDT 24 Aug 01 08:33:47 PM PDT 24 4777537584 ps
T254 /workspace/coverage/default/2.chip_sw_alert_test.3633440655 Aug 01 08:36:21 PM PDT 24 Aug 01 08:41:07 PM PDT 24 3611617678 ps
T1303 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.4260249243 Aug 01 08:29:42 PM PDT 24 Aug 01 08:34:23 PM PDT 24 3433335633 ps
T1304 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.598383206 Aug 01 08:11:53 PM PDT 24 Aug 01 08:29:50 PM PDT 24 8949579410 ps
T381 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1544928233 Aug 01 08:20:44 PM PDT 24 Aug 01 08:27:27 PM PDT 24 6176739990 ps
T1305 /workspace/coverage/default/2.chip_sw_edn_auto_mode.1014251203 Aug 01 08:35:29 PM PDT 24 Aug 01 08:58:09 PM PDT 24 4786626724 ps
T1306 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3385917056 Aug 01 08:24:35 PM PDT 24 Aug 01 08:47:57 PM PDT 24 6546797010 ps
T809 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3598679416 Aug 01 08:51:22 PM PDT 24 Aug 01 08:58:02 PM PDT 24 4390263500 ps
T737 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2744414887 Aug 01 08:50:43 PM PDT 24 Aug 01 08:57:17 PM PDT 24 3939777890 ps
T1307 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2808964217 Aug 01 08:33:15 PM PDT 24 Aug 01 09:32:50 PM PDT 24 14846575920 ps
T1308 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.2220763888 Aug 01 08:33:13 PM PDT 24 Aug 01 08:36:10 PM PDT 24 3333111240 ps
T1309 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2412039529 Aug 01 08:34:13 PM PDT 24 Aug 01 08:47:07 PM PDT 24 6814935440 ps
T1310 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.1322705932 Aug 01 08:23:59 PM PDT 24 Aug 01 08:32:23 PM PDT 24 4565183076 ps
T1311 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.133641115 Aug 01 08:22:59 PM PDT 24 Aug 01 10:06:21 PM PDT 24 23705342023 ps
T1312 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.61517972 Aug 01 08:39:50 PM PDT 24 Aug 01 08:44:05 PM PDT 24 2522762850 ps
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