Unified Coverage Report :: Module :: prim_alert_sender

Module : prim_alert_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender	75.00			75.00
tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.35	96.47	89.29	87.38		100.00	63.64	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.46	98.83	84.05	97.97		79.43	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.31	99.65	66.67	90.22		100.00	90.00	u_rv_plic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.35	96.47	89.29	87.38		100.00	63.64	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.35	96.47	89.29	87.38		100.00	63.64	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.35	96.47	89.29	87.38		100.00	63.64	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T161,T102,T267	Yes	T161,T102,T267	INPUT
alert_req_i	Yes	Yes	T189,T264,T178	Yes	T189,T264,T178	INPUT
alert_ack_o	Yes	Yes	T189,T264,T178	Yes	T189,T264,T178	OUTPUT
alert_state_o	Yes	Yes	T189,T264,T178	Yes	T189,T264,T178	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T54,T93,T161	Yes	T54,T93,T161	INPUT
alert_rx_i.ping_n	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i.ping_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T54,T93,T161	Yes	T54,T93,T161	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

	Total	Covered	Percent
Totals	12	9	75.00
Total Bits	24	18	75.00
Total Bits 0->1	12	9	75.00
Total Bits 1->0	12	9	75.00

Ports	12	9	75.00
Port Bits	24	18	75.00
Port Bits 0->1	12	9	75.00
Port Bits 1->0	12	9	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
alert_req_i	No	No		No		INPUT
alert_ack_o	No	No		No		OUTPUT
alert_state_o	No	No		No		OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i.ping_n	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i.ping_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T31	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
alert_req_i	Yes	Yes	T120,T121,T123	Yes	T120,T121,T122	INPUT
alert_ack_o	Yes	Yes	T120,T121,T122	Yes	T120,T121,T122	OUTPUT
alert_state_o	Yes	Yes	T120,T121,T123	Yes	T120,T121,T122	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i.ping_n	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i.ping_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
alert_req_i	Yes	Yes	T247,T248	Yes	T247,T248,T249	INPUT
alert_ack_o	Yes	Yes	T247,T248,T249	Yes	T247,T248,T249	OUTPUT
alert_state_o	Yes	Yes	T247,T248	Yes	T247,T248,T249	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i.ping_n	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i.ping_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
alert_req_i	Yes	Yes	T387	Yes	T387	INPUT
alert_ack_o	Yes	Yes	T387	Yes	T387	OUTPUT
alert_state_o	Yes	Yes	T387	Yes	T387	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i.ping_n	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i.ping_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T161,T102,T267	Yes	T161,T102,T267	INPUT
alert_req_i	Yes	Yes	T108	Yes	T108	INPUT
alert_ack_o	Yes	Yes	T108	Yes	T108	OUTPUT
alert_state_o	Yes	Yes	T108	Yes	T108	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T54,T93,T161	Yes	T54,T93,T161	INPUT
alert_rx_i.ping_n	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i.ping_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T54,T93,T161	Yes	T54,T93,T161	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	INPUT
alert_req_i	Yes	Yes	T189,T264,T178	Yes	T189,T264,T178	INPUT
alert_ack_o	Yes	Yes	T189,T264,T178	Yes	T189,T264,T178	OUTPUT
alert_state_o	Yes	Yes	T189,T264,T178	Yes	T189,T264,T178	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T54,T189,T264	Yes	T54,T189,T264	INPUT
alert_rx_i.ping_n	Yes	Yes	T54,T93,T94	Yes	T54,T94,T277	INPUT
alert_rx_i.ping_p	Yes	Yes	T54,T94,T277	Yes	T54,T93,T94	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T54,T189,T264	Yes	T54,T189,T264	OUTPUT