Unified Coverage Report :: Module :: rv_core_ibex

Module : rv_core_ibex

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.14	96.47	89.29	86.30		100.00	63.64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex	87.35	96.47	89.29	87.38		100.00	63.64

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.35	96.47	89.29	87.38		100.00	63.64

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.38	96.51	81.88	90.33		96.77	91.43

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.22	92.47		87.18			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
fifo_d	100.00	100.00	100.00			100.00	100.00
fifo_i	93.75	75.00	100.00			100.00	100.00
gen_alert_senders[0].u_alert_sender	100.00			100.00
gen_alert_senders[1].u_alert_sender	100.00			100.00
gen_alert_senders[2].u_alert_sender	100.00			100.00
gen_alert_senders[3].u_alert_sender	75.00			75.00
tl_adapter_host_d_ibex	91.79	95.35	81.82			90.00	100.00
tl_adapter_host_i_ibex	87.90	90.48	72.22			88.89	100.00
u_alert_nmi_sync	100.00	100.00				100.00
u_core	95.66			95.66
u_core_sleeping_buf	100.00	100.00
u_dbus_trans	96.36	100.00	92.59			100.00	92.86
u_edn_if	89.08	100.00	86.44			94.87	75.00
u_ibus_trans	96.36	100.00	92.59			100.00	92.86
u_intr_timer_sync	100.00	100.00				100.00
u_lc_sync	100.00	100.00				100.00	100.00
u_prim_buf_irq	100.00	100.00
u_prim_esc_receiver	100.00			100.00
u_prim_lc_sender	100.00	100.00				100.00
u_prim_sync_reqack_data	91.67	100.00	66.67			100.00	100.00
u_pwrmgr_sync	100.00	100.00				100.00	100.00
u_reg_cfg	93.44	96.56	80.55			96.64	100.00
u_sim_win_rsp	89.32	77.27	80.00			100.00	100.00
u_tlul_req_buf	100.00	100.00
u_tlul_rsp_buf	100.00	100.00
u_wdog_nmi_sync	100.00	100.00				100.00

Line Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	82	96.47
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	492	3	3	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
ALWAYS	518	8	8	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	726	1	1	100.00
CONT_ASSIGN	728	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	752	1	1	100.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	757	1	1	100.00
CONT_ASSIGN	760	1	1	100.00
ALWAYS	792	11	11	100.00
ALWAYS	808	7	7	100.00
CONT_ASSIGN	819	1	1	100.00
CONT_ASSIGN	838	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	843	1	0	0.00
CONT_ASSIGN	847	0	0
CONT_ASSIGN	886	1	1	100.00
ALWAYS	945	0	0
CONT_ASSIGN	986	1	0	0.00
CONT_ASSIGN	988	1	0	0.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
492	1	1
493	1	1
495	1	1
512	1	1
513	1	1
514	1	1
515	1	1
518	1	1
519	1	1
520	1	1
521	1	1
522	1	1
523	1	1
524	1	1
525	1	1
			MISSING_ELSE
702	2	2
703	2	2
704	2	2
708	2	2
709	2	2
710	2	2
717	1	1
718	1	1
719	1	1
722	1	1
724	1	1
726	1	1
728	1	1
735	1	1
737	1	1
739	1	1
741	1	1
751	1	1
752	1	1
753	1	1
754	1	1
757	1	1
760	1	1
792	1	1
793	1	1
794	1	1
796	1	1
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE
808	1	1
809	1	1
810	1	1
811	1	1
813	1	1
814	1	1
815	1	1
819	1	1
838	1	1
839	1	1
840	1	1
843	0	1
847		unreachable
886	1	1
945		unreachable
946		unreachable
947		unreachable
948		unreachable
			==> MISSING_ELSE
986	0	1
988	0	1
990	1	1
992	1	1
994	1	1

---

Cond Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T189,T178,T263
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T264,T265,T133
1	0	Covered	T150,T41,T266

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T150,T41,T266

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T161,T102,T267
1	0	Covered	T1,T2,T3
1	1	Covered	T102,T103,T104

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T102,T103,T104
1	0	Covered	T1,T2,T3
1	1	Covered	T161,T102,T267

 LINE       739
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T161,T102,T267
1	0	Covered	T1,T2,T3
1	1	Covered	T102,T103,T104

 LINE       741
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T161,T102,T267
1	0	Covered	T1,T2,T3
1	1	Covered	T102,T103,T104

 LINE       753
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T150,T41,T266
0	1	0	Covered	T189,T178,T263
1	0	0	Covered	T268,T269,T270

 LINE       800
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T54
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Totals	123	91	73.98
Total Bits	1628	1405	86.30
Total Bits 0->1	814	703	86.36
Total Bits 1->0	814	702	86.24

Ports	123	91	73.98
Port Bits	1628	1405	86.30
Port Bits 0->1	814	703	86.36
Port Bits 1->0	814	702	86.24

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
clk_esc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_esc_ni	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
rst_cpu_n_o	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	No	No		No		OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	No	No		No		OUTPUT
corei_tl_h_o.a_mask[3:0]	No	No		No		OUTPUT
corei_tl_h_o.a_address[1:0]	No	No		No		OUTPUT
corei_tl_h_o.a_address[16:2]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_address[18:17]	No	No		No		OUTPUT
corei_tl_h_o.a_address[19]	No	No		Yes	T271,T272,T273	OUTPUT
corei_tl_h_o.a_address[27:20]	No	No		No		OUTPUT
corei_tl_h_o.a_address[29:28]	Yes	Yes	*T189,*T169,*T263	Yes	T189,T169,T263	OUTPUT
corei_tl_h_o.a_address[31:30]	No	No		No		OUTPUT
corei_tl_h_o.a_source[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_source[5:3]	No	No		No		OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	No	No		No		OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	No	No		No		OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_error	Yes	Yes	T31,T187,T188	Yes	T31,T187,T188	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_user.rsp_intg[5:0]	Yes	Yes	*T31,*T187,*T189	Yes	T31,T187,T189	INPUT
corei_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_sink	No	No		No		INPUT
corei_tl_h_i.d_source[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_source[5:3]	No	No		No		INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[0]	No	No		No		INPUT
corei_tl_h_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T49,T52,T53	Yes	T49,T52,T53	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T49,T53,T190	Yes	T49,T53,T190	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T49,T53,T190	Yes	T49,T53,T190	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T49,T53,T190	Yes	T49,T53,T190	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_opcode[1]	No	No		No		OUTPUT
cored_tl_h_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_error	Yes	Yes	T1,T4,T31	Yes	T1,T4,T31	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_sink	No	No		No		INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
irq_software_i	Yes	Yes	T253,T261,T262	Yes	T253,T261,T262	INPUT
irq_timer_i	Yes	Yes	T3,T98,T274	Yes	T3,T98,T274	INPUT
irq_external_i	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	INPUT
esc_tx_i.esc_n	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	INPUT
esc_tx_i.esc_p	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	INPUT
esc_rx_o.resp_n	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	OUTPUT
nmi_wdog_i	Yes	Yes	T275,T266,T276	Yes	T275,T266,T276	INPUT
debug_req_i	Yes	Yes	T191,T51,T192	Yes	T191,T51,T192	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.cmd_intg[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.cmd_intg[1]	No	No		No		INPUT
cfg_tl_d_i.a_user.cmd_intg[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.instr_type[2:1]	No	No		No		INPUT
cfg_tl_d_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[1:0]	No	No		No		INPUT
cfg_tl_d_i.a_address[7:2]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[1:0]	Yes	Yes	*T208,*T108,*T1	Yes	T208,T108,T1	INPUT
cfg_tl_d_i.a_source[5:2]	No	No		No		INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[0]	No	No		No		INPUT
cfg_tl_d_i.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[1:0]	No	No		No		INPUT
cfg_tl_d_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T108	Yes	T108	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[2:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[3]	No	No		No		OUTPUT
cfg_tl_d_o.d_user.rsp_intg[5:4]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	OUTPUT
cfg_tl_d_o.d_sink	No	No		No		OUTPUT
cfg_tl_d_o.d_source[1:0]	Yes	Yes	*T108,*T1,*T2	Yes	T208,T108,T1	OUTPUT
cfg_tl_d_o.d_source[5:2]	No	No		No		OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[0]	No	No		No		OUTPUT
cfg_tl_d_o.d_size[1]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T1,T54,T60	Yes	T1,T3,T54	INPUT
edn_i.edn_fips	Yes	Yes	T61,T63,T68	Yes	T61,T63,T68	INPUT
edn_i.edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
icache_otp_key_o.req	Yes	Yes	T169,T180,T181	Yes	T169,T180,T181	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T4,T54,T31	Yes	T3,T4,T54	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T2,T4,T54	Yes	T2,T4,T54	INPUT
icache_otp_key_i.ack	Yes	Yes	T180,T181,T182	Yes	T180,T181,T182	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T54,T93,T161	Yes	T54,T93,T161	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T54,T189,T264	Yes	T54,T189,T264	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T54,T93,T94	Yes	T54,T94,T277	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T54,T94,T277	Yes	T54,T93,T94	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T54,T93,T161	Yes	T54,T93,T161	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T54,T189,T264	Yes	T54,T189,T264	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	492	2	2	100.00
IF	518	3	3	100.00
IF	796	3	3	100.00
IF	808	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T150,T41,T266
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	492	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	518	if ((!rst_ni))
-2-:	522	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T264,T265,T133
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	796	if (reg2hw.rnd_data.re)
-2-:	800	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T54
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	808	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	14	63.64
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	14	63.64

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	529253896	6	0	0
FpvSecCmIbexFetchEnable1_A	529253896	25292825	0	98
FpvSecCmIbexFetchEnable2_A	529253896	67006284	0	88
FpvSecCmIbexFetchEnable3Rev_A	529253896	457577337	0	2036
FpvSecCmIbexFetchEnable3_A	529253896	457579255	0	1928
FpvSecCmIbexInstrIntgErrCheck_A	529253896	0	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	529253896	590	0	0
FpvSecCmIbexLockstepResetCountAlertCheck_A	529253896	0	0	0
FpvSecCmIbexPcMismatchCheck_A	529253896	0	0	0
FpvSecCmIbexRfEccErrCheck_A	529253896	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	529253896	0	0	0
FpvSecCmRegWeOnehotCheck_A	529253896	3	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	529253896	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	529253896	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	529253896	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	1027	1027	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	1027	1027	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	1027	1027	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	1027	1027	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	1027	1027	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	529253896	189	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	529253896	196	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	6	0	0
T133	0	1	0	0
T172	181652	0	0	0
T180	85955	0	0	0
T251	225753	0	0	0
T252	194675	0	0	0
T264	280087	1	0	0
T265	0	1	0	0
T276	184991	0	0	0
T278	0	1	0	0
T279	0	1	0	0
T280	0	1	0	0
T281	955032	0	0	0
T282	177753	0	0	0
T283	159082	0	0	0
T284	240871	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	25292825	0	98
T1	219930	41111	0	0
T2	610375	9927	0	0
T3	82768	9927	0	0
T4	266866	41099	0	0
T31	233232	40604	0	0
T41	0	0	0	2
T43	0	0	0	2
T49	0	0	0	2
T54	493951	19850	0	0
T58	450658	19858	0	0
T59	131504	19842	0	0
T60	152022	9927	0	0
T89	0	0	0	2
T90	0	0	0	2
T119	237771	40603	0	0
T140	0	0	0	2
T166	0	0	0	2
T176	0	0	0	2
T285	0	0	0	2
T286	0	0	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	67006284	0	88
T1	219930	69554	0	0
T2	610375	34775	0	0
T3	82768	34775	0	0
T4	266866	69550	0	0
T6	0	0	0	2
T31	233232	69555	0	0
T41	0	0	0	2
T43	0	0	0	2
T49	0	0	0	2
T54	493951	88754	0	0
T58	450658	69555	0	0
T59	131504	69555	0	0
T60	152022	38308	0	0
T90	0	0	0	2
T119	237771	69555	0	0
T176	0	0	0	2
T285	0	0	0	2
T287	0	0	0	2
T288	0	0	0	2
T289	0	0	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	457577337	0	2036
T1	219930	129001	0	2
T2	610375	575539	0	2
T3	82768	47932	0	2
T4	266866	175956	0	2
T31	233232	142801	0	2
T54	493951	405074	0	2
T58	450658	380985	0	2
T59	131504	61845	0	2
T60	152022	113652	0	2
T119	237771	147351	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	457579255	0	1928
T1	219930	129003	0	2
T2	610375	575540	0	2
T3	82768	47933	0	2
T4	266866	175957	0	2
T31	233232	142803	0	2
T54	493951	405084	0	2
T58	450658	380987	0	2
T59	131504	61847	0	2
T60	152022	113654	0	2
T119	237771	147352	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	590	0	0
T61	187671	0	0	0
T62	219065	0	0	0
T70	449487	0	0	0
T84	214917	0	0	0
T151	137724	0	0	0
T178	0	32	0	0
T179	0	31	0	0
T189	276303	1	0	0
T202	69707	0	0	0
T215	251708	0	0	0
T263	0	1	0	0
T290	0	99	0	0
T291	0	32	0	0
T292	0	32	0	0
T293	0	1	0	0
T294	0	98	0	0
T295	0	32	0	0
T296	378326	0	0	0
T297	316352	0	0	0

FpvSecCmIbexLockstepResetCountAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	3	0	0
T20	110764	0	0	0
T34	145811	0	0	0
T43	193370	0	0	0
T268	260476	1	0	0
T269	0	1	0	0
T270	0	1	0	0
T298	245685	0	0	0
T299	247425	0	0	0
T300	142442	0	0	0
T301	79048	0	0	0
T302	341089	0	0	0
T303	422355	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T54	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T119	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T54	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T119	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T54	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T119	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T54	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T119	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T54	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T119	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	189	0	0
T49	114604	0	0	0
T180	85955	49	0	0
T181	0	33	0	0
T182	0	33	0	0
T252	194675	0	0	0
T276	184991	0	0	0
T283	159082	0	0	0
T284	240871	0	0	0
T304	0	20	0	0
T305	0	33	0	0
T306	0	21	0	0
T307	158267	0	0	0
T308	78015	0	0	0
T309	342987	0	0	0
T310	290563	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	196	0	0
T113	193480	0	0	0
T169	299176	16	0	0
T180	0	12	0	0
T181	0	42	0	0
T182	0	42	0	0
T194	278143	0	0	0
T204	219545	0	0	0
T210	0	16	0	0
T211	0	16	0	0
T266	491685	0	0	0
T304	0	5	0	0
T305	0	42	0	0
T306	0	5	0	0
T311	134068	0	0	0
T312	129968	0	0	0
T313	181719	0	0	0
T314	73627	0	0	0
T315	169102	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	82	96.47
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	492	3	3	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
ALWAYS	518	8	8	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	726	1	1	100.00
CONT_ASSIGN	728	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	752	1	1	100.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	757	1	1	100.00
CONT_ASSIGN	760	1	1	100.00
ALWAYS	792	11	11	100.00
ALWAYS	808	7	7	100.00
CONT_ASSIGN	819	1	1	100.00
CONT_ASSIGN	838	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	843	1	0	0.00
CONT_ASSIGN	847	0	0
CONT_ASSIGN	886	1	1	100.00
ALWAYS	945	0	0
CONT_ASSIGN	986	1	0	0.00
CONT_ASSIGN	988	1	0	0.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
492	1	1
493	1	1
495	1	1
512	1	1
513	1	1
514	1	1
515	1	1
518	1	1
519	1	1
520	1	1
521	1	1
522	1	1
523	1	1
524	1	1
525	1	1
			MISSING_ELSE
702	2	2
703	2	2
704	2	2
708	2	2
709	2	2
710	2	2
717	1	1
718	1	1
719	1	1
722	1	1
724	1	1
726	1	1
728	1	1
735	1	1
737	1	1
739	1	1
741	1	1
751	1	1
752	1	1
753	1	1
754	1	1
757	1	1
760	1	1
792	1	1
793	1	1
794	1	1
796	1	1
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE
808	1	1
809	1	1
810	1	1
811	1	1
813	1	1
814	1	1
815	1	1
819	1	1
838	1	1
839	1	1
840	1	1
843	0	1
847		unreachable
886	1	1
945		unreachable
946		unreachable
947		unreachable
948		unreachable
			==> MISSING_ELSE
986	0	1
988	0	1
990	1	1
992	1	1
994	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T189,T178,T263
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T264,T265,T133
1	0	Covered	T150,T41,T266

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T150,T41,T266

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T161,T102,T267
1	0	Covered	T1,T2,T3
1	1	Covered	T102,T103,T104

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T102,T103,T104
1	0	Covered	T1,T2,T3
1	1	Covered	T161,T102,T267

 LINE       739
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T161,T102,T267
1	0	Covered	T1,T2,T3
1	1	Covered	T102,T103,T104

 LINE       741
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T161,T102,T267
1	0	Covered	T1,T2,T3
1	1	Covered	T102,T103,T104

 LINE       753
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T150,T41,T266
0	1	0	Covered	T189,T178,T263
1	0	0	Covered	T268,T269,T270

 LINE       800
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T54
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Totals	119	91	76.47
Total Bits	1608	1405	87.38
Total Bits 0->1	804	703	87.44
Total Bits 1->0	804	702	87.31

Ports	119	91	76.47
Port Bits	1608	1405	87.38
Port Bits 0->1	804	703	87.44
Port Bits 1->0	804	702	87.31

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
clk_esc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_esc_ni	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
rst_cpu_n_o	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	No	No		No		OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	No	No		No		OUTPUT
corei_tl_h_o.a_mask[3:0]	No	No		No		OUTPUT
corei_tl_h_o.a_address[1:0]	No	No		No		OUTPUT
corei_tl_h_o.a_address[16:2]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_address[18:17]	No	No		No		OUTPUT
corei_tl_h_o.a_address[19]	No	No		Yes	T271,T272,T273	OUTPUT
corei_tl_h_o.a_address[27:20]	No	No		No		OUTPUT
corei_tl_h_o.a_address[29:28]	Yes	Yes	*T189,*T169,*T263	Yes	T189,T169,T263	OUTPUT
corei_tl_h_o.a_address[31:30]	No	No		No		OUTPUT
corei_tl_h_o.a_source[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_source[5:3]	No	No		No		OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	No	No		No		OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	No	No		No		OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_error	Yes	Yes	T31,T187,T188	Yes	T31,T187,T188	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_user.rsp_intg[5:0]	Yes	Yes	*T31,*T187,*T189	Yes	T31,T187,T189	INPUT
corei_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_sink	No	No		No		INPUT
corei_tl_h_i.d_source[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_source[5:3]	No	No		No		INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[0]	No	No		No		INPUT
corei_tl_h_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T49,T52,T53	Yes	T49,T52,T53	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T49,T53,T190	Yes	T49,T53,T190	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T49,T53,T190	Yes	T49,T53,T190	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T49,T53,T190	Yes	T49,T53,T190	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_opcode[1]	No	No		No		OUTPUT
cored_tl_h_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_error	Yes	Yes	T1,T4,T31	Yes	T1,T4,T31	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_sink	No	No		No		INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
irq_software_i	Yes	Yes	T253,T261,T262	Yes	T253,T261,T262	INPUT
irq_timer_i	Yes	Yes	T3,T98,T274	Yes	T3,T98,T274	INPUT
irq_external_i	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	INPUT
esc_tx_i.esc_n	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	INPUT
esc_tx_i.esc_p	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	INPUT
esc_rx_o.resp_n	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	OUTPUT
nmi_wdog_i	Yes	Yes	T275,T266,T276	Yes	T275,T266,T276	INPUT
debug_req_i	Yes	Yes	T191,T51,T192	Yes	T191,T51,T192	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.cmd_intg[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.cmd_intg[1]	No	No		No		INPUT
cfg_tl_d_i.a_user.cmd_intg[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.instr_type[2:1]	No	No		No		INPUT
cfg_tl_d_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[1:0]	No	No		No		INPUT
cfg_tl_d_i.a_address[7:2]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[1:0]	Yes	Yes	*T208,*T108,*T1	Yes	T208,T108,T1	INPUT
cfg_tl_d_i.a_source[5:2]	No	No		No		INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[0]	No	No		No		INPUT
cfg_tl_d_i.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[1:0]	No	No		No		INPUT
cfg_tl_d_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T108	Yes	T108	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[2:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[3]	No	No		No		OUTPUT
cfg_tl_d_o.d_user.rsp_intg[5:4]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	OUTPUT
cfg_tl_d_o.d_sink	No	No		No		OUTPUT
cfg_tl_d_o.d_source[1:0]	Yes	Yes	*T108,*T1,*T2	Yes	T208,T108,T1	OUTPUT
cfg_tl_d_o.d_source[5:2]	No	No		No		OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[0]	No	No		No		OUTPUT
cfg_tl_d_o.d_size[1]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T1,T54,T60	Yes	T1,T3,T54	INPUT
edn_i.edn_fips	Yes	Yes	T61,T63,T68	Yes	T61,T63,T68	INPUT
edn_i.edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
icache_otp_key_o.req	Yes	Yes	T169,T180,T181	Yes	T169,T180,T181	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T4,T54,T31	Yes	T3,T4,T54	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T2,T4,T54	Yes	T2,T4,T54	INPUT
icache_otp_key_i.ack	Yes	Yes	T180,T181,T182	Yes	T180,T181,T182	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T54,T93,T161	Yes	T54,T93,T161	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T54,T189,T264	Yes	T54,T189,T264	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T54,T93,T94	Yes	T54,T94,T277	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T54,T94,T277	Yes	T54,T93,T94	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T54,T93,T161	Yes	T54,T93,T161	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T54,T189,T264	Yes	T54,T189,T264	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	492	2	2	100.00
IF	518	3	3	100.00
IF	796	3	3	100.00
IF	808	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T150,T41,T266
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	492	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	518	if ((!rst_ni))
-2-:	522	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T264,T265,T133
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	796	if (reg2hw.rnd_data.re)
-2-:	800	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T54
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	808	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	14	63.64
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	14	63.64

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	529253896	6	0	0
FpvSecCmIbexFetchEnable1_A	529253896	25292825	0	98
FpvSecCmIbexFetchEnable2_A	529253896	67006284	0	88
FpvSecCmIbexFetchEnable3Rev_A	529253896	457577337	0	2036
FpvSecCmIbexFetchEnable3_A	529253896	457579255	0	1928
FpvSecCmIbexInstrIntgErrCheck_A	529253896	0	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	529253896	590	0	0
FpvSecCmIbexLockstepResetCountAlertCheck_A	529253896	0	0	0
FpvSecCmIbexPcMismatchCheck_A	529253896	0	0	0
FpvSecCmIbexRfEccErrCheck_A	529253896	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	529253896	0	0	0
FpvSecCmRegWeOnehotCheck_A	529253896	3	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	529253896	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	529253896	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	529253896	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	1027	1027	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	1027	1027	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	1027	1027	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	1027	1027	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	1027	1027	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	529253896	189	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	529253896	196	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	6	0	0
T133	0	1	0	0
T172	181652	0	0	0
T180	85955	0	0	0
T251	225753	0	0	0
T252	194675	0	0	0
T264	280087	1	0	0
T265	0	1	0	0
T276	184991	0	0	0
T278	0	1	0	0
T279	0	1	0	0
T280	0	1	0	0
T281	955032	0	0	0
T282	177753	0	0	0
T283	159082	0	0	0
T284	240871	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	25292825	0	98
T1	219930	41111	0	0
T2	610375	9927	0	0
T3	82768	9927	0	0
T4	266866	41099	0	0
T31	233232	40604	0	0
T41	0	0	0	2
T43	0	0	0	2
T49	0	0	0	2
T54	493951	19850	0	0
T58	450658	19858	0	0
T59	131504	19842	0	0
T60	152022	9927	0	0
T89	0	0	0	2
T90	0	0	0	2
T119	237771	40603	0	0
T140	0	0	0	2
T166	0	0	0	2
T176	0	0	0	2
T285	0	0	0	2
T286	0	0	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	67006284	0	88
T1	219930	69554	0	0
T2	610375	34775	0	0
T3	82768	34775	0	0
T4	266866	69550	0	0
T6	0	0	0	2
T31	233232	69555	0	0
T41	0	0	0	2
T43	0	0	0	2
T49	0	0	0	2
T54	493951	88754	0	0
T58	450658	69555	0	0
T59	131504	69555	0	0
T60	152022	38308	0	0
T90	0	0	0	2
T119	237771	69555	0	0
T176	0	0	0	2
T285	0	0	0	2
T287	0	0	0	2
T288	0	0	0	2
T289	0	0	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	457577337	0	2036
T1	219930	129001	0	2
T2	610375	575539	0	2
T3	82768	47932	0	2
T4	266866	175956	0	2
T31	233232	142801	0	2
T54	493951	405074	0	2
T58	450658	380985	0	2
T59	131504	61845	0	2
T60	152022	113652	0	2
T119	237771	147351	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	457579255	0	1928
T1	219930	129003	0	2
T2	610375	575540	0	2
T3	82768	47933	0	2
T4	266866	175957	0	2
T31	233232	142803	0	2
T54	493951	405084	0	2
T58	450658	380987	0	2
T59	131504	61847	0	2
T60	152022	113654	0	2
T119	237771	147352	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	590	0	0
T61	187671	0	0	0
T62	219065	0	0	0
T70	449487	0	0	0
T84	214917	0	0	0
T151	137724	0	0	0
T178	0	32	0	0
T179	0	31	0	0
T189	276303	1	0	0
T202	69707	0	0	0
T215	251708	0	0	0
T263	0	1	0	0
T290	0	99	0	0
T291	0	32	0	0
T292	0	32	0	0
T293	0	1	0	0
T294	0	98	0	0
T295	0	32	0	0
T296	378326	0	0	0
T297	316352	0	0	0

FpvSecCmIbexLockstepResetCountAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	3	0	0
T20	110764	0	0	0
T34	145811	0	0	0
T43	193370	0	0	0
T268	260476	1	0	0
T269	0	1	0	0
T270	0	1	0	0
T298	245685	0	0	0
T299	247425	0	0	0
T300	142442	0	0	0
T301	79048	0	0	0
T302	341089	0	0	0
T303	422355	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T54	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T119	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T54	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T119	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T54	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T119	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T54	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T119	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T54	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T119	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	189	0	0
T49	114604	0	0	0
T180	85955	49	0	0
T181	0	33	0	0
T182	0	33	0	0
T252	194675	0	0	0
T276	184991	0	0	0
T283	159082	0	0	0
T284	240871	0	0	0
T304	0	20	0	0
T305	0	33	0	0
T306	0	21	0	0
T307	158267	0	0	0
T308	78015	0	0	0
T309	342987	0	0	0
T310	290563	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	196	0	0
T113	193480	0	0	0
T169	299176	16	0	0
T180	0	12	0	0
T181	0	42	0	0
T182	0	42	0	0
T194	278143	0	0	0
T204	219545	0	0	0
T210	0	16	0	0
T211	0	16	0	0
T266	491685	0	0	0
T304	0	5	0	0
T305	0	42	0	0
T306	0	5	0	0
T311	134068	0	0	0
T312	129968	0	0	0
T313	181719	0	0	0
T314	73627	0	0	0
T315	169102	0	0	0