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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.45 92.87 82.58 90.73 94.73 97.35 84.43


Total test records in report: 1027
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T102 /workspace/coverage/default/0.chip_sw_alert_test.2202484433 Aug 03 07:12:14 PM PDT 24 Aug 03 07:16:35 PM PDT 24 3158620820 ps
T574 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.1227512161 Aug 03 07:44:36 PM PDT 24 Aug 03 07:54:14 PM PDT 24 3748446454 ps
T575 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.1966449596 Aug 03 07:12:01 PM PDT 24 Aug 03 07:15:09 PM PDT 24 2809756440 ps
T576 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.1619675489 Aug 03 07:31:14 PM PDT 24 Aug 03 07:36:03 PM PDT 24 2614147403 ps
T120 /workspace/coverage/default/8.chip_sw_all_escalation_resets.4284789042 Aug 03 07:51:40 PM PDT 24 Aug 03 08:02:28 PM PDT 24 4948500856 ps
T127 /workspace/coverage/default/2.rom_keymgr_functest.2205000982 Aug 03 07:47:10 PM PDT 24 Aug 03 07:55:17 PM PDT 24 4440400620 ps
T67 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.648598797 Aug 03 07:29:56 PM PDT 24 Aug 03 08:02:59 PM PDT 24 25362743486 ps
T128 /workspace/coverage/default/0.chip_sw_aon_timer_irq.952541811 Aug 03 07:09:30 PM PDT 24 Aug 03 07:15:46 PM PDT 24 4065899010 ps
T129 /workspace/coverage/default/0.chip_sw_kmac_app_rom.2121297538 Aug 03 07:12:24 PM PDT 24 Aug 03 07:16:04 PM PDT 24 2403402652 ps
T130 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.2618884515 Aug 03 07:30:07 PM PDT 24 Aug 03 08:07:16 PM PDT 24 11375614032 ps
T131 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2779256217 Aug 03 07:41:44 PM PDT 24 Aug 03 07:54:29 PM PDT 24 8858181636 ps
T132 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.4180208655 Aug 03 07:51:20 PM PDT 24 Aug 03 08:11:36 PM PDT 24 8376225200 ps
T133 /workspace/coverage/default/20.chip_sw_all_escalation_resets.1086898810 Aug 03 07:51:42 PM PDT 24 Aug 03 07:59:44 PM PDT 24 3922991096 ps
T134 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.333851996 Aug 03 07:09:06 PM PDT 24 Aug 03 07:19:09 PM PDT 24 8015802626 ps
T432 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3683662705 Aug 03 07:30:38 PM PDT 24 Aug 03 07:37:27 PM PDT 24 4147718166 ps
T23 /workspace/coverage/default/0.chip_sw_usbdev_dpi.1701713436 Aug 03 07:07:33 PM PDT 24 Aug 03 07:57:22 PM PDT 24 11314226544 ps
T267 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.3781603867 Aug 03 07:39:58 PM PDT 24 Aug 03 07:49:20 PM PDT 24 5436529032 ps
T577 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1906377591 Aug 03 07:11:55 PM PDT 24 Aug 03 07:18:01 PM PDT 24 3381409900 ps
T486 /workspace/coverage/default/65.chip_sw_all_escalation_resets.1829462888 Aug 03 07:53:54 PM PDT 24 Aug 03 08:03:26 PM PDT 24 6400688680 ps
T8 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1760940568 Aug 03 07:34:31 PM PDT 24 Aug 03 07:40:06 PM PDT 24 3437011757 ps
T376 /workspace/coverage/default/2.chip_sw_uart_tx_rx.1318195253 Aug 03 07:34:13 PM PDT 24 Aug 03 07:46:10 PM PDT 24 4505254168 ps
T121 /workspace/coverage/default/98.chip_sw_all_escalation_resets.2644868640 Aug 03 07:56:29 PM PDT 24 Aug 03 08:06:00 PM PDT 24 6131388720 ps
T494 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.40865866 Aug 03 07:51:12 PM PDT 24 Aug 03 07:57:09 PM PDT 24 3543377348 ps
T578 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.4278036795 Aug 03 07:27:44 PM PDT 24 Aug 03 07:38:02 PM PDT 24 5522412750 ps
T326 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1975009390 Aug 03 07:47:25 PM PDT 24 Aug 03 07:53:32 PM PDT 24 3492565668 ps
T80 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3268983603 Aug 03 07:44:31 PM PDT 24 Aug 03 07:49:52 PM PDT 24 6953320118 ps
T220 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.4115637294 Aug 03 07:37:17 PM PDT 24 Aug 03 07:47:26 PM PDT 24 4493021912 ps
T579 /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1153524102 Aug 03 07:47:44 PM PDT 24 Aug 03 10:18:03 PM PDT 24 41088363230 ps
T327 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3212339077 Aug 03 07:28:33 PM PDT 24 Aug 03 07:51:39 PM PDT 24 7918907057 ps
T580 /workspace/coverage/default/2.chip_sw_otbn_randomness.3529979121 Aug 03 07:40:37 PM PDT 24 Aug 03 07:57:45 PM PDT 24 5693938930 ps
T581 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2004344025 Aug 03 07:23:13 PM PDT 24 Aug 03 08:25:39 PM PDT 24 15418608480 ps
T582 /workspace/coverage/default/1.chip_sw_csrng_smoketest.3534348071 Aug 03 07:38:18 PM PDT 24 Aug 03 07:41:35 PM PDT 24 2741624864 ps
T115 /workspace/coverage/default/4.chip_tap_straps_rma.3619848020 Aug 03 07:47:17 PM PDT 24 Aug 03 07:50:28 PM PDT 24 3452972247 ps
T583 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.668697599 Aug 03 07:16:06 PM PDT 24 Aug 03 07:23:06 PM PDT 24 7032547888 ps
T466 /workspace/coverage/default/40.chip_sw_all_escalation_resets.815927746 Aug 03 07:51:19 PM PDT 24 Aug 03 08:01:15 PM PDT 24 5020602576 ps
T584 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.3277108547 Aug 03 07:33:39 PM PDT 24 Aug 03 07:49:44 PM PDT 24 8564606134 ps
T585 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2113006290 Aug 03 07:49:00 PM PDT 24 Aug 03 07:51:58 PM PDT 24 2758502984 ps
T586 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3453379381 Aug 03 07:24:58 PM PDT 24 Aug 03 08:05:06 PM PDT 24 24480665300 ps
T453 /workspace/coverage/default/18.chip_sw_all_escalation_resets.1330551574 Aug 03 07:55:04 PM PDT 24 Aug 03 08:04:01 PM PDT 24 6197433614 ps
T105 /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.625003590 Aug 03 07:07:16 PM PDT 24 Aug 03 07:10:52 PM PDT 24 3367364203 ps
T191 /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.4231554011 Aug 03 07:19:34 PM PDT 24 Aug 03 07:57:00 PM PDT 24 25236100045 ps
T587 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2059436975 Aug 03 07:38:44 PM PDT 24 Aug 03 08:01:26 PM PDT 24 13965374387 ps
T86 /workspace/coverage/default/2.chip_sw_power_sleep_load.846867462 Aug 03 07:44:43 PM PDT 24 Aug 03 07:55:19 PM PDT 24 10198943580 ps
T491 /workspace/coverage/default/72.chip_sw_all_escalation_resets.159202162 Aug 03 07:54:09 PM PDT 24 Aug 03 08:03:19 PM PDT 24 5097987792 ps
T325 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1566275250 Aug 03 07:35:33 PM PDT 24 Aug 03 07:44:36 PM PDT 24 4828947981 ps
T490 /workspace/coverage/default/71.chip_sw_all_escalation_resets.514936758 Aug 03 07:53:33 PM PDT 24 Aug 03 08:01:05 PM PDT 24 5318810460 ps
T87 /workspace/coverage/default/0.chip_sw_power_sleep_load.3587493422 Aug 03 07:19:25 PM PDT 24 Aug 03 07:28:49 PM PDT 24 9793886976 ps
T373 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2337415264 Aug 03 07:07:04 PM PDT 24 Aug 03 07:17:22 PM PDT 24 4637442655 ps
T221 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.3143302156 Aug 03 07:22:47 PM PDT 24 Aug 03 07:37:00 PM PDT 24 5061715750 ps
T254 /workspace/coverage/default/2.chip_sw_pattgen_ios.1082953373 Aug 03 07:35:05 PM PDT 24 Aug 03 07:40:10 PM PDT 24 3864434852 ps
T521 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.4116026102 Aug 03 07:52:03 PM PDT 24 Aug 03 08:00:03 PM PDT 24 3074299744 ps
T436 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.245772695 Aug 03 07:24:30 PM PDT 24 Aug 03 07:26:52 PM PDT 24 2726927530 ps
T588 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3288411543 Aug 03 07:14:26 PM PDT 24 Aug 03 07:25:14 PM PDT 24 5336991228 ps
T51 /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.2647813556 Aug 03 07:18:53 PM PDT 24 Aug 03 07:56:30 PM PDT 24 26151342263 ps
T328 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3723668185 Aug 03 07:41:50 PM PDT 24 Aug 03 08:15:09 PM PDT 24 12339772700 ps
T382 /workspace/coverage/default/17.chip_sw_all_escalation_resets.1784434352 Aug 03 07:50:46 PM PDT 24 Aug 03 08:01:21 PM PDT 24 4796945800 ps
T589 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.4112285604 Aug 03 07:26:18 PM PDT 24 Aug 03 07:43:19 PM PDT 24 5689355060 ps
T332 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.248125996 Aug 03 07:12:21 PM PDT 24 Aug 03 07:38:41 PM PDT 24 8015394012 ps
T590 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.4151593911 Aug 03 07:34:50 PM PDT 24 Aug 03 07:46:10 PM PDT 24 4424015538 ps
T116 /workspace/coverage/default/0.chip_tap_straps_testunlock0.1429896370 Aug 03 07:15:43 PM PDT 24 Aug 03 07:27:20 PM PDT 24 7155034286 ps
T481 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3894122823 Aug 03 07:53:40 PM PDT 24 Aug 03 07:59:54 PM PDT 24 4016743386 ps
T244 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.712306751 Aug 03 07:09:07 PM PDT 24 Aug 03 07:18:35 PM PDT 24 4760092783 ps
T464 /workspace/coverage/default/0.chip_sw_aes_masking_off.2955727964 Aug 03 07:09:09 PM PDT 24 Aug 03 07:13:22 PM PDT 24 3274150036 ps
T329 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1131079037 Aug 03 07:13:00 PM PDT 24 Aug 03 07:32:43 PM PDT 24 6871588160 ps
T591 /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.3257137529 Aug 03 07:37:12 PM PDT 24 Aug 03 07:42:12 PM PDT 24 3177682355 ps
T592 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3001767022 Aug 03 07:24:52 PM PDT 24 Aug 03 07:33:54 PM PDT 24 5371630980 ps
T532 /workspace/coverage/default/79.chip_sw_all_escalation_resets.2861371727 Aug 03 07:54:44 PM PDT 24 Aug 03 08:02:09 PM PDT 24 5146879492 ps
T593 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.699664225 Aug 03 07:47:28 PM PDT 24 Aug 03 07:57:38 PM PDT 24 4685433188 ps
T449 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1948728064 Aug 03 07:52:31 PM PDT 24 Aug 03 07:59:25 PM PDT 24 3906896230 ps
T594 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3933070764 Aug 03 07:44:23 PM PDT 24 Aug 03 07:49:12 PM PDT 24 3825703179 ps
T226 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3419339708 Aug 03 07:37:06 PM PDT 24 Aug 03 07:50:41 PM PDT 24 5371538250 ps
T57 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1615398062 Aug 03 07:07:50 PM PDT 24 Aug 03 07:17:00 PM PDT 24 6212544829 ps
T595 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2518513874 Aug 03 07:43:26 PM PDT 24 Aug 03 08:08:01 PM PDT 24 9974557471 ps
T465 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.645715456 Aug 03 07:51:59 PM PDT 24 Aug 03 07:58:24 PM PDT 24 4230999350 ps
T596 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1787539983 Aug 03 07:32:05 PM PDT 24 Aug 03 07:35:48 PM PDT 24 2688332466 ps
T157 /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3607632421 Aug 03 07:34:54 PM PDT 24 Aug 03 10:41:07 PM PDT 24 58949412556 ps
T274 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.4075104377 Aug 03 07:21:52 PM PDT 24 Aug 03 07:28:10 PM PDT 24 3788368632 ps
T597 /workspace/coverage/default/2.rom_e2e_asm_init_prod.2579412017 Aug 03 07:48:30 PM PDT 24 Aug 03 08:41:29 PM PDT 24 15081358729 ps
T472 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1424294943 Aug 03 07:50:47 PM PDT 24 Aug 03 07:57:43 PM PDT 24 3906843636 ps
T321 /workspace/coverage/default/1.chip_sw_power_sleep_load.1985340533 Aug 03 07:31:21 PM PDT 24 Aug 03 07:41:06 PM PDT 24 10845314990 ps
T365 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.2912353270 Aug 03 07:42:50 PM PDT 24 Aug 03 08:04:07 PM PDT 24 6670510292 ps
T598 /workspace/coverage/default/1.rom_e2e_asm_init_dev.3386149901 Aug 03 07:35:16 PM PDT 24 Aug 03 08:55:06 PM PDT 24 15825063354 ps
T599 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.743697863 Aug 03 07:08:31 PM PDT 24 Aug 03 07:20:17 PM PDT 24 4128489540 ps
T287 /workspace/coverage/default/1.rom_e2e_shutdown_output.803330684 Aug 03 07:36:52 PM PDT 24 Aug 03 08:33:47 PM PDT 24 27609532296 ps
T475 /workspace/coverage/default/53.chip_sw_all_escalation_resets.1313120657 Aug 03 07:52:26 PM PDT 24 Aug 03 08:02:02 PM PDT 24 4706254684 ps
T600 /workspace/coverage/default/4.chip_sw_uart_tx_rx.2690349664 Aug 03 07:47:22 PM PDT 24 Aug 03 07:56:28 PM PDT 24 4684135960 ps
T601 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.4010890389 Aug 03 07:36:59 PM PDT 24 Aug 03 08:43:27 PM PDT 24 15689768344 ps
T602 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.2129223829 Aug 03 07:22:38 PM PDT 24 Aug 03 07:40:42 PM PDT 24 5546931024 ps
T538 /workspace/coverage/default/0.chip_sw_all_escalation_resets.3941614900 Aug 03 07:07:14 PM PDT 24 Aug 03 07:17:06 PM PDT 24 5653239992 ps
T603 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.475900538 Aug 03 07:47:13 PM PDT 24 Aug 03 08:26:28 PM PDT 24 13393106092 ps
T604 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.3483164377 Aug 03 07:25:03 PM PDT 24 Aug 03 08:30:41 PM PDT 24 14611494392 ps
T499 /workspace/coverage/default/60.chip_sw_all_escalation_resets.923041674 Aug 03 07:56:46 PM PDT 24 Aug 03 08:06:43 PM PDT 24 5574311944 ps
T605 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2743217992 Aug 03 07:42:22 PM PDT 24 Aug 03 07:54:23 PM PDT 24 4206883876 ps
T224 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2225219604 Aug 03 07:23:05 PM PDT 24 Aug 03 07:31:50 PM PDT 24 4331228930 ps
T606 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.574704425 Aug 03 07:22:01 PM PDT 24 Aug 03 07:32:45 PM PDT 24 4262354725 ps
T607 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.1852051232 Aug 03 07:43:07 PM PDT 24 Aug 03 07:51:53 PM PDT 24 6024841372 ps
T608 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3545243918 Aug 03 07:26:31 PM PDT 24 Aug 03 07:53:22 PM PDT 24 7158280750 ps
T609 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1047500956 Aug 03 07:41:41 PM PDT 24 Aug 03 08:04:42 PM PDT 24 6590343336 ps
T610 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.94745986 Aug 03 07:25:22 PM PDT 24 Aug 03 07:36:28 PM PDT 24 3792958766 ps
T611 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.242881874 Aug 03 07:27:55 PM PDT 24 Aug 03 07:31:36 PM PDT 24 2991697224 ps
T612 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1122256033 Aug 03 07:46:51 PM PDT 24 Aug 03 07:52:07 PM PDT 24 3220869022 ps
T613 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.72330206 Aug 03 07:15:26 PM PDT 24 Aug 03 07:24:53 PM PDT 24 3932961178 ps
T245 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3766081250 Aug 03 07:27:39 PM PDT 24 Aug 03 07:39:45 PM PDT 24 5040744603 ps
T207 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.734704518 Aug 03 07:41:50 PM PDT 24 Aug 03 07:55:59 PM PDT 24 7651525004 ps
T614 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.119181124 Aug 03 07:39:07 PM PDT 24 Aug 03 07:51:54 PM PDT 24 5029389450 ps
T615 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3065215935 Aug 03 07:07:28 PM PDT 24 Aug 03 07:13:09 PM PDT 24 4912742650 ps
T616 /workspace/coverage/default/0.chip_sw_csrng_smoketest.3504480267 Aug 03 07:23:06 PM PDT 24 Aug 03 07:26:53 PM PDT 24 3292572040 ps
T483 /workspace/coverage/default/50.chip_sw_all_escalation_resets.794225190 Aug 03 07:56:22 PM PDT 24 Aug 03 08:04:44 PM PDT 24 4845344740 ps
T617 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.4136183058 Aug 03 07:33:35 PM PDT 24 Aug 03 07:37:11 PM PDT 24 3035800692 ps
T618 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2570409341 Aug 03 07:13:46 PM PDT 24 Aug 03 07:21:33 PM PDT 24 4939791216 ps
T456 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.330585671 Aug 03 07:52:37 PM PDT 24 Aug 03 07:58:54 PM PDT 24 3124235446 ps
T619 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3127394309 Aug 03 07:46:22 PM PDT 24 Aug 03 07:55:16 PM PDT 24 8300499956 ps
T620 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.129897425 Aug 03 07:17:47 PM PDT 24 Aug 03 07:37:13 PM PDT 24 6071548402 ps
T621 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.1675528940 Aug 03 07:40:52 PM PDT 24 Aug 03 07:54:49 PM PDT 24 6939249280 ps
T622 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3904649558 Aug 03 07:08:34 PM PDT 24 Aug 03 07:17:04 PM PDT 24 4403095455 ps
T288 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3752960703 Aug 03 07:22:33 PM PDT 24 Aug 03 08:11:43 PM PDT 24 11543745548 ps
T623 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.163486694 Aug 03 07:49:24 PM PDT 24 Aug 03 08:00:40 PM PDT 24 11435003759 ps
T624 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1976402191 Aug 03 07:23:18 PM PDT 24 Aug 03 07:48:58 PM PDT 24 8462481184 ps
T625 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.728760487 Aug 03 07:49:50 PM PDT 24 Aug 03 08:16:06 PM PDT 24 8477436430 ps
T241 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.2723437068 Aug 03 07:21:37 PM PDT 24 Aug 03 10:43:58 PM PDT 24 64334719759 ps
T253 /workspace/coverage/default/0.chip_sw_plic_sw_irq.3194133237 Aug 03 07:14:19 PM PDT 24 Aug 03 07:20:15 PM PDT 24 3344485842 ps
T146 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1851009409 Aug 03 07:17:01 PM PDT 24 Aug 03 07:24:01 PM PDT 24 4095885352 ps
T290 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.426252102 Aug 03 07:26:00 PM PDT 24 Aug 03 07:33:57 PM PDT 24 3886831128 ps
T414 /workspace/coverage/default/0.chip_sw_edn_boot_mode.3145167082 Aug 03 07:10:59 PM PDT 24 Aug 03 07:19:27 PM PDT 24 3453713560 ps
T438 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.791921154 Aug 03 07:40:20 PM PDT 24 Aug 03 07:43:45 PM PDT 24 2862797176 ps
T439 /workspace/coverage/default/96.chip_sw_all_escalation_resets.3604793345 Aug 03 07:56:12 PM PDT 24 Aug 03 08:05:36 PM PDT 24 5798040688 ps
T440 /workspace/coverage/default/58.chip_sw_all_escalation_resets.3789328232 Aug 03 07:53:45 PM PDT 24 Aug 03 08:04:27 PM PDT 24 4817458872 ps
T437 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3589183752 Aug 03 07:07:21 PM PDT 24 Aug 03 07:08:59 PM PDT 24 2656902487 ps
T441 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3972207877 Aug 03 07:21:32 PM PDT 24 Aug 03 07:31:34 PM PDT 24 3994212976 ps
T442 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2134491477 Aug 03 07:07:45 PM PDT 24 Aug 03 07:34:19 PM PDT 24 7879476040 ps
T443 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3515243135 Aug 03 07:47:32 PM PDT 24 Aug 03 07:54:44 PM PDT 24 3785806575 ps
T626 /workspace/coverage/default/2.chip_sw_edn_kat.152823945 Aug 03 07:40:09 PM PDT 24 Aug 03 07:49:45 PM PDT 24 3419901000 ps
T32 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.853142451 Aug 03 07:36:28 PM PDT 24 Aug 03 07:39:56 PM PDT 24 2341827022 ps
T158 /workspace/coverage/default/0.rom_raw_unlock.981639924 Aug 03 07:20:12 PM PDT 24 Aug 03 07:24:11 PM PDT 24 5172164435 ps
T24 /workspace/coverage/default/2.chip_sw_gpio_smoketest.3035322619 Aug 03 07:44:56 PM PDT 24 Aug 03 07:49:28 PM PDT 24 2907678201 ps
T458 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2528449726 Aug 03 07:52:48 PM PDT 24 Aug 03 07:59:18 PM PDT 24 3870525018 ps
T461 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.124710370 Aug 03 07:54:05 PM PDT 24 Aug 03 08:01:53 PM PDT 24 4215882638 ps
T457 /workspace/coverage/default/32.chip_sw_all_escalation_resets.2914577080 Aug 03 07:50:33 PM PDT 24 Aug 03 08:00:27 PM PDT 24 4932643080 ps
T446 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3016123336 Aug 03 07:54:56 PM PDT 24 Aug 03 08:02:20 PM PDT 24 3800877216 ps
T627 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.2605788751 Aug 03 07:23:44 PM PDT 24 Aug 03 08:26:38 PM PDT 24 14946596200 ps
T291 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.343909898 Aug 03 07:29:36 PM PDT 24 Aug 03 07:37:44 PM PDT 24 5127617119 ps
T40 /workspace/coverage/default/0.chip_sw_power_virus.3812478476 Aug 03 07:25:02 PM PDT 24 Aug 03 07:47:56 PM PDT 24 5557501476 ps
T628 /workspace/coverage/default/2.chip_sw_aes_masking_off.4031792833 Aug 03 07:40:39 PM PDT 24 Aug 03 07:45:24 PM PDT 24 2714725804 ps
T82 /workspace/coverage/default/2.chip_tap_straps_testunlock0.69391836 Aug 03 07:43:21 PM PDT 24 Aug 03 07:49:34 PM PDT 24 4093726340 ps
T524 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2849370740 Aug 03 07:56:35 PM PDT 24 Aug 03 08:03:56 PM PDT 24 3774948596 ps
T478 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2245656869 Aug 03 07:53:43 PM PDT 24 Aug 03 08:00:52 PM PDT 24 4181280088 ps
T629 /workspace/coverage/default/2.chip_sw_csrng_kat_test.1738179910 Aug 03 07:41:20 PM PDT 24 Aug 03 07:45:47 PM PDT 24 2994406426 ps
T630 /workspace/coverage/default/0.chip_sw_kmac_idle.4075681890 Aug 03 07:15:25 PM PDT 24 Aug 03 07:19:56 PM PDT 24 3485490236 ps
T25 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.3679148534 Aug 03 07:35:30 PM PDT 24 Aug 03 07:40:26 PM PDT 24 3005149880 ps
T631 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.2343893852 Aug 03 07:27:10 PM PDT 24 Aug 03 07:33:20 PM PDT 24 4101896548 ps
T38 /workspace/coverage/default/2.chip_sw_spi_device_tpm.8225676 Aug 03 07:36:18 PM PDT 24 Aug 03 07:41:13 PM PDT 24 3240447588 ps
T184 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1692439560 Aug 03 07:06:29 PM PDT 24 Aug 03 08:38:36 PM PDT 24 44001124015 ps
T103 /workspace/coverage/default/1.chip_sw_alert_test.2705064193 Aug 03 07:26:28 PM PDT 24 Aug 03 07:31:13 PM PDT 24 3499953804 ps
T415 /workspace/coverage/default/2.chip_sw_edn_boot_mode.3167832220 Aug 03 07:42:09 PM PDT 24 Aug 03 07:54:17 PM PDT 24 3295058852 ps
T632 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1566618145 Aug 03 07:21:52 PM PDT 24 Aug 03 07:35:00 PM PDT 24 8644395991 ps
T74 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2862343513 Aug 03 07:47:52 PM PDT 24 Aug 03 07:58:45 PM PDT 24 4737394424 ps
T633 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1005683769 Aug 03 07:50:24 PM PDT 24 Aug 03 07:58:10 PM PDT 24 3816645054 ps
T634 /workspace/coverage/default/49.chip_sw_all_escalation_resets.11438100 Aug 03 07:53:48 PM PDT 24 Aug 03 08:03:15 PM PDT 24 5923240938 ps
T444 /workspace/coverage/default/63.chip_sw_all_escalation_resets.615376543 Aug 03 07:53:32 PM PDT 24 Aug 03 08:01:05 PM PDT 24 4906741288 ps
T377 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.1593409149 Aug 03 07:42:52 PM PDT 24 Aug 03 07:48:16 PM PDT 24 2822376072 ps
T476 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1200527513 Aug 03 07:47:52 PM PDT 24 Aug 03 07:55:01 PM PDT 24 4296622364 ps
T635 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.1797434998 Aug 03 07:47:20 PM PDT 24 Aug 03 07:57:58 PM PDT 24 3838345118 ps
T528 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1139080022 Aug 03 07:56:20 PM PDT 24 Aug 03 08:01:56 PM PDT 24 4491941592 ps
T122 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.576653186 Aug 03 07:54:01 PM PDT 24 Aug 03 07:59:08 PM PDT 24 3724029212 ps
T246 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2233766724 Aug 03 07:38:32 PM PDT 24 Aug 03 07:49:30 PM PDT 24 4524867277 ps
T450 /workspace/coverage/default/92.chip_sw_all_escalation_resets.2559633223 Aug 03 07:55:35 PM PDT 24 Aug 03 08:05:54 PM PDT 24 5515083012 ps
T398 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.4079602664 Aug 03 07:52:20 PM PDT 24 Aug 03 07:58:58 PM PDT 24 3482723928 ps
T636 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2018434261 Aug 03 07:08:16 PM PDT 24 Aug 03 07:15:19 PM PDT 24 7488325704 ps
T637 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2255933324 Aug 03 07:13:34 PM PDT 24 Aug 03 07:55:14 PM PDT 24 11202810214 ps
T638 /workspace/coverage/default/0.chip_sw_csrng_kat_test.897565389 Aug 03 07:13:19 PM PDT 24 Aug 03 07:18:59 PM PDT 24 2761201804 ps
T639 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2764532606 Aug 03 07:08:18 PM PDT 24 Aug 03 07:15:08 PM PDT 24 3538374902 ps
T640 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3288011470 Aug 03 07:34:56 PM PDT 24 Aug 03 07:42:23 PM PDT 24 4655748239 ps
T641 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.4223004032 Aug 03 07:38:47 PM PDT 24 Aug 03 07:46:36 PM PDT 24 6805924320 ps
T320 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1524108485 Aug 03 07:07:55 PM PDT 24 Aug 03 10:12:05 PM PDT 24 58801943171 ps
T269 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1359675838 Aug 03 07:50:13 PM PDT 24 Aug 03 07:57:38 PM PDT 24 4223417462 ps
T391 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.3395936441 Aug 03 07:38:04 PM PDT 24 Aug 03 08:02:42 PM PDT 24 10445471681 ps
T642 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.68230345 Aug 03 07:12:53 PM PDT 24 Aug 03 07:36:04 PM PDT 24 7083667172 ps
T643 /workspace/coverage/default/0.chip_sw_usbdev_stream.112379883 Aug 03 07:08:46 PM PDT 24 Aug 03 08:23:30 PM PDT 24 18235422580 ps
T644 /workspace/coverage/default/1.chip_sw_example_concurrency.1557939282 Aug 03 07:20:27 PM PDT 24 Aug 03 07:24:14 PM PDT 24 2738826350 ps
T506 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3859101162 Aug 03 07:54:44 PM PDT 24 Aug 03 08:00:41 PM PDT 24 4409059856 ps
T278 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1638487244 Aug 03 07:24:22 PM PDT 24 Aug 03 07:31:56 PM PDT 24 5886805320 ps
T645 /workspace/coverage/default/1.chip_sw_hmac_oneshot.446842698 Aug 03 07:27:58 PM PDT 24 Aug 03 07:33:53 PM PDT 24 3165831210 ps
T646 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1199171539 Aug 03 07:47:43 PM PDT 24 Aug 03 07:53:45 PM PDT 24 3642417406 ps
T647 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.2441671690 Aug 03 07:21:05 PM PDT 24 Aug 03 07:24:07 PM PDT 24 3062130428 ps
T112 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.477201878 Aug 03 07:15:38 PM PDT 24 Aug 03 07:43:43 PM PDT 24 24983079692 ps
T195 /workspace/coverage/default/2.chip_sw_kmac_app_rom.3856670678 Aug 03 07:41:42 PM PDT 24 Aug 03 07:44:57 PM PDT 24 2833765240 ps
T433 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2370428729 Aug 03 07:30:19 PM PDT 24 Aug 03 07:37:18 PM PDT 24 5297848976 ps
T648 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.2768290332 Aug 03 07:44:43 PM PDT 24 Aug 03 07:53:30 PM PDT 24 4029264782 ps
T649 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.1527112824 Aug 03 07:24:43 PM PDT 24 Aug 03 08:31:44 PM PDT 24 14994236880 ps
T385 /workspace/coverage/default/2.chip_sw_hmac_enc.3818184560 Aug 03 07:42:09 PM PDT 24 Aug 03 07:46:08 PM PDT 24 2957115412 ps
T650 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.896851967 Aug 03 07:07:10 PM PDT 24 Aug 03 08:35:07 PM PDT 24 28349775054 ps
T651 /workspace/coverage/default/1.chip_tap_straps_rma.2982690866 Aug 03 07:29:56 PM PDT 24 Aug 03 07:35:54 PM PDT 24 3825649538 ps
T118 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3051145760 Aug 03 07:06:17 PM PDT 24 Aug 03 07:12:52 PM PDT 24 3905017450 ps
T652 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.2616034971 Aug 03 07:30:29 PM PDT 24 Aug 03 07:36:24 PM PDT 24 3363811000 ps
T292 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.401687023 Aug 03 07:12:27 PM PDT 24 Aug 03 07:20:36 PM PDT 24 5080378959 ps
T171 /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.2029744978 Aug 03 07:33:49 PM PDT 24 Aug 03 07:44:47 PM PDT 24 5238847630 ps
T293 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.1327273191 Aug 03 07:49:44 PM PDT 24 Aug 03 08:01:38 PM PDT 24 6528373732 ps
T653 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1215954498 Aug 03 07:09:27 PM PDT 24 Aug 03 07:29:04 PM PDT 24 7102960888 ps
T216 /workspace/coverage/default/2.chip_plic_all_irqs_0.3413347643 Aug 03 07:42:46 PM PDT 24 Aug 03 08:04:38 PM PDT 24 5877720498 ps
T654 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2699777814 Aug 03 07:37:03 PM PDT 24 Aug 03 07:55:12 PM PDT 24 6048124112 ps
T655 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3341715494 Aug 03 07:37:27 PM PDT 24 Aug 03 08:42:34 PM PDT 24 14876477150 ps
T656 /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3070071371 Aug 03 07:35:56 PM PDT 24 Aug 03 11:27:39 PM PDT 24 78876706605 ps
T379 /workspace/coverage/default/0.chip_sival_flash_info_access.1630995266 Aug 03 07:07:06 PM PDT 24 Aug 03 07:11:44 PM PDT 24 3333038250 ps
T657 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.4166496080 Aug 03 07:34:48 PM PDT 24 Aug 03 07:55:11 PM PDT 24 8930545792 ps
T516 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.44803001 Aug 03 07:53:55 PM PDT 24 Aug 03 08:00:25 PM PDT 24 3536942364 ps
T658 /workspace/coverage/default/4.chip_tap_straps_prod.3414709175 Aug 03 07:48:11 PM PDT 24 Aug 03 07:51:19 PM PDT 24 2940826237 ps
T659 /workspace/coverage/default/2.chip_sw_uart_smoketest.4046626659 Aug 03 07:45:42 PM PDT 24 Aug 03 07:49:39 PM PDT 24 2762173592 ps
T660 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.4076846908 Aug 03 07:29:22 PM PDT 24 Aug 03 07:41:09 PM PDT 24 12388816477 ps
T517 /workspace/coverage/default/77.chip_sw_all_escalation_resets.4067892060 Aug 03 07:54:46 PM PDT 24 Aug 03 08:08:26 PM PDT 24 6393867240 ps
T661 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3932819892 Aug 03 07:41:43 PM PDT 24 Aug 03 08:06:18 PM PDT 24 7929078773 ps
T662 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2990052862 Aug 03 07:06:13 PM PDT 24 Aug 03 07:15:09 PM PDT 24 5799260280 ps
T663 /workspace/coverage/default/1.chip_sw_otbn_smoketest.627389894 Aug 03 07:40:43 PM PDT 24 Aug 03 08:09:12 PM PDT 24 9911543204 ps
T192 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.155173165 Aug 03 07:17:25 PM PDT 24 Aug 03 07:27:41 PM PDT 24 4588888632 ps
T147 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1370813668 Aug 03 07:29:56 PM PDT 24 Aug 03 07:35:39 PM PDT 24 5007150916 ps
T135 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4238006441 Aug 03 07:43:22 PM PDT 24 Aug 03 08:07:52 PM PDT 24 20614803960 ps
T664 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.4191097352 Aug 03 07:09:04 PM PDT 24 Aug 03 07:21:23 PM PDT 24 5792007015 ps
T289 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.4166253288 Aug 03 07:22:57 PM PDT 24 Aug 03 08:20:03 PM PDT 24 14416569091 ps
T665 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.996089528 Aug 03 07:22:55 PM PDT 24 Aug 03 10:41:23 PM PDT 24 58052083273 ps
T277 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.965311310 Aug 03 07:40:52 PM PDT 24 Aug 03 08:11:44 PM PDT 24 12842357560 ps
T666 /workspace/coverage/default/1.rom_e2e_self_hash.373270939 Aug 03 07:35:50 PM PDT 24 Aug 03 09:12:51 PM PDT 24 26810080400 ps
T495 /workspace/coverage/default/42.chip_sw_all_escalation_resets.3469440076 Aug 03 07:52:52 PM PDT 24 Aug 03 08:04:05 PM PDT 24 4456032766 ps
T667 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.1832819869 Aug 03 07:16:45 PM PDT 24 Aug 03 07:22:28 PM PDT 24 3179163960 ps
T389 /workspace/coverage/default/0.chip_sw_power_idle_load.1754188437 Aug 03 07:17:30 PM PDT 24 Aug 03 07:27:42 PM PDT 24 4739328510 ps
T668 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1106473654 Aug 03 07:41:37 PM PDT 24 Aug 03 07:48:41 PM PDT 24 4259857300 ps
T669 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1355614519 Aug 03 07:19:54 PM PDT 24 Aug 03 07:24:42 PM PDT 24 3161408500 ps
T670 /workspace/coverage/default/2.chip_sw_hmac_oneshot.3783372683 Aug 03 07:42:06 PM PDT 24 Aug 03 07:47:05 PM PDT 24 2914046480 ps
T294 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1394835649 Aug 03 07:10:30 PM PDT 24 Aug 03 07:17:20 PM PDT 24 3327496680 ps
T671 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1977071634 Aug 03 07:41:32 PM PDT 24 Aug 03 07:50:18 PM PDT 24 5099217408 ps
T672 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.1422309678 Aug 03 07:40:01 PM PDT 24 Aug 03 07:51:02 PM PDT 24 8052029420 ps
T673 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1621226355 Aug 03 07:40:02 PM PDT 24 Aug 03 07:43:16 PM PDT 24 2717640736 ps
T35 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1311255955 Aug 03 07:08:35 PM PDT 24 Aug 03 07:16:22 PM PDT 24 5759669304 ps
T674 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2004481382 Aug 03 07:34:21 PM PDT 24 Aug 03 07:41:44 PM PDT 24 5742397442 ps
T675 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.3276172824 Aug 03 07:25:45 PM PDT 24 Aug 03 07:35:25 PM PDT 24 4674604316 ps
T9 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3154831191 Aug 03 07:21:18 PM PDT 24 Aug 03 07:25:23 PM PDT 24 2996826948 ps
T676 /workspace/coverage/default/4.chip_tap_straps_testunlock0.686274037 Aug 03 07:47:21 PM PDT 24 Aug 03 07:50:49 PM PDT 24 3064578113 ps
T507 /workspace/coverage/default/33.chip_sw_all_escalation_resets.2015577574 Aug 03 07:49:50 PM PDT 24 Aug 03 07:58:30 PM PDT 24 4382076780 ps
T677 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1753064020 Aug 03 07:32:44 PM PDT 24 Aug 03 07:54:54 PM PDT 24 5509521780 ps
T678 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.771591027 Aug 03 07:29:55 PM PDT 24 Aug 03 07:37:42 PM PDT 24 5131653536 ps
T679 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.2595208602 Aug 03 07:38:28 PM PDT 24 Aug 03 07:50:16 PM PDT 24 6123715572 ps
T680 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.1433428847 Aug 03 07:44:27 PM PDT 24 Aug 03 07:47:49 PM PDT 24 2753449411 ps
T369 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.773307159 Aug 03 07:35:28 PM PDT 24 Aug 03 07:44:11 PM PDT 24 4121859360 ps
T681 /workspace/coverage/default/1.chip_sw_uart_smoketest.3692264984 Aug 03 07:34:59 PM PDT 24 Aug 03 07:40:02 PM PDT 24 2640718436 ps
T682 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.5731341 Aug 03 07:25:48 PM PDT 24 Aug 03 07:31:57 PM PDT 24 2996243098 ps
T530 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1138163152 Aug 03 07:52:17 PM PDT 24 Aug 03 07:58:05 PM PDT 24 3764808164 ps
T683 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.140851187 Aug 03 07:35:10 PM PDT 24 Aug 03 07:50:59 PM PDT 24 4752826692 ps
T342 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1960130121 Aug 03 07:17:11 PM PDT 24 Aug 03 07:44:50 PM PDT 24 26228396423 ps
T684 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.1499100389 Aug 03 07:23:00 PM PDT 24 Aug 03 08:25:57 PM PDT 24 15271722022 ps
T22 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.4066742934 Aug 03 07:10:15 PM PDT 24 Aug 03 08:16:23 PM PDT 24 20592770192 ps
T229 /workspace/coverage/default/2.chip_sw_power_virus.694454360 Aug 03 07:49:39 PM PDT 24 Aug 03 08:12:41 PM PDT 24 5679597000 ps
T685 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.4029523026 Aug 03 07:45:35 PM PDT 24 Aug 03 07:51:35 PM PDT 24 3462475082 ps
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