| T832 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3387947951 |
|
|
Aug 03 07:42:37 PM PDT 24 |
Aug 03 07:51:47 PM PDT 24 |
4360968992 ps |
| T833 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.463748210 |
|
|
Aug 03 07:36:40 PM PDT 24 |
Aug 03 07:55:43 PM PDT 24 |
10927492685 ps |
| T834 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.1411924995 |
|
|
Aug 03 07:45:28 PM PDT 24 |
Aug 03 07:49:37 PM PDT 24 |
2704271880 ps |
| T835 |
/workspace/coverage/default/56.chip_sw_all_escalation_resets.574435646 |
|
|
Aug 03 07:53:41 PM PDT 24 |
Aug 03 08:02:31 PM PDT 24 |
4740208848 ps |
| T529 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3735057617 |
|
|
Aug 03 07:50:04 PM PDT 24 |
Aug 03 07:56:47 PM PDT 24 |
3956880462 ps |
| T836 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.4269679384 |
|
|
Aug 03 07:50:47 PM PDT 24 |
Aug 03 08:06:15 PM PDT 24 |
11626360522 ps |
| T837 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1544543652 |
|
|
Aug 03 07:29:16 PM PDT 24 |
Aug 03 07:37:11 PM PDT 24 |
5274241300 ps |
| T378 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.4222403135 |
|
|
Aug 03 07:12:46 PM PDT 24 |
Aug 03 07:17:12 PM PDT 24 |
3141266456 ps |
| T838 |
/workspace/coverage/default/1.chip_sw_kmac_app_rom.3640728886 |
|
|
Aug 03 07:29:28 PM PDT 24 |
Aug 03 07:33:54 PM PDT 24 |
2746165084 ps |
| T480 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2547406659 |
|
|
Aug 03 07:54:54 PM PDT 24 |
Aug 03 08:00:31 PM PDT 24 |
3973120000 ps |
| T331 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.3548525316 |
|
|
Aug 03 07:27:39 PM PDT 24 |
Aug 03 08:12:56 PM PDT 24 |
14251910440 ps |
| T839 |
/workspace/coverage/default/0.rom_e2e_smoke.480501568 |
|
|
Aug 03 07:22:08 PM PDT 24 |
Aug 03 08:24:25 PM PDT 24 |
14732157000 ps |
| T840 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3819032310 |
|
|
Aug 03 07:09:53 PM PDT 24 |
Aug 03 07:17:29 PM PDT 24 |
18824935980 ps |
| T841 |
/workspace/coverage/default/0.chip_sw_example_concurrency.3446207715 |
|
|
Aug 03 07:06:16 PM PDT 24 |
Aug 03 07:11:24 PM PDT 24 |
3496152194 ps |
| T842 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.3223864669 |
|
|
Aug 03 07:26:54 PM PDT 24 |
Aug 03 07:30:23 PM PDT 24 |
3007997288 ps |
| T843 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3164877147 |
|
|
Aug 03 07:43:02 PM PDT 24 |
Aug 03 07:56:07 PM PDT 24 |
4810484338 ps |
| T367 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2609387968 |
|
|
Aug 03 07:46:52 PM PDT 24 |
Aug 03 07:58:11 PM PDT 24 |
5381598682 ps |
| T844 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1718157778 |
|
|
Aug 03 07:39:29 PM PDT 24 |
Aug 03 08:16:35 PM PDT 24 |
28701588259 ps |
| T845 |
/workspace/coverage/default/1.chip_tap_straps_prod.2109440599 |
|
|
Aug 03 07:30:17 PM PDT 24 |
Aug 03 07:46:09 PM PDT 24 |
11497786782 ps |
| T846 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3203937259 |
|
|
Aug 03 07:46:12 PM PDT 24 |
Aug 03 07:54:21 PM PDT 24 |
6694126232 ps |
| T847 |
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3030557343 |
|
|
Aug 03 07:48:46 PM PDT 24 |
Aug 03 09:01:12 PM PDT 24 |
20664929904 ps |
| T399 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.2603719958 |
|
|
Aug 03 07:54:06 PM PDT 24 |
Aug 03 08:05:58 PM PDT 24 |
5398864928 ps |
| T848 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1144214471 |
|
|
Aug 03 07:14:17 PM PDT 24 |
Aug 03 07:54:56 PM PDT 24 |
28720635720 ps |
| T849 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.1455514295 |
|
|
Aug 03 07:35:11 PM PDT 24 |
Aug 03 07:46:35 PM PDT 24 |
4955652976 ps |
| T850 |
/workspace/coverage/default/3.chip_tap_straps_prod.3816908282 |
|
|
Aug 03 07:46:19 PM PDT 24 |
Aug 03 07:48:51 PM PDT 24 |
2843243807 ps |
| T851 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2660928046 |
|
|
Aug 03 07:14:48 PM PDT 24 |
Aug 03 07:24:50 PM PDT 24 |
3784404408 ps |
| T852 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.1301831834 |
|
|
Aug 03 07:22:23 PM PDT 24 |
Aug 03 07:26:32 PM PDT 24 |
2720478520 ps |
| T853 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1423568207 |
|
|
Aug 03 07:14:10 PM PDT 24 |
Aug 03 07:26:10 PM PDT 24 |
10354717592 ps |
| T854 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1549467303 |
|
|
Aug 03 07:43:25 PM PDT 24 |
Aug 03 07:55:48 PM PDT 24 |
5035909684 ps |
| T855 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1723476080 |
|
|
Aug 03 07:21:33 PM PDT 24 |
Aug 03 09:07:16 PM PDT 24 |
24055178860 ps |
| T856 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2806841679 |
|
|
Aug 03 07:17:45 PM PDT 24 |
Aug 03 07:36:54 PM PDT 24 |
7199947976 ps |
| T857 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1738255043 |
|
|
Aug 03 07:26:41 PM PDT 24 |
Aug 03 08:28:31 PM PDT 24 |
13703149540 ps |
| T364 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2788776613 |
|
|
Aug 03 07:25:28 PM PDT 24 |
Aug 03 07:55:29 PM PDT 24 |
13421973920 ps |
| T858 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.1627805588 |
|
|
Aug 03 07:34:48 PM PDT 24 |
Aug 03 07:42:22 PM PDT 24 |
6727252372 ps |
| T859 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2304899458 |
|
|
Aug 03 07:34:04 PM PDT 24 |
Aug 03 07:38:00 PM PDT 24 |
3450765700 ps |
| T860 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.3675886175 |
|
|
Aug 03 07:35:38 PM PDT 24 |
Aug 03 07:49:18 PM PDT 24 |
5571947056 ps |
| T304 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3099748646 |
|
|
Aug 03 07:44:27 PM PDT 24 |
Aug 03 07:48:46 PM PDT 24 |
2291370350 ps |
| T861 |
/workspace/coverage/default/2.chip_sw_aes_enc.2416426044 |
|
|
Aug 03 07:39:36 PM PDT 24 |
Aug 03 07:43:05 PM PDT 24 |
2842367630 ps |
| T862 |
/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2817803717 |
|
|
Aug 03 07:11:39 PM PDT 24 |
Aug 03 10:52:10 PM PDT 24 |
254934176868 ps |
| T863 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.1426504704 |
|
|
Aug 03 07:14:27 PM PDT 24 |
Aug 03 07:21:54 PM PDT 24 |
4025571670 ps |
| T864 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.4045322699 |
|
|
Aug 03 07:51:46 PM PDT 24 |
Aug 03 08:01:24 PM PDT 24 |
4952064620 ps |
| T865 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter.1568271282 |
|
|
Aug 03 07:15:30 PM PDT 24 |
Aug 03 07:19:56 PM PDT 24 |
3218168227 ps |
| T866 |
/workspace/coverage/default/1.chip_sw_example_flash.3720774918 |
|
|
Aug 03 07:21:38 PM PDT 24 |
Aug 03 07:24:41 PM PDT 24 |
3048388070 ps |
| T81 |
/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.1890089241 |
|
|
Aug 03 07:43:37 PM PDT 24 |
Aug 03 08:57:27 PM PDT 24 |
23772579514 ps |
| T867 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3417819520 |
|
|
Aug 03 07:43:17 PM PDT 24 |
Aug 03 07:53:07 PM PDT 24 |
4498674760 ps |
| T868 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2547700581 |
|
|
Aug 03 07:11:07 PM PDT 24 |
Aug 03 08:56:27 PM PDT 24 |
26911464632 ps |
| T869 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1890595262 |
|
|
Aug 03 07:10:12 PM PDT 24 |
Aug 03 07:14:08 PM PDT 24 |
3199409868 ps |
| T33 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.3577675939 |
|
|
Aug 03 07:07:37 PM PDT 24 |
Aug 03 07:12:46 PM PDT 24 |
3449323260 ps |
| T870 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2225225672 |
|
|
Aug 03 07:29:17 PM PDT 24 |
Aug 03 08:52:40 PM PDT 24 |
16503686716 ps |
| T871 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3187493801 |
|
|
Aug 03 07:22:24 PM PDT 24 |
Aug 03 08:33:07 PM PDT 24 |
15264431008 ps |
| T872 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4137435860 |
|
|
Aug 03 07:45:41 PM PDT 24 |
Aug 03 07:55:42 PM PDT 24 |
5700054346 ps |
| T873 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.239251348 |
|
|
Aug 03 07:55:05 PM PDT 24 |
Aug 03 08:03:07 PM PDT 24 |
4513302858 ps |
| T874 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2698939785 |
|
|
Aug 03 07:31:16 PM PDT 24 |
Aug 03 07:41:19 PM PDT 24 |
5013703496 ps |
| T36 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3982288578 |
|
|
Aug 03 07:27:40 PM PDT 24 |
Aug 03 07:34:05 PM PDT 24 |
5191615736 ps |
| T354 |
/workspace/coverage/default/1.rom_raw_unlock.3276015018 |
|
|
Aug 03 07:33:08 PM PDT 24 |
Aug 03 07:36:41 PM PDT 24 |
4330485813 ps |
| T875 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1017967980 |
|
|
Aug 03 07:49:22 PM PDT 24 |
Aug 03 07:56:39 PM PDT 24 |
3286612560 ps |
| T876 |
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1255716378 |
|
|
Aug 03 07:48:36 PM PDT 24 |
Aug 03 09:29:42 PM PDT 24 |
28307143638 ps |
| T877 |
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3344038862 |
|
|
Aug 03 07:48:15 PM PDT 24 |
Aug 03 08:03:59 PM PDT 24 |
10736791754 ps |
| T878 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.125726464 |
|
|
Aug 03 07:47:30 PM PDT 24 |
Aug 03 07:55:20 PM PDT 24 |
5174207105 ps |
| T879 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1739500060 |
|
|
Aug 03 07:46:25 PM PDT 24 |
Aug 03 07:51:29 PM PDT 24 |
3165104618 ps |
| T279 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3909642052 |
|
|
Aug 03 07:08:33 PM PDT 24 |
Aug 03 07:19:13 PM PDT 24 |
6212018046 ps |
| T880 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3580765815 |
|
|
Aug 03 07:40:31 PM PDT 24 |
Aug 03 07:57:40 PM PDT 24 |
5579085590 ps |
| T344 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.338582782 |
|
|
Aug 03 07:54:46 PM PDT 24 |
Aug 03 08:00:45 PM PDT 24 |
3606847990 ps |
| T881 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2548653690 |
|
|
Aug 03 07:22:07 PM PDT 24 |
Aug 03 08:07:35 PM PDT 24 |
12969844688 ps |
| T536 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1271059586 |
|
|
Aug 03 07:12:29 PM PDT 24 |
Aug 03 07:18:56 PM PDT 24 |
3971742766 ps |
| T218 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.151457816 |
|
|
Aug 03 07:13:08 PM PDT 24 |
Aug 03 07:28:08 PM PDT 24 |
5871865422 ps |
| T882 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1464066063 |
|
|
Aug 03 07:11:14 PM PDT 24 |
Aug 03 07:16:11 PM PDT 24 |
3822332372 ps |
| T883 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx.447961304 |
|
|
Aug 03 07:45:36 PM PDT 24 |
Aug 03 07:55:49 PM PDT 24 |
4509977494 ps |
| T125 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1313466298 |
|
|
Aug 03 07:55:36 PM PDT 24 |
Aug 03 08:04:35 PM PDT 24 |
3628349432 ps |
| T884 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1329372285 |
|
|
Aug 03 07:22:30 PM PDT 24 |
Aug 03 08:29:55 PM PDT 24 |
15725006440 ps |
| T270 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1322527184 |
|
|
Aug 03 07:54:46 PM PDT 24 |
Aug 03 08:01:06 PM PDT 24 |
4089533706 ps |
| T885 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.4254006259 |
|
|
Aug 03 07:23:04 PM PDT 24 |
Aug 03 07:46:17 PM PDT 24 |
7627147956 ps |
| T886 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.32260791 |
|
|
Aug 03 07:47:38 PM PDT 24 |
Aug 03 08:36:01 PM PDT 24 |
13881176038 ps |
| T493 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.42436377 |
|
|
Aug 03 07:54:57 PM PDT 24 |
Aug 03 08:01:40 PM PDT 24 |
3592053760 ps |
| T887 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.434856929 |
|
|
Aug 03 07:37:20 PM PDT 24 |
Aug 03 07:44:16 PM PDT 24 |
6211379920 ps |
| T888 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.1381502470 |
|
|
Aug 03 07:21:17 PM PDT 24 |
Aug 03 08:00:06 PM PDT 24 |
9652435906 ps |
| T889 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3747898562 |
|
|
Aug 03 07:21:01 PM PDT 24 |
Aug 03 07:25:44 PM PDT 24 |
2752508700 ps |
| T890 |
/workspace/coverage/default/0.chip_sw_aes_enc.3386923050 |
|
|
Aug 03 07:09:59 PM PDT 24 |
Aug 03 07:14:13 PM PDT 24 |
2741859820 ps |
| T891 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3591978162 |
|
|
Aug 03 07:12:30 PM PDT 24 |
Aug 03 07:19:49 PM PDT 24 |
7033328436 ps |
| T356 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_dev.3769443312 |
|
|
Aug 03 07:21:35 PM PDT 24 |
Aug 03 08:03:05 PM PDT 24 |
10966042516 ps |
| T892 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1026142918 |
|
|
Aug 03 07:31:52 PM PDT 24 |
Aug 03 08:08:11 PM PDT 24 |
11724420732 ps |
| T395 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1064823797 |
|
|
Aug 03 07:15:16 PM PDT 24 |
Aug 03 07:24:39 PM PDT 24 |
6399055630 ps |
| T893 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.2871108771 |
|
|
Aug 03 07:21:02 PM PDT 24 |
Aug 03 08:25:03 PM PDT 24 |
26445333787 ps |
| T400 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1007852849 |
|
|
Aug 03 07:52:29 PM PDT 24 |
Aug 03 07:58:54 PM PDT 24 |
3649647338 ps |
| T894 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.2576094407 |
|
|
Aug 03 07:12:19 PM PDT 24 |
Aug 03 07:21:02 PM PDT 24 |
8431007995 ps |
| T895 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2263029348 |
|
|
Aug 03 07:21:14 PM PDT 24 |
Aug 03 07:25:53 PM PDT 24 |
3412723328 ps |
| T896 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.4048242891 |
|
|
Aug 03 07:44:48 PM PDT 24 |
Aug 03 07:56:26 PM PDT 24 |
9129963818 ps |
| T897 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2399238826 |
|
|
Aug 03 07:25:09 PM PDT 24 |
Aug 03 08:21:31 PM PDT 24 |
17057264920 ps |
| T26 |
/workspace/coverage/default/0.chip_sw_gpio.3315156266 |
|
|
Aug 03 07:06:29 PM PDT 24 |
Aug 03 07:13:26 PM PDT 24 |
4149045899 ps |
| T898 |
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1835167479 |
|
|
Aug 03 07:48:18 PM PDT 24 |
Aug 03 08:49:34 PM PDT 24 |
16987423800 ps |
| T899 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1013698691 |
|
|
Aug 03 07:16:58 PM PDT 24 |
Aug 03 07:30:32 PM PDT 24 |
7518757473 ps |
| T522 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2759345327 |
|
|
Aug 03 07:55:06 PM PDT 24 |
Aug 03 08:03:06 PM PDT 24 |
3342149188 ps |
| T27 |
/workspace/coverage/default/2.chip_sw_gpio.4150822370 |
|
|
Aug 03 07:35:58 PM PDT 24 |
Aug 03 07:44:25 PM PDT 24 |
4542897457 ps |
| T900 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3731043349 |
|
|
Aug 03 07:23:08 PM PDT 24 |
Aug 03 07:37:10 PM PDT 24 |
11068365280 ps |
| T901 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.4030719102 |
|
|
Aug 03 07:39:17 PM PDT 24 |
Aug 03 07:46:41 PM PDT 24 |
3501845016 ps |
| T902 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2764321014 |
|
|
Aug 03 07:25:31 PM PDT 24 |
Aug 03 07:36:25 PM PDT 24 |
5836851176 ps |
| T523 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.2204357143 |
|
|
Aug 03 07:49:49 PM PDT 24 |
Aug 03 08:00:47 PM PDT 24 |
5762639940 ps |
| T903 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3408138635 |
|
|
Aug 03 07:23:09 PM PDT 24 |
Aug 03 08:31:43 PM PDT 24 |
14790751946 ps |
| T904 |
/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3718241737 |
|
|
Aug 03 07:52:26 PM PDT 24 |
Aug 03 08:03:09 PM PDT 24 |
4389860248 ps |
| T262 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.2469315142 |
|
|
Aug 03 07:32:49 PM PDT 24 |
Aug 03 07:36:40 PM PDT 24 |
2865672768 ps |
| T537 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.1774437842 |
|
|
Aug 03 07:47:57 PM PDT 24 |
Aug 03 07:56:36 PM PDT 24 |
4160788466 ps |
| T905 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.4169578230 |
|
|
Aug 03 07:24:02 PM PDT 24 |
Aug 03 07:29:55 PM PDT 24 |
4524897800 ps |
| T906 |
/workspace/coverage/default/1.chip_tap_straps_dev.43336688 |
|
|
Aug 03 07:31:51 PM PDT 24 |
Aug 03 07:35:45 PM PDT 24 |
3587282049 ps |
| T907 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.3764977639 |
|
|
Aug 03 07:46:01 PM PDT 24 |
Aug 03 07:58:28 PM PDT 24 |
3974139480 ps |
| T908 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2408423144 |
|
|
Aug 03 07:38:51 PM PDT 24 |
Aug 03 08:00:44 PM PDT 24 |
13627020289 ps |
| T447 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.249179944 |
|
|
Aug 03 07:49:31 PM PDT 24 |
Aug 03 08:03:51 PM PDT 24 |
5913687544 ps |
| T468 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3433141487 |
|
|
Aug 03 07:53:32 PM PDT 24 |
Aug 03 08:01:19 PM PDT 24 |
4406842528 ps |
| T909 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2836884791 |
|
|
Aug 03 07:38:38 PM PDT 24 |
Aug 03 08:37:46 PM PDT 24 |
20933538581 ps |
| T910 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2801219637 |
|
|
Aug 03 07:41:39 PM PDT 24 |
Aug 03 07:50:14 PM PDT 24 |
3859877542 ps |
| T911 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.787675533 |
|
|
Aug 03 07:53:18 PM PDT 24 |
Aug 03 08:02:31 PM PDT 24 |
5255476258 ps |
| T912 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.930226150 |
|
|
Aug 03 07:48:58 PM PDT 24 |
Aug 03 08:23:51 PM PDT 24 |
13261090720 ps |
| T913 |
/workspace/coverage/default/1.chip_sw_flash_crash_alert.3283574015 |
|
|
Aug 03 07:31:51 PM PDT 24 |
Aug 03 07:44:41 PM PDT 24 |
5747668044 ps |
| T914 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.259281735 |
|
|
Aug 03 07:15:42 PM PDT 24 |
Aug 03 07:24:52 PM PDT 24 |
4130575300 ps |
| T915 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.732128205 |
|
|
Aug 03 07:45:32 PM PDT 24 |
Aug 03 08:42:06 PM PDT 24 |
20860558770 ps |
| T916 |
/workspace/coverage/default/1.chip_sw_edn_kat.1669811804 |
|
|
Aug 03 07:27:57 PM PDT 24 |
Aug 03 07:37:09 PM PDT 24 |
3034689392 ps |
| T917 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.1418586470 |
|
|
Aug 03 07:13:30 PM PDT 24 |
Aug 03 07:35:31 PM PDT 24 |
12809354562 ps |
| T498 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.65181866 |
|
|
Aug 03 07:53:05 PM PDT 24 |
Aug 03 08:04:21 PM PDT 24 |
5656476704 ps |
| T918 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.863485805 |
|
|
Aug 03 07:36:34 PM PDT 24 |
Aug 03 07:38:17 PM PDT 24 |
2151505414 ps |
| T919 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.608969282 |
|
|
Aug 03 07:11:28 PM PDT 24 |
Aug 03 07:39:18 PM PDT 24 |
13283774712 ps |
| T920 |
/workspace/coverage/default/0.chip_sw_hmac_smoketest.2081303700 |
|
|
Aug 03 07:23:07 PM PDT 24 |
Aug 03 07:27:50 PM PDT 24 |
3354709510 ps |
| T921 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.2504726481 |
|
|
Aug 03 07:09:24 PM PDT 24 |
Aug 03 07:25:36 PM PDT 24 |
5832405266 ps |
| T922 |
/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.678096032 |
|
|
Aug 03 07:41:00 PM PDT 24 |
Aug 03 07:50:28 PM PDT 24 |
3368709108 ps |
| T448 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.4111756361 |
|
|
Aug 03 07:54:47 PM PDT 24 |
Aug 03 08:02:49 PM PDT 24 |
5392072162 ps |
| T923 |
/workspace/coverage/default/0.chip_sw_edn_kat.3912595018 |
|
|
Aug 03 07:10:59 PM PDT 24 |
Aug 03 07:19:48 PM PDT 24 |
3044691352 ps |
| T924 |
/workspace/coverage/default/0.chip_sw_alert_handler_entropy.2705538651 |
|
|
Aug 03 07:12:40 PM PDT 24 |
Aug 03 07:16:31 PM PDT 24 |
3233525984 ps |
| T925 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.628776745 |
|
|
Aug 03 07:29:55 PM PDT 24 |
Aug 03 07:59:45 PM PDT 24 |
21159779555 ps |
| T926 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2100645639 |
|
|
Aug 03 07:41:18 PM PDT 24 |
Aug 03 08:22:47 PM PDT 24 |
8387746040 ps |
| T927 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3401854806 |
|
|
Aug 03 07:51:01 PM PDT 24 |
Aug 03 08:00:15 PM PDT 24 |
4117755160 ps |
| T928 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.86685566 |
|
|
Aug 03 07:57:19 PM PDT 24 |
Aug 03 08:03:49 PM PDT 24 |
4429917576 ps |
| T929 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.382629819 |
|
|
Aug 03 07:30:21 PM PDT 24 |
Aug 03 07:43:12 PM PDT 24 |
4473493168 ps |
| T930 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.379182956 |
|
|
Aug 03 07:36:44 PM PDT 24 |
Aug 03 07:43:53 PM PDT 24 |
3561069652 ps |
| T482 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.3650240717 |
|
|
Aug 03 07:49:30 PM PDT 24 |
Aug 03 08:01:09 PM PDT 24 |
6417145776 ps |
| T474 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.879958928 |
|
|
Aug 03 07:56:00 PM PDT 24 |
Aug 03 08:05:17 PM PDT 24 |
4869257584 ps |
| T931 |
/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.1823996704 |
|
|
Aug 03 07:36:13 PM PDT 24 |
Aug 03 07:41:10 PM PDT 24 |
3176069140 ps |
| T932 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3520001770 |
|
|
Aug 03 07:39:52 PM PDT 24 |
Aug 03 07:43:53 PM PDT 24 |
2306809405 ps |
| T933 |
/workspace/coverage/default/1.chip_sw_alert_handler_escalation.1203684158 |
|
|
Aug 03 07:25:24 PM PDT 24 |
Aug 03 07:34:44 PM PDT 24 |
5655459272 ps |
| T469 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2380909772 |
|
|
Aug 03 07:55:18 PM PDT 24 |
Aug 03 08:04:37 PM PDT 24 |
4689127078 ps |
| T934 |
/workspace/coverage/default/2.chip_sw_kmac_smoketest.418193092 |
|
|
Aug 03 07:45:39 PM PDT 24 |
Aug 03 07:51:32 PM PDT 24 |
3297641248 ps |
| T935 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.364043948 |
|
|
Aug 03 07:07:38 PM PDT 24 |
Aug 03 10:12:54 PM PDT 24 |
64716278303 ps |
| T936 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3299201858 |
|
|
Aug 03 07:06:40 PM PDT 24 |
Aug 03 07:35:34 PM PDT 24 |
8959054408 ps |
| T937 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2227474319 |
|
|
Aug 03 07:53:40 PM PDT 24 |
Aug 03 08:02:33 PM PDT 24 |
3718671720 ps |
| T938 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.1071416414 |
|
|
Aug 03 07:35:07 PM PDT 24 |
Aug 03 10:51:23 PM PDT 24 |
65217170462 ps |
| T939 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.2808705998 |
|
|
Aug 03 07:47:58 PM PDT 24 |
Aug 03 08:55:51 PM PDT 24 |
15400881530 ps |
| T940 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1021844889 |
|
|
Aug 03 07:14:45 PM PDT 24 |
Aug 03 07:24:04 PM PDT 24 |
5420404882 ps |
| T941 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.922104487 |
|
|
Aug 03 07:06:21 PM PDT 24 |
Aug 03 07:11:00 PM PDT 24 |
3495249276 ps |
| T942 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.4126407202 |
|
|
Aug 03 07:20:41 PM PDT 24 |
Aug 03 07:30:47 PM PDT 24 |
4990346062 ps |
| T943 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2764274076 |
|
|
Aug 03 07:41:12 PM PDT 24 |
Aug 03 07:59:07 PM PDT 24 |
7315403402 ps |
| T944 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.408383011 |
|
|
Aug 03 07:39:38 PM PDT 24 |
Aug 03 07:48:15 PM PDT 24 |
5057952760 ps |
| T945 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3233889214 |
|
|
Aug 03 07:13:30 PM PDT 24 |
Aug 03 07:24:47 PM PDT 24 |
7931360272 ps |
| T533 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1687995711 |
|
|
Aug 03 07:51:16 PM PDT 24 |
Aug 03 07:55:54 PM PDT 24 |
3504874600 ps |
| T946 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx.3493306050 |
|
|
Aug 03 07:21:32 PM PDT 24 |
Aug 03 07:31:32 PM PDT 24 |
4124910324 ps |
| T445 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.3712587048 |
|
|
Aug 03 07:51:23 PM PDT 24 |
Aug 03 08:01:36 PM PDT 24 |
5499900132 ps |
| T107 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.2086286314 |
|
|
Aug 03 07:21:36 PM PDT 24 |
Aug 03 07:25:30 PM PDT 24 |
3278504520 ps |
| T511 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.300835565 |
|
|
Aug 03 07:54:05 PM PDT 24 |
Aug 03 08:02:05 PM PDT 24 |
5280060068 ps |
| T947 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.409097707 |
|
|
Aug 03 07:38:09 PM PDT 24 |
Aug 03 07:40:23 PM PDT 24 |
3074396440 ps |
| T514 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1624791926 |
|
|
Aug 03 07:55:05 PM PDT 24 |
Aug 03 08:00:53 PM PDT 24 |
3661615288 ps |
| T948 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.642325918 |
|
|
Aug 03 07:08:56 PM PDT 24 |
Aug 03 11:25:44 PM PDT 24 |
77303285382 ps |
| T949 |
/workspace/coverage/default/2.chip_sw_example_rom.39085298 |
|
|
Aug 03 07:33:18 PM PDT 24 |
Aug 03 07:35:07 PM PDT 24 |
2478406040 ps |
| T950 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.605036015 |
|
|
Aug 03 07:10:32 PM PDT 24 |
Aug 03 07:31:57 PM PDT 24 |
7413630872 ps |
| T951 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.3766628638 |
|
|
Aug 03 07:11:11 PM PDT 24 |
Aug 03 07:32:57 PM PDT 24 |
5087327420 ps |
| T952 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3068537375 |
|
|
Aug 03 07:29:51 PM PDT 24 |
Aug 03 07:36:49 PM PDT 24 |
4878052860 ps |
| T953 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.3171341145 |
|
|
Aug 03 07:33:34 PM PDT 24 |
Aug 03 07:36:42 PM PDT 24 |
2610544972 ps |
| T954 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2903697174 |
|
|
Aug 03 07:23:19 PM PDT 24 |
Aug 03 08:34:21 PM PDT 24 |
16194995332 ps |
| T955 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.1165378840 |
|
|
Aug 03 07:49:31 PM PDT 24 |
Aug 03 08:00:59 PM PDT 24 |
5429705420 ps |
| T418 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1647938832 |
|
|
Aug 03 07:30:12 PM PDT 24 |
Aug 03 07:37:26 PM PDT 24 |
7235290128 ps |
| T956 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.3196003378 |
|
|
Aug 03 07:23:29 PM PDT 24 |
Aug 03 08:24:04 PM PDT 24 |
14888810147 ps |
| T957 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.246616729 |
|
|
Aug 03 07:43:02 PM PDT 24 |
Aug 03 07:53:54 PM PDT 24 |
3752553230 ps |
| T520 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.11711211 |
|
|
Aug 03 07:52:34 PM PDT 24 |
Aug 03 08:00:50 PM PDT 24 |
3924050540 ps |
| T958 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.240383860 |
|
|
Aug 03 07:23:38 PM PDT 24 |
Aug 03 08:17:04 PM PDT 24 |
11605693400 ps |
| T959 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.440559232 |
|
|
Aug 03 07:15:58 PM PDT 24 |
Aug 03 07:22:02 PM PDT 24 |
3813867736 ps |
| T960 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1558876221 |
|
|
Aug 03 07:37:08 PM PDT 24 |
Aug 03 07:49:37 PM PDT 24 |
4543691160 ps |
| T961 |
/workspace/coverage/default/1.chip_sw_hmac_enc.2041199372 |
|
|
Aug 03 07:28:22 PM PDT 24 |
Aug 03 07:33:06 PM PDT 24 |
2910068248 ps |
| T962 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.4205790973 |
|
|
Aug 03 07:38:08 PM PDT 24 |
Aug 03 08:17:03 PM PDT 24 |
28843777236 ps |
| T317 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.3348158302 |
|
|
Aug 03 07:35:08 PM PDT 24 |
Aug 03 07:38:59 PM PDT 24 |
2489086824 ps |
| T963 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.105055437 |
|
|
Aug 03 07:16:51 PM PDT 24 |
Aug 03 07:27:47 PM PDT 24 |
4647432787 ps |
| T964 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2385220774 |
|
|
Aug 03 07:21:54 PM PDT 24 |
Aug 03 10:58:18 PM PDT 24 |
78935102976 ps |
| T965 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3438274460 |
|
|
Aug 03 07:55:12 PM PDT 24 |
Aug 03 08:02:00 PM PDT 24 |
4017224120 ps |
| T452 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.2970494620 |
|
|
Aug 03 07:46:00 PM PDT 24 |
Aug 03 07:56:02 PM PDT 24 |
4372927614 ps |
| T966 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2011001454 |
|
|
Aug 03 07:22:13 PM PDT 24 |
Aug 03 07:32:30 PM PDT 24 |
3985712144 ps |
| T505 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.2662555346 |
|
|
Aug 03 07:50:20 PM PDT 24 |
Aug 03 08:03:02 PM PDT 24 |
6190277384 ps |
| T967 |
/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.198297255 |
|
|
Aug 03 07:27:58 PM PDT 24 |
Aug 03 07:40:34 PM PDT 24 |
5632412604 ps |
| T968 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1354719803 |
|
|
Aug 03 07:50:25 PM PDT 24 |
Aug 03 08:41:34 PM PDT 24 |
14766563632 ps |
| T969 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.432975810 |
|
|
Aug 03 07:45:34 PM PDT 24 |
Aug 03 07:49:44 PM PDT 24 |
2699938760 ps |
| T970 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.823457021 |
|
|
Aug 03 07:24:56 PM PDT 24 |
Aug 03 07:36:34 PM PDT 24 |
8787647520 ps |
| T77 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4031035781 |
|
|
Aug 03 07:29:49 PM PDT 24 |
Aug 03 07:38:16 PM PDT 24 |
5115931622 ps |
| T971 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2051981924 |
|
|
Aug 03 07:06:51 PM PDT 24 |
Aug 03 07:17:15 PM PDT 24 |
3965301646 ps |
| T972 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.2244955873 |
|
|
Aug 03 07:37:06 PM PDT 24 |
Aug 03 07:55:14 PM PDT 24 |
6080883000 ps |
| T260 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3133669706 |
|
|
Aug 03 07:24:26 PM PDT 24 |
Aug 03 07:28:02 PM PDT 24 |
2545146062 ps |
| T973 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.920511444 |
|
|
Aug 03 07:43:14 PM PDT 24 |
Aug 03 07:54:53 PM PDT 24 |
4900132760 ps |
| T974 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.796482874 |
|
|
Aug 03 07:46:37 PM PDT 24 |
Aug 03 07:52:59 PM PDT 24 |
3829581722 ps |
| T975 |
/workspace/coverage/default/2.chip_tap_straps_dev.2324864217 |
|
|
Aug 03 07:42:48 PM PDT 24 |
Aug 03 07:48:21 PM PDT 24 |
4155568901 ps |
| T165 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1260437162 |
|
|
Aug 03 07:36:30 PM PDT 24 |
Aug 03 07:38:30 PM PDT 24 |
2620988085 ps |
| T976 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1629541539 |
|
|
Aug 03 07:35:25 PM PDT 24 |
Aug 03 08:26:34 PM PDT 24 |
11252153265 ps |
| T419 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.978221894 |
|
|
Aug 03 07:15:09 PM PDT 24 |
Aug 03 07:37:45 PM PDT 24 |
25505389818 ps |
| T977 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.1311377508 |
|
|
Aug 03 07:53:40 PM PDT 24 |
Aug 03 08:07:37 PM PDT 24 |
5223005040 ps |
| T978 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3548761245 |
|
|
Aug 03 07:27:46 PM PDT 24 |
Aug 03 07:33:44 PM PDT 24 |
17654796216 ps |
| T979 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2917488586 |
|
|
Aug 03 07:40:59 PM PDT 24 |
Aug 03 08:31:10 PM PDT 24 |
18613543835 ps |
| T305 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3020510310 |
|
|
Aug 03 07:44:10 PM PDT 24 |
Aug 03 07:48:03 PM PDT 24 |
2953088090 ps |
| T980 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.991264842 |
|
|
Aug 03 07:24:47 PM PDT 24 |
Aug 03 08:03:10 PM PDT 24 |
22832146232 ps |
| T280 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.3313665570 |
|
|
Aug 03 07:56:03 PM PDT 24 |
Aug 03 08:04:05 PM PDT 24 |
5354221604 ps |
| T981 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.593889731 |
|
|
Aug 03 07:22:23 PM PDT 24 |
Aug 03 08:13:48 PM PDT 24 |
11363336724 ps |
| T982 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3211419179 |
|
|
Aug 03 07:36:23 PM PDT 24 |
Aug 03 07:45:17 PM PDT 24 |
3450201450 ps |
| T339 |
/workspace/coverage/default/2.chip_sw_flash_init.586659922 |
|
|
Aug 03 07:37:11 PM PDT 24 |
Aug 03 08:08:17 PM PDT 24 |
21454631475 ps |
| T10 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2100922815 |
|
|
Aug 03 07:06:36 PM PDT 24 |
Aug 03 07:10:38 PM PDT 24 |
3281527396 ps |
| T983 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.2037997294 |
|
|
Aug 03 07:34:38 PM PDT 24 |
Aug 03 07:39:05 PM PDT 24 |
2728866258 ps |
| T984 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.366765422 |
|
|
Aug 03 07:45:58 PM PDT 24 |
Aug 03 07:53:46 PM PDT 24 |
6077939308 ps |
| T337 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3559017702 |
|
|
Aug 03 07:07:31 PM PDT 24 |
Aug 03 08:39:34 PM PDT 24 |
46572306132 ps |
| T985 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.575177084 |
|
|
Aug 03 07:17:32 PM PDT 24 |
Aug 03 07:21:39 PM PDT 24 |
3528292984 ps |
| T986 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1756813613 |
|
|
Aug 03 07:08:51 PM PDT 24 |
Aug 03 08:11:23 PM PDT 24 |
17720692120 ps |
| T100 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.3256999890 |
|
|
Aug 03 07:13:48 PM PDT 24 |
Aug 03 07:24:53 PM PDT 24 |
4543768460 ps |
| T987 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.581426329 |
|
|
Aug 03 07:22:30 PM PDT 24 |
Aug 03 08:35:46 PM PDT 24 |
17555657198 ps |
| T988 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.2733624315 |
|
|
Aug 03 07:45:24 PM PDT 24 |
Aug 03 07:55:51 PM PDT 24 |
4643219224 ps |
| T989 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.3602533171 |
|
|
Aug 03 07:22:16 PM PDT 24 |
Aug 03 07:34:27 PM PDT 24 |
4565246664 ps |
| T111 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.877402465 |
|
|
Aug 03 07:21:42 PM PDT 24 |
Aug 03 07:28:27 PM PDT 24 |
5679532422 ps |
| T990 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1333375118 |
|
|
Aug 03 07:07:07 PM PDT 24 |
Aug 03 08:56:07 PM PDT 24 |
48773516102 ps |
| T489 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.867905213 |
|
|
Aug 03 07:56:06 PM PDT 24 |
Aug 03 08:05:26 PM PDT 24 |
5486295120 ps |
| T991 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.4163200265 |
|
|
Aug 03 07:25:52 PM PDT 24 |
Aug 03 07:30:40 PM PDT 24 |
2946808946 ps |
| T992 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.4132990786 |
|
|
Aug 03 07:26:02 PM PDT 24 |
Aug 03 07:55:30 PM PDT 24 |
22596215142 ps |
| T993 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.123024134 |
|
|
Aug 03 07:37:09 PM PDT 24 |
Aug 03 07:42:01 PM PDT 24 |
2546751866 ps |
| T994 |
/workspace/coverage/default/1.chip_sw_example_rom.643413128 |
|
|
Aug 03 07:20:49 PM PDT 24 |
Aug 03 07:23:10 PM PDT 24 |
2479870728 ps |
| T995 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3032220182 |
|
|
Aug 03 07:24:27 PM PDT 24 |
Aug 03 07:55:25 PM PDT 24 |
9493322003 ps |
| T515 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2283230146 |
|
|
Aug 03 07:26:51 PM PDT 24 |
Aug 03 07:33:17 PM PDT 24 |
3208528900 ps |
| T996 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.1840815011 |
|
|
Aug 03 07:51:24 PM PDT 24 |
Aug 03 08:04:16 PM PDT 24 |
5444254192 ps |
| T997 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.401998201 |
|
|
Aug 03 07:40:35 PM PDT 24 |
Aug 03 07:50:58 PM PDT 24 |
5224488860 ps |
| T998 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1353980500 |
|
|
Aug 03 07:24:21 PM PDT 24 |
Aug 03 07:47:36 PM PDT 24 |
9975916303 ps |
| T343 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.925220198 |
|
|
Aug 03 07:37:17 PM PDT 24 |
Aug 03 09:18:38 PM PDT 24 |
50715552080 ps |
| T999 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.2652125977 |
|
|
Aug 03 07:55:06 PM PDT 24 |
Aug 03 08:05:58 PM PDT 24 |
5489211012 ps |
| T1000 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1026923549 |
|
|
Aug 03 07:09:47 PM PDT 24 |
Aug 03 07:19:54 PM PDT 24 |
4176622760 ps |
| T1001 |
/workspace/coverage/default/1.chip_sw_otbn_randomness.3493603724 |
|
|
Aug 03 07:25:29 PM PDT 24 |
Aug 03 07:41:03 PM PDT 24 |
5385976204 ps |
| T470 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.581853886 |
|
|
Aug 03 07:54:41 PM PDT 24 |
Aug 03 08:04:41 PM PDT 24 |
6185994400 ps |
| T1002 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2861393088 |
|
|
Aug 03 07:40:59 PM PDT 24 |
Aug 03 07:46:24 PM PDT 24 |
3018833528 ps |
| T1003 |
/workspace/coverage/default/2.chip_sw_aes_entropy.821225061 |
|
|
Aug 03 07:40:50 PM PDT 24 |
Aug 03 07:44:46 PM PDT 24 |
3320255502 ps |
| T1004 |
/workspace/coverage/default/0.rom_e2e_static_critical.3355325885 |
|
|
Aug 03 07:23:37 PM PDT 24 |
Aug 03 08:44:26 PM PDT 24 |
17924596938 ps |
| T1005 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1278633805 |
|
|
Aug 03 07:37:57 PM PDT 24 |
Aug 03 09:09:58 PM PDT 24 |
45663847898 ps |
| T1006 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.1957926707 |
|
|
Aug 03 07:25:09 PM PDT 24 |
Aug 03 07:30:10 PM PDT 24 |
3773412129 ps |
| T368 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1794548732 |
|
|
Aug 03 07:08:46 PM PDT 24 |
Aug 03 07:17:45 PM PDT 24 |
3459868328 ps |
| T510 |
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2081483459 |
|
|
Aug 03 07:51:09 PM PDT 24 |
Aug 03 07:57:06 PM PDT 24 |
3702820526 ps |
| T1007 |
/workspace/coverage/default/0.chip_sw_aes_entropy.2070612539 |
|
|
Aug 03 07:12:37 PM PDT 24 |
Aug 03 07:17:24 PM PDT 24 |
2751540820 ps |
| T485 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.4169043233 |
|
|
Aug 03 07:47:28 PM PDT 24 |
Aug 03 07:58:03 PM PDT 24 |
4310227404 ps |
| T471 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.38952205 |
|
|
Aug 03 07:55:13 PM PDT 24 |
Aug 03 08:01:00 PM PDT 24 |
3048135068 ps |
| T1008 |
/workspace/coverage/default/93.chip_sw_all_escalation_resets.4089723534 |
|
|
Aug 03 07:55:49 PM PDT 24 |
Aug 03 08:03:38 PM PDT 24 |
4950652064 ps |
| T1009 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.3200415187 |
|
|
Aug 03 07:53:44 PM PDT 24 |
Aug 03 08:06:06 PM PDT 24 |
4422720792 ps |
| T539 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.1142051421 |
|
|
Aug 03 07:55:46 PM PDT 24 |
Aug 03 08:03:11 PM PDT 24 |
5394534472 ps |
| T1010 |
/workspace/coverage/default/3.chip_tap_straps_testunlock0.3213355154 |
|
|
Aug 03 07:45:13 PM PDT 24 |
Aug 03 07:54:46 PM PDT 24 |
6207145357 ps |
| T168 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1326764517 |
|
|
Aug 03 07:09:21 PM PDT 24 |
Aug 03 07:18:20 PM PDT 24 |
4228475104 ps |
| T1011 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.1441344334 |
|
|
Aug 03 07:33:24 PM PDT 24 |
Aug 03 07:40:19 PM PDT 24 |
4914084792 ps |
| T1012 |
/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3826235655 |
|
|
Aug 03 07:31:29 PM PDT 24 |
Aug 03 08:03:04 PM PDT 24 |
25986496371 ps |
| T1013 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1389160551 |
|
|
Aug 03 07:38:20 PM PDT 24 |
Aug 03 07:43:57 PM PDT 24 |
3225597144 ps |
| T401 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2881563438 |
|
|
Aug 03 07:51:07 PM PDT 24 |
Aug 03 07:56:43 PM PDT 24 |
2933310872 ps |
| T1014 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3239645642 |
|
|
Aug 03 07:29:02 PM PDT 24 |
Aug 03 07:39:53 PM PDT 24 |
7930899760 ps |