Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.09			84.09

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_i2c0	83.91			83.91
tb.dut.top_earlgrey.u_i2c1	84.00			84.00
tb.dut.top_earlgrey.u_i2c2	84.00			84.00

---

Module Instance : tb.dut.top_earlgrey.u_i2c0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.91			83.91

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.91			83.91

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.19	92.47		87.09			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.00			84.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.00			84.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.19	92.47		87.09			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.00			84.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.00			84.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.19	92.47		87.09			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	54	40	74.07
Total Bits	352	296	84.09
Total Bits 0->1	176	148	84.09
Total Bits 1->0	176	148	84.09

Ports	54	40	74.07
Port Bits	352	296	84.09
Port Bits 0->1	176	148	84.09
Port Bits 1->0	176	148	84.09

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T32	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T11,T227,T228	Yes	T11,T227,T228	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T11,T227,T228	Yes	T11,T227,T228	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T6,*T52	Yes	T4,T6,T52	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T6,*T52,*T53	Yes	T6,T52,T53	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T97,T159,T11	Yes	T97,T159,T11	INPUT
tl_o.a_ready	Yes	Yes	T97,T159,T11	Yes	T97,T159,T11	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T11,T227,T228	Yes	T11,T227,T228	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T159,T11,T227	Yes	T97,T159,T11	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T159,*T160,T229	Yes	T97,T159,T11	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T159,T11,T227	Yes	T97,T159,T11	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T159,*T11,*T227	Yes	T97,T159,T11	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T159,T160,T229	Yes	T97,T159,T11	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T11,*T227,*T228	Yes	T11,T227,T228	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T97,T159,T11	Yes	T97,T159,T11	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T199,T62	Yes	T3,T199,T62	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T62,T96,T98	Yes	T62,T96,T98	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T62,T96,T98	Yes	T62,T96,T98	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T199,T62	Yes	T3,T199,T62	OUTPUT
cio_scl_i	Yes	Yes	T11,T227,T228	Yes	T11,T227,T228	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T11,T227,T228	Yes	T11,T227,T228	OUTPUT
cio_sda_i	Yes	Yes	T11,T227,T228	Yes	T11,T227,T228	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T11,T227,T228	Yes	T11,T227,T228	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T227,T228,T230	Yes	T227,T228,T230	OUTPUT
intr_rx_threshold_o	Yes	Yes	T227,T228,T230	Yes	T227,T228,T230	OUTPUT
intr_acq_threshold_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_rx_overflow_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_controller_halt_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_scl_interference_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_sda_interference_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_sda_unstable_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_cmd_complete_o	Yes	Yes	T227,T228,T230	Yes	T227,T228,T230	OUTPUT
intr_tx_stretch_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_tx_threshold_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_acq_stretch_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_unexp_stop_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_host_timeout_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c0

	Total	Covered	Percent
Totals	54	40	74.07
Total Bits	348	292	83.91
Total Bits 0->1	174	146	83.91
Total Bits 1->0	174	146	83.91

Ports	54	40	74.07
Port Bits	348	292	83.91
Port Bits 0->1	174	146	83.91
Port Bits 1->0	174	146	83.91

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T32	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T11,T227,T230	Yes	T11,T227,T230	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T11,T227,T230	Yes	T11,T227,T230	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T6,*T52	Yes	T4,T6,T52	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T6,*T52,*T53	Yes	T6,T52,T53	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T97,T159,T11	Yes	T97,T159,T11	INPUT
tl_o.a_ready	Yes	Yes	T97,T159,T11	Yes	T97,T159,T11	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T11,T227,T230	Yes	T11,T227,T230	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T159,T11,T227	Yes	T97,T159,T11	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T159,*T160,T229	Yes	T97,T159,T11	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T159,T11,T227	Yes	T97,T159,T11	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T159,*T11,*T227	Yes	T97,T159,T11	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T159,T160,T229	Yes	T97,T159,T11	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T11,*T227,*T230	Yes	T11,T227,T230	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T97,T159,T11	Yes	T97,T159,T11	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T96,T98,T99	Yes	T96,T98,T99	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T96,T98,T99	Yes	T96,T98,T99	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
cio_scl_i	Yes	Yes	T11,T227,T230	Yes	T11,T227,T230	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T11,T227,T230	Yes	T11,T227,T230	OUTPUT
cio_sda_i	Yes	Yes	T11,T227,T230	Yes	T11,T227,T230	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T11,T227,T230	Yes	T11,T227,T230	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T227,T230,T231	Yes	T227,T230,T231	OUTPUT
intr_rx_threshold_o	Yes	Yes	T227,T230,T231	Yes	T227,T230,T231	OUTPUT
intr_acq_threshold_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_rx_overflow_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_controller_halt_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_scl_interference_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_sda_interference_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_sda_unstable_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_cmd_complete_o	Yes	Yes	T227,T230,T231	Yes	T227,T230,T231	OUTPUT
intr_tx_stretch_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_tx_threshold_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_acq_stretch_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_unexp_stop_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_host_timeout_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c1

	Total	Covered	Percent
Totals	54	40	74.07
Total Bits	350	294	84.00
Total Bits 0->1	175	147	84.00
Total Bits 1->0	175	147	84.00

Ports	54	40	74.07
Port Bits	350	294	84.00
Port Bits 0->1	175	147	84.00
Port Bits 1->0	175	147	84.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T32	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T11,T228,T12	Yes	T11,T228,T12	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T11,T228,T12	Yes	T11,T228,T12	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T6,*T52	Yes	T4,T6,T52	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T6,*T52,*T53	Yes	T6,T52,T53	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T97,T159,T11	Yes	T97,T159,T11	INPUT
tl_o.a_ready	Yes	Yes	T97,T159,T11	Yes	T97,T159,T11	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T11,T228,T12	Yes	T11,T228,T12	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T159,T11,T228	Yes	T97,T159,T11	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T159,*T160,T229	Yes	T97,T159,T11	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T159,T11,T228	Yes	T97,T159,T11	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T11,*T228,*T12	Yes	T97,T11,T228	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T159,T160,T229	Yes	T97,T159,T11	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T11,*T228,*T12	Yes	T11,T228,T12	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T97,T159,T11	Yes	T97,T159,T11	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T199,T62,T96	Yes	T199,T62,T96	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T62,T96,T98	Yes	T62,T96,T98	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T62,T96,T98	Yes	T62,T96,T98	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T199,T62,T96	Yes	T199,T62,T96	OUTPUT
cio_scl_i	Yes	Yes	T11,T228,T12	Yes	T11,T228,T12	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T11,T228,T12	Yes	T11,T228,T12	OUTPUT
cio_sda_i	Yes	Yes	T11,T228,T12	Yes	T11,T228,T12	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T11,T228,T12	Yes	T11,T228,T12	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T228,T187,T188	Yes	T228,T187,T188	OUTPUT
intr_rx_threshold_o	Yes	Yes	T228,T187,T188	Yes	T228,T187,T188	OUTPUT
intr_acq_threshold_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_rx_overflow_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_controller_halt_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_scl_interference_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_sda_interference_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_sda_unstable_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_cmd_complete_o	Yes	Yes	T228,T187,T188	Yes	T228,T187,T188	OUTPUT
intr_tx_stretch_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_tx_threshold_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_acq_stretch_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_unexp_stop_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_host_timeout_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c2

	Total	Covered	Percent
Totals	54	40	74.07
Total Bits	350	294	84.00
Total Bits 0->1	175	147	84.00
Total Bits 1->0	175	147	84.00

Ports	54	40	74.07
Port Bits	350	294	84.00
Port Bits 0->1	175	147	84.00
Port Bits 1->0	175	147	84.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T32	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T11,T12,T229	Yes	T11,T12,T229	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T11,T12,T229	Yes	T11,T12,T229	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[16:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T6,*T52	Yes	T4,T6,T52	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T6,*T52,*T53	Yes	T6,T52,T53	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T97,T159,T11	Yes	T97,T159,T11	INPUT
tl_o.a_ready	Yes	Yes	T97,T159,T11	Yes	T97,T159,T11	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T11,T12,T45	Yes	T11,T12,T45	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T159,T11,T160	Yes	T97,T159,T11	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T159,*T160,T229	Yes	T97,T159,T11	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T159,T11,T160	Yes	T97,T159,T11	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T11,*T12,*T229	Yes	T97,T11,T105	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T159,T160,T229	Yes	T97,T159,T11	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T11,*T12,*T229	Yes	T11,T12,T229	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T97,T159,T11	Yes	T97,T159,T11	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T62,T96	Yes	T3,T62,T96	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T62,T96,T98	Yes	T62,T96,T98	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T62,T96,T98	Yes	T62,T96,T98	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T62,T96	Yes	T3,T62,T96	OUTPUT
cio_scl_i	Yes	Yes	T11,T12,T45	Yes	T11,T12,T45	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T11,T12,T45	Yes	T11,T12,T45	OUTPUT
cio_sda_i	Yes	Yes	T11,T12,T45	Yes	T11,T12,T45	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T11,T12,T45	Yes	T11,T12,T45	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T187,T188,T232	Yes	T187,T188,T232	OUTPUT
intr_rx_threshold_o	Yes	Yes	T187,T188,T232	Yes	T187,T188,T232	OUTPUT
intr_acq_threshold_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_rx_overflow_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_controller_halt_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_scl_interference_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_sda_interference_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_sda_unstable_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_cmd_complete_o	Yes	Yes	T187,T188,T232	Yes	T187,T188,T232	OUTPUT
intr_tx_stretch_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_tx_threshold_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_acq_stretch_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_unexp_stop_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT
intr_host_timeout_o	Yes	Yes	T187,T188,T189	Yes	T187,T188,T189	OUTPUT

*Tests covering at least one bit in the range