| | | | | | | | |
| clk_ctrl_and_main_pd_sva_if |
100.00 |
|
|
100.00 |
|
|
|
| u_adc_ctrl_aon |
89.81 |
|
|
89.81 |
|
|
|
| u_aes |
96.62 |
|
|
96.62 |
|
|
|
| u_alert_handler |
97.29 |
|
|
97.29 |
|
|
|
| u_aon_timer_aon |
90.13 |
|
|
90.13 |
|
|
|
| u_clkmgr_aon |
94.93 |
|
|
94.93 |
|
|
|
| u_csrng |
96.70 |
|
|
96.70 |
|
|
|
| u_dft_tap_breakout |
100.00 |
100.00 |
|
100.00 |
|
|
|
| u_edn0 |
95.12 |
|
|
95.12 |
|
|
|
u_edn1 |
92.30 |
|
|
92.30 |
|
|
|
| u_entropy_src |
88.09 |
|
|
88.09 |
|
|
|
| u_flash_ctrl |
86.89 |
|
|
86.89 |
|
|
|
| u_gpio |
94.07 |
|
|
94.07 |
|
|
|
| u_hmac |
83.54 |
|
|
83.54 |
|
|
|
| u_i2c0 |
83.91 |
|
|
83.91 |
|
|
|
| u_i2c1 |
84.00 |
|
|
84.00 |
|
|
|
| u_i2c2 |
84.00 |
|
|
84.00 |
|
|
|
| u_keymgr |
89.25 |
|
|
89.25 |
|
|
|
| u_kmac |
99.22 |
|
|
99.22 |
|
|
|
| u_lc_ctrl |
93.09 |
|
|
93.09 |
|
|
|
| u_otbn |
98.03 |
|
|
98.03 |
|
|
|
| u_otp_ctrl |
83.89 |
|
|
83.89 |
|
|
|
| u_pattgen |
88.67 |
|
|
88.67 |
|
|
|
| u_pinmux_aon |
90.34 |
88.29 |
75.66 |
97.99 |
|
90.47 |
99.30 |
| gen_alert_tx[0].u_prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
| gen_wkup_detect[0].u_pinmux_wkup |
87.21 |
88.89 |
90.91 |
|
|
81.82 |
|
| u_prim_filter |
93.27 |
100.00 |
88.89 |
|
|
90.91 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_wkup_detect[1].u_pinmux_wkup |
77.78 |
83.33 |
77.27 |
|
|
72.73 |
|
| u_prim_filter |
93.27 |
100.00 |
88.89 |
|
|
90.91 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_wkup_detect[2].u_pinmux_wkup |
60.10 |
66.67 |
45.45 |
|
|
68.18 |
|
| u_prim_filter |
76.27 |
82.35 |
55.56 |
|
|
90.91 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_wkup_detect[3].u_pinmux_wkup |
56.14 |
63.89 |
40.91 |
|
|
63.64 |
|
| u_prim_filter |
67.58 |
76.47 |
44.44 |
|
|
81.82 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_wkup_detect[4].u_pinmux_wkup |
56.14 |
63.89 |
40.91 |
|
|
63.64 |
|
| u_prim_filter |
67.58 |
76.47 |
44.44 |
|
|
81.82 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_wkup_detect[5].u_pinmux_wkup |
74.41 |
77.78 |
72.73 |
|
|
72.73 |
|
| u_prim_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_wkup_detect[6].u_pinmux_wkup |
78.37 |
80.56 |
81.82 |
|
|
72.73 |
|
| u_prim_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_wkup_detect[7].u_pinmux_wkup |
76.85 |
80.56 |
77.27 |
|
|
72.73 |
|
| u_prim_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_pinmux_strap_sampling |
98.82 |
99.62 |
95.65 |
|
|
100.00 |
100.00 |
| subtree... |
|
|
|
|
|
|
|
| u_reg |
88.41 |
87.34 |
73.99 |
|
|
92.31 |
100.00 |
| subtree... |
|
|
|
|
|
|
|
| u_usbdev_aon_wake |
98.43 |
100.00 |
95.59 |
|
|
98.11 |
100.00 |
| filter_activity |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| filter_bus_reset |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| filter_sense |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_async.prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_pullup_en_cdc |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_pwm_aon |
90.20 |
|
|
90.20 |
|
|
|
| u_pwrmgr_aon |
93.07 |
|
|
93.07 |
|
|
|
| u_rom_ctrl |
97.26 |
|
|
97.26 |
|
|
|
| u_rstmgr_aon |
92.31 |
|
|
92.31 |
|
|
|
| u_rv_core_ibex |
91.48 |
96.51 |
81.54 |
90.41 |
|
96.77 |
92.14 |
| subtree... |
|
|
|
|
|
|
|
| u_rv_dm |
86.99 |
|
|
86.99 |
|
|
|
| u_rv_plic |
91.51 |
93.92 |
83.79 |
90.81 |
|
92.60 |
96.43 |
| gen_alert_tx[0].u_prim_alert_sender |
91.67 |
|
|
91.67 |
|
|
|
| gen_target[0].u_target |
91.67 |
89.34 |
77.33 |
|
|
100.00 |
100.00 |
| u_prim_max_tree |
91.64 |
89.27 |
77.30 |
|
|
100.00 |
100.00 |
| u_gateway |
75.00 |
100.00 |
25.00 |
|
|
100.00 |
|
| u_prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_reg |
93.03 |
94.26 |
87.90 |
|
|
89.97 |
100.00 |
| subtree... |
|
|
|
|
|
|
|
| u_rv_timer |
89.73 |
|
|
89.73 |
|
|
|
| u_sensor_ctrl_aon |
90.14 |
93.87 |
87.57 |
79.93 |
|
95.56 |
93.75 |
| gen_alert_sync_assign[0].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[10].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[1].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[2].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[3].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[4].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[5].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[6].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[7].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[8].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| gen_alert_sync_assign[9].u_alert_in_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| u_alert_n_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_alert_p_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_init_chg |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| g_sync.u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_init_intr |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| u_io_intr |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| u_io_status_chg |
100.00 |
100.00 |
|
|
|
100.00 |
|
| g_sync.u_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_prim_sec_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| u_reg |
93.88 |
93.33 |
86.93 |
|
|
95.24 |
100.00 |
| subtree... |
|
|
|
|
|
|
|
| u_wake_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_spi_device |
88.66 |
|
|
88.66 |
|
|
|
| u_spi_host0 |
84.66 |
|
|
84.66 |
|
|
|
| u_spi_host1 |
85.80 |
|
|
85.80 |
|
|
|
| u_sram_ctrl_main |
93.84 |
|
|
93.84 |
|
|
|
| u_sram_ctrl_ret_aon |
94.56 |
|
|
94.56 |
|
|
|
| u_sysrst_ctrl_aon |
91.02 |
|
|
91.02 |
|
|
|
| u_uart0 |
90.13 |
|
|
90.13 |
|
|
|
| u_uart1 |
90.20 |
|
|
90.20 |
|
|
|
| u_uart2 |
90.20 |
|
|
90.20 |
|
|
|
| u_uart3 |
90.26 |
|
|
90.26 |
|
|
|
| u_usbdev |
83.33 |
|
|
83.33 |
|
|
|
| u_xbar_main |
81.62 |
|
|
81.62 |
|
|
|
| u_xbar_peri |
88.40 |
|
|
88.40 |
|
|
|