Unified Coverage Report :: Module :: sysrst_ctrl

Module : sysrst_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.02			91.02

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_sysrst_ctrl_aon	91.02			91.02

---

Module Instance : tb.dut.top_earlgrey.u_sysrst_ctrl_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.02			91.02

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.02			91.02

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.19	92.47		87.09			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : sysrst_ctrl

	Total	Covered	Percent
Totals	50	42	84.00
Total Bits	334	304	91.02
Total Bits 0->1	167	152	91.02
Total Bits 1->0	167	152	91.02

Ports	50	42	84.00
Port Bits	334	304	91.02
Port Bits 0->1	167	152	91.02
Port Bits 1->0	167	152	91.02

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T32	Yes	T1,T2,T3	INPUT
rst_aon_ni	Yes	Yes	T2,T3,T32	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T37,T60,T6	Yes	T37,T60,T6	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T37,T60,T6	Yes	T37,T60,T6	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[7:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[21:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[22]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T6,*T52	Yes	T4,T6,T52	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T6,*T52,*T53	Yes	T6,T52,T53	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T37,T60,T6	Yes	T37,T60,T6	INPUT
tl_o.a_ready	Yes	Yes	T37,T60,T6	Yes	T37,T60,T6	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T37,T60,T6	Yes	T37,T60,T6	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T37,T60,T6	Yes	T37,T60,T6	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T60,T6,T274	Yes	T37,T60,T6	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T37,T60,T6	Yes	T37,T60,T6	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T6,*T110,*T37	Yes	T6,T110,T37	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T60,T6,T274	Yes	T37,T60,T6	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T37,*T60,*T6	Yes	T37,T60,T6	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T37,T60,T6	Yes	T37,T60,T6	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T6,T334,T96	Yes	T6,T334,T96	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T334,T96,T99	Yes	T96,T99,T124	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T96,T99,T124	Yes	T334,T96,T99	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T6,T334,T96	Yes	T6,T334,T96	OUTPUT
wkup_req_o	Yes	Yes	T60,T274,T16	Yes	T37,T60,T274	OUTPUT
rst_req_o	Yes	Yes	T60,T274,T21	Yes	T60,T274,T21	OUTPUT
intr_event_detected_o	Yes	Yes	T138,T190,T364	Yes	T138,T190,T364	OUTPUT
cio_ac_present_i	Yes	Yes	T242,T138,T244	Yes	T242,T138,T244	INPUT
cio_ec_rst_l_i	Yes	Yes	T6,T242,T21	Yes	T6,T242,T21	INPUT
cio_key0_in_i	Yes	Yes	T60,T274,T242	Yes	T60,T274,T242	INPUT
cio_key1_in_i	Yes	Yes	T242,T21,T22	Yes	T242,T21,T22	INPUT
cio_key2_in_i	Yes	Yes	T242,T22,T138	Yes	T242,T22,T138	INPUT
cio_pwrb_in_i	Yes	Yes	T242,T16,T115	Yes	T242,T16,T115	INPUT
cio_lid_open_i	Yes	Yes	T37,T242,T38	Yes	T37,T242,T38	INPUT
cio_flash_wp_l_i	Yes	Yes	T21,T22,T138	Yes	T37,T242,T21	INPUT
cio_bat_disable_o	Yes	Yes	T60,T274,T326	Yes	T60,T274,T21	OUTPUT
cio_flash_wp_l_o	Yes	Yes	T21,T22,T243	Yes	T37,T21,T22	OUTPUT
cio_ec_rst_l_o	Yes	Yes	T6,T21,T22	Yes	T6,T21,T22	OUTPUT
cio_key0_out_o	Yes	Yes	T60,T274,T242	Yes	T60,T274,T242	OUTPUT
cio_key1_out_o	Yes	Yes	T242,T21,T22	Yes	T242,T21,T22	OUTPUT
cio_key2_out_o	Yes	Yes	T242,T22,T138	Yes	T242,T21,T22	OUTPUT
cio_pwrb_out_o	Yes	Yes	T242,T16,T115	Yes	T242,T16,T21	OUTPUT
cio_z3_wakeup_o	Yes	Yes	T22,T243,T245	Yes	T37,T21,T22	OUTPUT
cio_bat_disable_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_flash_wp_l_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_ec_rst_l_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_key0_out_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_key1_out_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_key2_out_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_pwrb_out_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_z3_wakeup_en_o	Unreachable	Unreachable		Unreachable		OUTPUT

*Tests covering at least one bit in the range