Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.26			90.26

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	90.13			90.13
tb.dut.top_earlgrey.u_uart1	90.20			90.20
tb.dut.top_earlgrey.u_uart2	90.20			90.20
tb.dut.top_earlgrey.u_uart3	90.26			90.26

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.19	92.47		87.09			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.19	92.47		87.09			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.19	92.47		87.09			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.26			90.26

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.26			90.26

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.19	92.47		87.09			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	308	278	90.26
Total Bits 0->1	154	139	90.26
Total Bits 1->0	154	139	90.26

Ports	40	32	80.00
Port Bits	308	278	90.26
Port Bits 0->1	154	139	90.26
Port Bits 1->0	154	139	90.26

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T32	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T316,T92,T49	Yes	T316,T92,T49	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T316,T92,T49	Yes	T316,T92,T49	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T6,*T52	Yes	T4,T6,T52	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T6,*T52,*T53	Yes	T6,T52,T53	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T316,T92,T49	Yes	T316,T92,T49	INPUT
tl_o.a_ready	Yes	Yes	T316,T92,T49	Yes	T316,T92,T49	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T316,T92,T49	Yes	T316,T92,T49	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T316,T92,T49	Yes	T316,T92,T49	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T46,T47,*T159	Yes	T316,T92,T49	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T316,T92,T49	Yes	T316,T92,T49	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T110,*T178,*T319	Yes	T110,T178,T319	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T46,T47,T159	Yes	T316,T92,T49	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T316,*T92,*T49	Yes	T316,T92,T49	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T316,T92,T49	Yes	T316,T92,T49	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T317,T334,T96	Yes	T317,T334,T96	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T96,T99,T124	Yes	T96,T99,T124	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T96,T99,T124	Yes	T96,T99,T124	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T317,T334,T96	Yes	T317,T334,T96	OUTPUT
cio_rx_i	Yes	Yes	T2,T3,T32	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T316,T92,T49	Yes	T316,T92,T49	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T316,T92,T305	Yes	T316,T92,T305	OUTPUT
intr_tx_empty_o	Yes	Yes	T316,T92,T305	Yes	T316,T92,T305	OUTPUT
intr_rx_watermark_o	Yes	Yes	T316,T92,T305	Yes	T316,T92,T305	OUTPUT
intr_tx_done_o	Yes	Yes	T316,T92,T305	Yes	T316,T92,T305	OUTPUT
intr_rx_overflow_o	Yes	Yes	T316,T92,T305	Yes	T316,T92,T305	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	OUTPUT
intr_rx_break_err_o	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	OUTPUT
intr_rx_timeout_o	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	304	274	90.13
Total Bits 0->1	152	137	90.13
Total Bits 1->0	152	137	90.13

Ports	40	32	80.00
Port Bits	304	274	90.13
Port Bits 0->1	152	137	90.13
Port Bits 1->0	152	137	90.13

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T32	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T316,T49,T175	Yes	T316,T49,T175	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T316,T49,T175	Yes	T316,T49,T175	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T6,*T52	Yes	T4,T6,T52	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T6,*T52,*T53	Yes	T6,T52,T53	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T316,T49,T175	Yes	T316,T49,T175	INPUT
tl_o.a_ready	Yes	Yes	T316,T49,T50	Yes	T316,T49,T50	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T316,T49,T50	Yes	T316,T49,T50	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T316,T49,T50	Yes	T316,T49,T50	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T46,T47,*T159	Yes	T316,T49,T50	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T316,T49,T50	Yes	T316,T49,T50	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T110,*T178,*T319	Yes	T110,T178,T319	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T46,T47,T159	Yes	T316,T49,T50	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T316,*T49,*T50	Yes	T316,T49,T50	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T316,T49,T50	Yes	T316,T49,T50	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T96,T97,T99	Yes	T96,T97,T99	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T96,T99,T124	Yes	T96,T99,T124	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T96,T99,T124	Yes	T96,T99,T124	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T96,T97,T99	Yes	T96,T97,T99	OUTPUT
cio_rx_i	Yes	Yes	T2,T3,T32	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T316,T49,T50	Yes	T316,T49,T50	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T316,T348,T349	Yes	T316,T348,T349	OUTPUT
intr_tx_empty_o	Yes	Yes	T316,T348,T349	Yes	T316,T348,T349	OUTPUT
intr_rx_watermark_o	Yes	Yes	T316,T348,T349	Yes	T316,T348,T349	OUTPUT
intr_tx_done_o	Yes	Yes	T316,T348,T349	Yes	T316,T348,T349	OUTPUT
intr_rx_overflow_o	Yes	Yes	T316,T348,T349	Yes	T316,T348,T349	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	OUTPUT
intr_rx_break_err_o	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	OUTPUT
intr_rx_timeout_o	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	306	276	90.20
Total Bits 0->1	153	138	90.20
Total Bits 1->0	153	138	90.20

Ports	40	32	80.00
Port Bits	306	276	90.20
Port Bits 0->1	153	138	90.20
Port Bits 1->0	153	138	90.20

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T32	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T305,T320,T11	Yes	T305,T320,T11	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T305,T320,T11	Yes	T305,T320,T11	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T6,*T52	Yes	T4,T6,T52	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T6,*T52,*T53	Yes	T6,T52,T53	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T305,T320,T97	Yes	T305,T320,T97	INPUT
tl_o.a_ready	Yes	Yes	T305,T320,T97	Yes	T305,T320,T97	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T305,T320,T11	Yes	T305,T320,T11	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T305,T320,T159	Yes	T305,T320,T97	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T159,T110,*T160	Yes	T305,T320,T97	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T305,T320,T159	Yes	T305,T320,T97	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T110,*T305,*T320	Yes	T110,T305,T320	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T159,T110,T160	Yes	T305,T320,T97	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T305,*T320,*T11	Yes	T305,T320,T11	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T305,T320,T97	Yes	T305,T320,T97	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T334,T96,T97	Yes	T334,T96,T97	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T96,T99,T124	Yes	T96,T99,T124	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T96,T99,T124	Yes	T96,T99,T124	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T334,T96,T97	Yes	T334,T96,T97	OUTPUT
cio_rx_i	Yes	Yes	T305,T320,T363	Yes	T305,T320,T363	INPUT
cio_tx_o	Yes	Yes	T305,T320,T363	Yes	T305,T320,T363	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T305,T320,T363	Yes	T305,T320,T363	OUTPUT
intr_tx_empty_o	Yes	Yes	T305,T320,T363	Yes	T305,T320,T363	OUTPUT
intr_rx_watermark_o	Yes	Yes	T305,T320,T363	Yes	T305,T320,T363	OUTPUT
intr_tx_done_o	Yes	Yes	T305,T320,T363	Yes	T305,T320,T363	OUTPUT
intr_rx_overflow_o	Yes	Yes	T305,T320,T363	Yes	T305,T320,T363	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	OUTPUT
intr_rx_break_err_o	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	OUTPUT
intr_rx_timeout_o	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	306	276	90.20
Total Bits 0->1	153	138	90.20
Total Bits 1->0	153	138	90.20

Ports	40	32	80.00
Port Bits	306	276	90.20
Port Bits 0->1	153	138	90.20
Port Bits 1->0	153	138	90.20

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T32	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T92,T93,T321	Yes	T92,T93,T321	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T92,T93,T321	Yes	T92,T93,T321	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T6,*T52	Yes	T4,T6,T52	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T6,*T52,*T53	Yes	T6,T52,T53	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T92,T97,T93	Yes	T92,T97,T93	INPUT
tl_o.a_ready	Yes	Yes	T92,T97,T93	Yes	T92,T97,T93	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T92,T93,T321	Yes	T92,T93,T321	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T92,T93,T159	Yes	T92,T97,T93	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T159,T110,*T160	Yes	T92,T97,T93	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T92,T93,T159	Yes	T92,T97,T93	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T110,*T92,*T93	Yes	T110,T92,T93	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T159,T110,T160	Yes	T92,T97,T93	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T92,*T93,*T321	Yes	T92,T93,T321	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T92,T97,T93	Yes	T92,T97,T93	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T96,T97,T99	Yes	T96,T97,T99	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T96,T99,T124	Yes	T96,T99,T124	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T96,T99,T124	Yes	T96,T99,T124	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T96,T97,T99	Yes	T96,T97,T99	OUTPUT
cio_rx_i	Yes	Yes	T92,T93,T321	Yes	T92,T93,T321	INPUT
cio_tx_o	Yes	Yes	T92,T93,T321	Yes	T92,T93,T321	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T92,T93,T321	Yes	T92,T93,T321	OUTPUT
intr_tx_empty_o	Yes	Yes	T92,T93,T321	Yes	T92,T93,T321	OUTPUT
intr_rx_watermark_o	Yes	Yes	T92,T93,T321	Yes	T92,T93,T321	OUTPUT
intr_tx_done_o	Yes	Yes	T92,T93,T321	Yes	T92,T93,T321	OUTPUT
intr_rx_overflow_o	Yes	Yes	T92,T93,T321	Yes	T92,T93,T321	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	OUTPUT
intr_rx_break_err_o	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	OUTPUT
intr_rx_timeout_o	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	308	278	90.26
Total Bits 0->1	154	139	90.26
Total Bits 1->0	154	139	90.26

Ports	40	32	80.00
Port Bits	308	278	90.26
Port Bits 0->1	154	139	90.26
Port Bits 1->0	154	139	90.26

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T32	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T14,T15,T322	Yes	T14,T15,T322	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T14,T15,T322	Yes	T14,T15,T322	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T6,*T52	Yes	T4,T6,T52	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T6,*T52,*T53	Yes	T6,T52,T53	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T14,T97,T15	Yes	T14,T97,T15	INPUT
tl_o.a_ready	Yes	Yes	T14,T97,T15	Yes	T14,T97,T15	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T14,T15,T322	Yes	T14,T15,T322	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T14,T15,T322	Yes	T14,T97,T15	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T159,T110,*T160	Yes	T14,T97,T15	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T14,T15,T322	Yes	T14,T97,T15	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T110,*T14,*T15	Yes	T110,T14,T15	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T159,T110,T160	Yes	T14,T97,T15	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T14,*T15,*T322	Yes	T14,T15,T322	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T14,T97,T15	Yes	T14,T97,T15	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T317,T96,T97	Yes	T317,T96,T97	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T96,T99,T124	Yes	T96,T99,T124	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T96,T99,T124	Yes	T96,T99,T124	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T317,T96,T97	Yes	T317,T96,T97	OUTPUT
cio_rx_i	Yes	Yes	T14,T15,T322	Yes	T14,T15,T322	INPUT
cio_tx_o	Yes	Yes	T14,T15,T322	Yes	T14,T15,T322	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T14,T15,T322	Yes	T14,T15,T322	OUTPUT
intr_tx_empty_o	Yes	Yes	T14,T15,T322	Yes	T14,T15,T322	OUTPUT
intr_rx_watermark_o	Yes	Yes	T14,T15,T322	Yes	T14,T15,T322	OUTPUT
intr_tx_done_o	Yes	Yes	T14,T15,T322	Yes	T14,T15,T322	OUTPUT
intr_rx_overflow_o	Yes	Yes	T14,T15,T322	Yes	T14,T15,T322	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	OUTPUT
intr_rx_break_err_o	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	OUTPUT
intr_rx_timeout_o	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	OUTPUT

*Tests covering at least one bit in the range