Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T20,T65,T58 |
1 | 0 | Covered | T20,T65,T58 |
1 | 1 | Covered | T20,T65,T58 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T20,T65,T58 |
1 | 0 | Covered | T20,T65,T58 |
1 | 1 | Covered | T20,T65,T58 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
11591 |
0 |
0 |
T16 |
441 |
0 |
0 |
0 |
T20 |
4413 |
2 |
0 |
0 |
T21 |
390 |
0 |
0 |
0 |
T27 |
241854 |
0 |
0 |
0 |
T51 |
1038 |
0 |
0 |
0 |
T58 |
40078 |
7 |
0 |
0 |
T59 |
0 |
8 |
0 |
0 |
T60 |
0 |
2 |
0 |
0 |
T61 |
0 |
7 |
0 |
0 |
T62 |
0 |
7 |
0 |
0 |
T63 |
0 |
4 |
0 |
0 |
T65 |
0 |
2 |
0 |
0 |
T78 |
0 |
2 |
0 |
0 |
T80 |
46154 |
3 |
0 |
0 |
T91 |
44291 |
0 |
0 |
0 |
T106 |
0 |
4 |
0 |
0 |
T107 |
0 |
4 |
0 |
0 |
T108 |
386 |
0 |
0 |
0 |
T109 |
481 |
0 |
0 |
0 |
T110 |
604 |
0 |
0 |
0 |
T111 |
472 |
0 |
0 |
0 |
T112 |
483 |
0 |
0 |
0 |
T113 |
753 |
0 |
0 |
0 |
T150 |
0 |
6 |
0 |
0 |
T151 |
0 |
6 |
0 |
0 |
T152 |
0 |
14 |
0 |
0 |
T155 |
551926 |
0 |
0 |
0 |
T255 |
25819 |
0 |
0 |
0 |
T381 |
0 |
2 |
0 |
0 |
T382 |
0 |
13 |
0 |
0 |
T384 |
0 |
1 |
0 |
0 |
T397 |
79137 |
0 |
0 |
0 |
T409 |
0 |
2 |
0 |
0 |
T415 |
0 |
2 |
0 |
0 |
T416 |
0 |
2 |
0 |
0 |
T417 |
99535 |
0 |
0 |
0 |
T418 |
24557 |
0 |
0 |
0 |
T419 |
55084 |
0 |
0 |
0 |
T420 |
138157 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
11604 |
0 |
0 |
T16 |
25125 |
0 |
0 |
0 |
T20 |
165389 |
2 |
0 |
0 |
T21 |
20089 |
0 |
0 |
0 |
T27 |
241854 |
0 |
0 |
0 |
T51 |
55930 |
0 |
0 |
0 |
T58 |
40078 |
8 |
0 |
0 |
T59 |
0 |
9 |
0 |
0 |
T60 |
0 |
3 |
0 |
0 |
T61 |
0 |
7 |
0 |
0 |
T62 |
0 |
4 |
0 |
0 |
T63 |
0 |
4 |
0 |
0 |
T65 |
0 |
2 |
0 |
0 |
T78 |
0 |
2 |
0 |
0 |
T80 |
681 |
3 |
0 |
0 |
T91 |
44291 |
0 |
0 |
0 |
T106 |
0 |
4 |
0 |
0 |
T107 |
0 |
4 |
0 |
0 |
T108 |
23099 |
0 |
0 |
0 |
T109 |
18449 |
0 |
0 |
0 |
T110 |
39382 |
0 |
0 |
0 |
T111 |
22906 |
0 |
0 |
0 |
T112 |
24410 |
0 |
0 |
0 |
T113 |
60189 |
0 |
0 |
0 |
T150 |
0 |
6 |
0 |
0 |
T151 |
0 |
6 |
0 |
0 |
T152 |
0 |
14 |
0 |
0 |
T155 |
551926 |
0 |
0 |
0 |
T255 |
25819 |
0 |
0 |
0 |
T381 |
0 |
2 |
0 |
0 |
T382 |
0 |
13 |
0 |
0 |
T384 |
0 |
1 |
0 |
0 |
T397 |
79137 |
0 |
0 |
0 |
T409 |
0 |
2 |
0 |
0 |
T415 |
0 |
2 |
0 |
0 |
T416 |
0 |
2 |
0 |
0 |
T417 |
99535 |
0 |
0 |
0 |
T418 |
24557 |
0 |
0 |
0 |
T419 |
55084 |
0 |
0 |
0 |
T420 |
138157 |
0 |
0 |
0 |