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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.03 95.50 93.78 95.28 94.53 97.53 99.55


Total test records in report: 2934
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T1075 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.331242288 Aug 07 07:57:18 PM PDT 24 Aug 07 09:02:04 PM PDT 24 13606286837 ps
T1076 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2028730363 Aug 07 08:20:43 PM PDT 24 Aug 07 08:24:26 PM PDT 24 2861270590 ps
T176 /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.2319175514 Aug 07 08:17:13 PM PDT 24 Aug 07 08:29:38 PM PDT 24 5167328104 ps
T149 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2513332070 Aug 07 07:53:35 PM PDT 24 Aug 07 07:59:47 PM PDT 24 3017152967 ps
T414 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.276241947 Aug 07 08:18:29 PM PDT 24 Aug 07 08:26:39 PM PDT 24 5132426290 ps
T440 /workspace/coverage/default/1.rom_volatile_raw_unlock.4259246080 Aug 07 08:08:02 PM PDT 24 Aug 07 08:09:54 PM PDT 24 2074321357 ps
T239 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.3244109443 Aug 07 07:57:40 PM PDT 24 Aug 07 09:27:35 PM PDT 24 50412976488 ps
T441 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3587261928 Aug 07 07:58:31 PM PDT 24 Aug 07 08:49:52 PM PDT 24 10756871005 ps
T442 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3386465049 Aug 07 08:28:34 PM PDT 24 Aug 07 08:34:15 PM PDT 24 3901916662 ps
T325 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1603939528 Aug 07 07:52:02 PM PDT 24 Aug 07 08:06:20 PM PDT 24 5591573034 ps
T443 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.3768496303 Aug 07 07:58:11 PM PDT 24 Aug 07 08:03:17 PM PDT 24 3579350517 ps
T444 /workspace/coverage/default/0.rom_e2e_static_critical.3904983867 Aug 07 08:00:36 PM PDT 24 Aug 07 09:20:05 PM PDT 24 17091441784 ps
T340 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.1528631117 Aug 07 08:09:19 PM PDT 24 Aug 07 08:22:33 PM PDT 24 4800817756 ps
T445 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.893267902 Aug 07 08:17:40 PM PDT 24 Aug 07 08:36:19 PM PDT 24 5782686200 ps
T1077 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.986769892 Aug 07 08:13:22 PM PDT 24 Aug 07 11:41:42 PM PDT 24 255055842936 ps
T366 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2735019470 Aug 07 07:55:37 PM PDT 24 Aug 07 08:05:44 PM PDT 24 19091780404 ps
T344 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1668308740 Aug 07 07:52:48 PM PDT 24 Aug 07 08:01:55 PM PDT 24 3411134122 ps
T801 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1718615570 Aug 07 08:32:38 PM PDT 24 Aug 07 08:38:41 PM PDT 24 3515415168 ps
T1078 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1248230570 Aug 07 07:51:35 PM PDT 24 Aug 07 09:30:55 PM PDT 24 27996664092 ps
T336 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1372807648 Aug 07 07:56:30 PM PDT 24 Aug 07 08:13:36 PM PDT 24 5265060488 ps
T1079 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.955265696 Aug 07 07:52:54 PM PDT 24 Aug 07 08:02:59 PM PDT 24 4122387760 ps
T1080 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.189024197 Aug 07 08:13:46 PM PDT 24 Aug 07 08:29:49 PM PDT 24 5030034956 ps
T283 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2824973045 Aug 07 08:05:20 PM PDT 24 Aug 07 08:15:45 PM PDT 24 3948593650 ps
T842 /workspace/coverage/default/59.chip_sw_all_escalation_resets.185193126 Aug 07 08:28:09 PM PDT 24 Aug 07 08:39:26 PM PDT 24 5324805660 ps
T1081 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3130599723 Aug 07 08:05:04 PM PDT 24 Aug 07 08:15:19 PM PDT 24 3739258054 ps
T1082 /workspace/coverage/default/2.chip_sw_kmac_entropy.1742477578 Aug 07 08:10:05 PM PDT 24 Aug 07 08:14:24 PM PDT 24 2893016660 ps
T1083 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.272865703 Aug 07 07:52:22 PM PDT 24 Aug 07 08:23:02 PM PDT 24 8629577796 ps
T1084 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.908702455 Aug 07 08:15:31 PM PDT 24 Aug 07 08:22:03 PM PDT 24 4253092804 ps
T328 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2304389054 Aug 07 08:01:22 PM PDT 24 Aug 07 08:31:01 PM PDT 24 12101864920 ps
T1085 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.1396155798 Aug 07 07:58:29 PM PDT 24 Aug 07 08:07:07 PM PDT 24 3589273568 ps
T1086 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2972641027 Aug 07 08:08:07 PM PDT 24 Aug 07 08:12:15 PM PDT 24 2962838000 ps
T1087 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1423835449 Aug 07 07:53:55 PM PDT 24 Aug 07 08:00:26 PM PDT 24 3312176200 ps
T1088 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.755949740 Aug 07 07:56:23 PM PDT 24 Aug 07 08:02:25 PM PDT 24 6587388580 ps
T1089 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1404562129 Aug 07 08:13:55 PM PDT 24 Aug 07 08:19:27 PM PDT 24 3097757116 ps
T839 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.4098775560 Aug 07 08:24:19 PM PDT 24 Aug 07 08:32:01 PM PDT 24 3863012312 ps
T1090 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2844236697 Aug 07 08:18:32 PM PDT 24 Aug 07 08:23:56 PM PDT 24 3760419316 ps
T1091 /workspace/coverage/default/0.chip_sw_aes_smoketest.1575359491 Aug 07 07:56:14 PM PDT 24 Aug 07 08:00:14 PM PDT 24 3327433752 ps
T1092 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3938978245 Aug 07 08:15:26 PM PDT 24 Aug 07 08:26:34 PM PDT 24 7719610536 ps
T54 /workspace/coverage/default/1.chip_jtag_csr_rw.3956764712 Aug 07 07:58:28 PM PDT 24 Aug 07 08:36:30 PM PDT 24 16955666710 ps
T1093 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.2492622679 Aug 07 08:20:33 PM PDT 24 Aug 07 08:27:07 PM PDT 24 5226038968 ps
T1094 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.257960698 Aug 07 07:53:33 PM PDT 24 Aug 07 08:07:36 PM PDT 24 4838401472 ps
T1095 /workspace/coverage/default/0.chip_sw_kmac_smoketest.1536097294 Aug 07 07:56:18 PM PDT 24 Aug 07 08:01:32 PM PDT 24 2570806000 ps
T1096 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2750221841 Aug 07 08:11:52 PM PDT 24 Aug 07 08:22:53 PM PDT 24 4798607360 ps
T266 /workspace/coverage/default/1.chip_sw_all_escalation_resets.3576143494 Aug 07 07:56:03 PM PDT 24 Aug 07 08:08:43 PM PDT 24 6163044000 ps
T554 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.849289418 Aug 07 08:02:16 PM PDT 24 Aug 07 08:15:25 PM PDT 24 4849139870 ps
T1097 /workspace/coverage/default/1.rom_e2e_asm_init_prod.1904232917 Aug 07 08:11:33 PM PDT 24 Aug 07 09:18:01 PM PDT 24 15194453986 ps
T1098 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2924161835 Aug 07 07:52:40 PM PDT 24 Aug 07 08:30:17 PM PDT 24 23169231428 ps
T794 /workspace/coverage/default/15.chip_sw_all_escalation_resets.956014955 Aug 07 08:23:39 PM PDT 24 Aug 07 08:36:01 PM PDT 24 6462829936 ps
T1099 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2420311264 Aug 07 08:18:11 PM PDT 24 Aug 07 08:22:53 PM PDT 24 2286545537 ps
T1100 /workspace/coverage/default/1.chip_sw_gpio_smoketest.2800707369 Aug 07 08:08:18 PM PDT 24 Aug 07 08:12:51 PM PDT 24 2419841391 ps
T371 /workspace/coverage/default/2.chip_sw_aon_timer_irq.1454540098 Aug 07 08:12:14 PM PDT 24 Aug 07 08:19:25 PM PDT 24 3663286972 ps
T1101 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.3895215608 Aug 07 08:16:59 PM PDT 24 Aug 07 08:24:14 PM PDT 24 5744137000 ps
T1102 /workspace/coverage/default/98.chip_sw_all_escalation_resets.685482017 Aug 07 08:31:50 PM PDT 24 Aug 07 08:43:15 PM PDT 24 5399993104 ps
T1103 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.2505653833 Aug 07 08:02:58 PM PDT 24 Aug 07 08:15:06 PM PDT 24 5740939808 ps
T722 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2676838482 Aug 07 07:51:06 PM PDT 24 Aug 07 07:53:22 PM PDT 24 2030331661 ps
T1104 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3557801273 Aug 07 07:51:47 PM PDT 24 Aug 07 08:00:22 PM PDT 24 4158939200 ps
T1105 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.469667684 Aug 07 07:51:53 PM PDT 24 Aug 07 08:04:35 PM PDT 24 4087700088 ps
T1106 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.20508687 Aug 07 08:12:27 PM PDT 24 Aug 07 08:18:04 PM PDT 24 4511315848 ps
T1107 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.2342041959 Aug 07 08:12:56 PM PDT 24 Aug 07 08:20:25 PM PDT 24 3471549230 ps
T856 /workspace/coverage/default/4.chip_sw_all_escalation_resets.2694674338 Aug 07 08:20:37 PM PDT 24 Aug 07 08:31:28 PM PDT 24 5599372306 ps
T1108 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.529546108 Aug 07 07:51:32 PM PDT 24 Aug 07 08:54:29 PM PDT 24 19934321936 ps
T1109 /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.714501184 Aug 07 08:22:35 PM PDT 24 Aug 07 08:59:02 PM PDT 24 9256479910 ps
T853 /workspace/coverage/default/66.chip_sw_all_escalation_resets.4178539396 Aug 07 08:28:48 PM PDT 24 Aug 07 08:39:02 PM PDT 24 4846796936 ps
T107 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3508004272 Aug 07 08:06:13 PM PDT 24 Aug 07 08:32:44 PM PDT 24 19727065296 ps
T1110 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3289177735 Aug 07 07:58:31 PM PDT 24 Aug 07 08:47:09 PM PDT 24 11454561978 ps
T1111 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1851136811 Aug 07 08:03:44 PM PDT 24 Aug 07 08:08:15 PM PDT 24 2178926996 ps
T1112 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.125813319 Aug 07 07:51:50 PM PDT 24 Aug 07 08:01:11 PM PDT 24 4015176468 ps
T60 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.3186845113 Aug 07 08:08:26 PM PDT 24 Aug 07 08:12:20 PM PDT 24 2790236802 ps
T784 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.4106566584 Aug 07 08:24:59 PM PDT 24 Aug 07 08:33:44 PM PDT 24 3116943596 ps
T796 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.4247504150 Aug 07 08:24:18 PM PDT 24 Aug 07 08:30:11 PM PDT 24 4045094800 ps
T1113 /workspace/coverage/default/2.rom_e2e_shutdown_output.2432099254 Aug 07 08:24:14 PM PDT 24 Aug 07 09:32:06 PM PDT 24 26639895825 ps
T782 /workspace/coverage/default/80.chip_sw_all_escalation_resets.398655837 Aug 07 08:30:04 PM PDT 24 Aug 07 08:41:40 PM PDT 24 5889778200 ps
T1114 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.1397626308 Aug 07 07:56:16 PM PDT 24 Aug 07 08:01:42 PM PDT 24 3596203560 ps
T1115 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4268337553 Aug 07 08:13:59 PM PDT 24 Aug 07 08:27:15 PM PDT 24 18935055804 ps
T1116 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3669900594 Aug 07 08:12:18 PM PDT 24 Aug 07 08:18:57 PM PDT 24 7702150162 ps
T1117 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1557447476 Aug 07 07:56:12 PM PDT 24 Aug 07 08:00:14 PM PDT 24 2990636430 ps
T1118 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.3873419300 Aug 07 07:52:25 PM PDT 24 Aug 07 07:55:12 PM PDT 24 2274119135 ps
T321 /workspace/coverage/default/0.chip_plic_all_irqs_0.1796495661 Aug 07 07:53:51 PM PDT 24 Aug 07 08:14:57 PM PDT 24 6313884380 ps
T137 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2481903961 Aug 07 08:05:52 PM PDT 24 Aug 07 08:14:38 PM PDT 24 5383254256 ps
T1119 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.2011656156 Aug 07 07:51:57 PM PDT 24 Aug 07 07:58:28 PM PDT 24 3342404440 ps
T1120 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2477019416 Aug 07 08:24:12 PM PDT 24 Aug 07 08:32:56 PM PDT 24 3632700734 ps
T1121 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.98484108 Aug 07 08:00:47 PM PDT 24 Aug 07 08:04:17 PM PDT 24 2731835640 ps
T114 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.4099091130 Aug 07 07:54:14 PM PDT 24 Aug 07 08:00:27 PM PDT 24 4594549000 ps
T446 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2131080437 Aug 07 07:52:40 PM PDT 24 Aug 07 08:03:13 PM PDT 24 9268481832 ps
T447 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.203094569 Aug 07 07:59:01 PM PDT 24 Aug 07 08:15:18 PM PDT 24 5627479822 ps
T448 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1005295075 Aug 07 08:15:41 PM PDT 24 Aug 07 08:26:40 PM PDT 24 5366251268 ps
T449 /workspace/coverage/default/3.chip_tap_straps_rma.3106657793 Aug 07 08:20:51 PM PDT 24 Aug 07 08:23:32 PM PDT 24 2702286725 ps
T450 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.971882340 Aug 07 08:23:38 PM PDT 24 Aug 07 08:32:32 PM PDT 24 5528963025 ps
T451 /workspace/coverage/default/90.chip_sw_all_escalation_resets.3711080636 Aug 07 08:31:02 PM PDT 24 Aug 07 08:43:46 PM PDT 24 6341630000 ps
T452 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1657108322 Aug 07 08:23:36 PM PDT 24 Aug 07 08:32:42 PM PDT 24 3916537940 ps
T453 /workspace/coverage/default/1.chip_sw_example_concurrency.3853868971 Aug 07 07:56:48 PM PDT 24 Aug 07 08:00:31 PM PDT 24 2730906540 ps
T454 /workspace/coverage/default/79.chip_sw_all_escalation_resets.2140596107 Aug 07 08:30:59 PM PDT 24 Aug 07 08:42:11 PM PDT 24 5487088148 ps
T267 /workspace/coverage/default/26.chip_sw_all_escalation_resets.798354282 Aug 07 08:27:12 PM PDT 24 Aug 07 08:37:19 PM PDT 24 4638870376 ps
T1122 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.4015995426 Aug 07 07:51:05 PM PDT 24 Aug 07 08:15:40 PM PDT 24 7622647338 ps
T341 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.1085201990 Aug 07 07:58:42 PM PDT 24 Aug 07 08:13:47 PM PDT 24 4724856360 ps
T1123 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1235874411 Aug 07 08:01:06 PM PDT 24 Aug 07 08:23:02 PM PDT 24 9071956261 ps
T717 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.343123047 Aug 07 08:17:00 PM PDT 24 Aug 07 08:25:03 PM PDT 24 4666834105 ps
T61 /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.2741308536 Aug 07 07:52:05 PM PDT 24 Aug 07 07:56:51 PM PDT 24 3877649944 ps
T758 /workspace/coverage/default/0.rom_raw_unlock.487385071 Aug 07 07:54:10 PM PDT 24 Aug 07 07:58:14 PM PDT 24 5710720768 ps
T707 /workspace/coverage/default/2.chip_sw_edn_boot_mode.3504870636 Aug 07 08:13:20 PM PDT 24 Aug 07 08:24:39 PM PDT 24 3509986800 ps
T377 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3154402642 Aug 07 08:24:25 PM PDT 24 Aug 07 08:34:59 PM PDT 24 3847587334 ps
T358 /workspace/coverage/default/1.chip_sw_pattgen_ios.352129668 Aug 07 07:58:11 PM PDT 24 Aug 07 08:02:54 PM PDT 24 3011910270 ps
T389 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1162929125 Aug 07 08:02:03 PM PDT 24 Aug 07 09:42:13 PM PDT 24 24209368676 ps
T390 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.328057488 Aug 07 08:01:51 PM PDT 24 Aug 07 08:22:04 PM PDT 24 7769387410 ps
T93 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2520840780 Aug 07 08:26:25 PM PDT 24 Aug 07 08:32:06 PM PDT 24 3275724872 ps
T391 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1381984501 Aug 07 08:01:50 PM PDT 24 Aug 07 09:17:06 PM PDT 24 14391248816 ps
T392 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.730566916 Aug 07 08:16:13 PM PDT 24 Aug 07 08:31:05 PM PDT 24 5346451808 ps
T393 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3252358042 Aug 07 08:26:03 PM PDT 24 Aug 07 08:33:19 PM PDT 24 4113716924 ps
T268 /workspace/coverage/default/71.chip_sw_all_escalation_resets.3150589624 Aug 07 08:31:06 PM PDT 24 Aug 07 08:40:49 PM PDT 24 6546505112 ps
T394 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.1236371691 Aug 07 08:22:47 PM PDT 24 Aug 07 09:05:42 PM PDT 24 13173345888 ps
T1124 /workspace/coverage/default/2.chip_sw_kmac_app_rom.733856357 Aug 07 08:14:17 PM PDT 24 Aug 07 08:18:45 PM PDT 24 2930323860 ps
T1125 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1961476698 Aug 07 07:52:20 PM PDT 24 Aug 07 08:12:08 PM PDT 24 6933616705 ps
T1126 /workspace/coverage/default/2.chip_sw_power_idle_load.3112040732 Aug 07 08:19:19 PM PDT 24 Aug 07 08:33:08 PM PDT 24 4442053208 ps
T1127 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2915646116 Aug 07 08:06:17 PM PDT 24 Aug 07 08:11:04 PM PDT 24 3605553222 ps
T1128 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3048508400 Aug 07 08:24:44 PM PDT 24 Aug 07 09:28:24 PM PDT 24 14559703340 ps
T1129 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3747193720 Aug 07 08:07:26 PM PDT 24 Aug 07 08:26:40 PM PDT 24 5736130480 ps
T1130 /workspace/coverage/default/64.chip_sw_all_escalation_resets.1578762893 Aug 07 08:28:11 PM PDT 24 Aug 07 08:36:46 PM PDT 24 5666177138 ps
T847 /workspace/coverage/default/2.chip_sw_all_escalation_resets.686358333 Aug 07 08:09:18 PM PDT 24 Aug 07 08:23:23 PM PDT 24 5677405704 ps
T850 /workspace/coverage/default/88.chip_sw_all_escalation_resets.1000287413 Aug 07 08:30:48 PM PDT 24 Aug 07 08:41:24 PM PDT 24 6555603532 ps
T1131 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.854906630 Aug 07 08:18:10 PM PDT 24 Aug 07 08:36:52 PM PDT 24 5557405716 ps
T1132 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2831615083 Aug 07 07:52:37 PM PDT 24 Aug 07 08:02:22 PM PDT 24 3630161572 ps
T330 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.102731198 Aug 07 08:14:43 PM PDT 24 Aug 07 08:37:23 PM PDT 24 6006914728 ps
T1133 /workspace/coverage/default/0.chip_tap_straps_prod.3315455456 Aug 07 07:52:06 PM PDT 24 Aug 07 08:02:53 PM PDT 24 7935983663 ps
T1134 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.792043134 Aug 07 08:10:49 PM PDT 24 Aug 07 08:18:57 PM PDT 24 8212372622 ps
T221 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.1321666203 Aug 07 07:51:55 PM PDT 24 Aug 07 11:40:06 PM PDT 24 66122314194 ps
T1135 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.3158961656 Aug 07 08:23:39 PM PDT 24 Aug 07 08:31:35 PM PDT 24 4006072632 ps
T116 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.2262049268 Aug 07 07:58:52 PM PDT 24 Aug 07 08:02:43 PM PDT 24 2947423260 ps
T432 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3215385991 Aug 07 08:18:26 PM PDT 24 Aug 07 08:36:12 PM PDT 24 7437256999 ps
T433 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.630800877 Aug 07 08:06:18 PM PDT 24 Aug 07 08:15:45 PM PDT 24 5032641895 ps
T434 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.2109091059 Aug 07 07:52:44 PM PDT 24 Aug 07 07:57:46 PM PDT 24 2799246052 ps
T435 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.1375083911 Aug 07 07:56:01 PM PDT 24 Aug 07 08:01:23 PM PDT 24 2478357000 ps
T436 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.887720367 Aug 07 07:51:36 PM PDT 24 Aug 07 09:02:17 PM PDT 24 15940729052 ps
T334 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1666121017 Aug 07 07:53:48 PM PDT 24 Aug 07 08:11:29 PM PDT 24 5276274464 ps
T437 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.4077402171 Aug 07 07:53:48 PM PDT 24 Aug 07 08:15:26 PM PDT 24 7022150194 ps
T438 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2650751345 Aug 07 08:13:18 PM PDT 24 Aug 07 08:37:22 PM PDT 24 7945757150 ps
T439 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.4043010356 Aug 07 07:52:25 PM PDT 24 Aug 07 11:50:56 PM PDT 24 77892943746 ps
T1136 /workspace/coverage/default/1.chip_sw_example_rom.2367640887 Aug 07 07:59:31 PM PDT 24 Aug 07 08:01:37 PM PDT 24 2008726264 ps
T1137 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.986562990 Aug 07 08:23:39 PM PDT 24 Aug 07 08:31:57 PM PDT 24 7114080347 ps
T1138 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.4040263471 Aug 07 08:15:19 PM PDT 24 Aug 07 08:24:03 PM PDT 24 5111271224 ps
T1139 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1114884157 Aug 07 08:11:12 PM PDT 24 Aug 07 08:48:50 PM PDT 24 20665234359 ps
T1140 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2417496999 Aug 07 07:52:01 PM PDT 24 Aug 07 08:16:30 PM PDT 24 9657553704 ps
T1141 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.1476853334 Aug 07 08:02:58 PM PDT 24 Aug 07 09:12:59 PM PDT 24 15102818776 ps
T160 /workspace/coverage/default/1.chip_plic_all_irqs_10.2945360113 Aug 07 08:05:03 PM PDT 24 Aug 07 08:13:56 PM PDT 24 3756620702 ps
T818 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1163691510 Aug 07 08:24:04 PM PDT 24 Aug 07 08:31:19 PM PDT 24 4029537980 ps
T1142 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1272503914 Aug 07 08:10:16 PM PDT 24 Aug 07 08:40:53 PM PDT 24 9330521654 ps
T251 /workspace/coverage/default/69.chip_sw_all_escalation_resets.2190392640 Aug 07 08:30:39 PM PDT 24 Aug 07 08:39:32 PM PDT 24 5256309030 ps
T1143 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2210400709 Aug 07 08:12:48 PM PDT 24 Aug 07 09:13:38 PM PDT 24 14869196532 ps
T1144 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1113979750 Aug 07 08:09:11 PM PDT 24 Aug 07 08:13:26 PM PDT 24 2909952520 ps
T1145 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1284144628 Aug 07 08:11:46 PM PDT 24 Aug 07 08:21:19 PM PDT 24 6186211474 ps
T1146 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3449559370 Aug 07 08:04:51 PM PDT 24 Aug 07 08:14:00 PM PDT 24 5010375456 ps
T1147 /workspace/coverage/default/56.chip_sw_all_escalation_resets.1149119758 Aug 07 08:30:48 PM PDT 24 Aug 07 08:39:38 PM PDT 24 5056840740 ps
T1148 /workspace/coverage/default/1.chip_sw_flash_crash_alert.2515248939 Aug 07 08:06:00 PM PDT 24 Aug 07 08:14:40 PM PDT 24 5057179800 ps
T1149 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.49393088 Aug 07 08:11:10 PM PDT 24 Aug 07 08:30:17 PM PDT 24 9203409672 ps
T1150 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.3566226167 Aug 07 08:06:04 PM PDT 24 Aug 07 08:11:03 PM PDT 24 2520815023 ps
T1151 /workspace/coverage/default/0.rom_keymgr_functest.980284911 Aug 07 07:55:05 PM PDT 24 Aug 07 08:05:09 PM PDT 24 5197242980 ps
T1152 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.2705944621 Aug 07 07:52:16 PM PDT 24 Aug 07 07:57:17 PM PDT 24 2822550852 ps
T191 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.423333837 Aug 07 08:06:48 PM PDT 24 Aug 07 08:12:48 PM PDT 24 3026564080 ps
T1153 /workspace/coverage/default/1.chip_sw_kmac_app_rom.609893233 Aug 07 08:04:21 PM PDT 24 Aug 07 08:07:05 PM PDT 24 2270147400 ps
T1154 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.4207510551 Aug 07 08:21:13 PM PDT 24 Aug 07 08:41:51 PM PDT 24 13282757445 ps
T1155 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.443628274 Aug 07 08:02:36 PM PDT 24 Aug 07 08:14:34 PM PDT 24 7644849482 ps
T141 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3979737138 Aug 07 08:20:58 PM PDT 24 Aug 07 08:37:22 PM PDT 24 7113567198 ps
T1156 /workspace/coverage/default/0.chip_sw_usbdev_vbus.643740797 Aug 07 07:50:33 PM PDT 24 Aug 07 07:53:40 PM PDT 24 3245331992 ps
T252 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1475914502 Aug 07 08:25:32 PM PDT 24 Aug 07 08:33:14 PM PDT 24 3208154784 ps
T1157 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.2583326394 Aug 07 08:17:58 PM PDT 24 Aug 07 08:23:10 PM PDT 24 2573935766 ps
T415 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2042794526 Aug 07 08:16:45 PM PDT 24 Aug 07 08:39:58 PM PDT 24 23477328528 ps
T1158 /workspace/coverage/default/2.chip_sw_flash_crash_alert.1628279110 Aug 07 08:17:31 PM PDT 24 Aug 07 08:29:06 PM PDT 24 4984969810 ps
T1159 /workspace/coverage/default/1.chip_sw_aes_enc.3180624866 Aug 07 08:01:50 PM PDT 24 Aug 07 08:07:54 PM PDT 24 2747307672 ps
T1160 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.189263522 Aug 07 08:01:33 PM PDT 24 Aug 07 08:07:58 PM PDT 24 6237562440 ps
T1161 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.661587734 Aug 07 07:54:27 PM PDT 24 Aug 07 07:58:43 PM PDT 24 2707896260 ps
T1162 /workspace/coverage/default/2.chip_sw_example_rom.307793953 Aug 07 08:08:23 PM PDT 24 Aug 07 08:10:21 PM PDT 24 2297942900 ps
T94 /workspace/coverage/default/21.chip_sw_all_escalation_resets.3952548961 Aug 07 08:25:13 PM PDT 24 Aug 07 08:35:04 PM PDT 24 5261017154 ps
T1163 /workspace/coverage/default/3.chip_tap_straps_prod.415248867 Aug 07 08:21:48 PM PDT 24 Aug 07 08:24:52 PM PDT 24 2307166869 ps
T1164 /workspace/coverage/default/2.chip_sw_plic_sw_irq.3700254487 Aug 07 08:15:23 PM PDT 24 Aug 07 08:21:43 PM PDT 24 3674606492 ps
T372 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1442301285 Aug 07 08:06:08 PM PDT 24 Aug 07 08:10:26 PM PDT 24 3632417813 ps
T117 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.815633984 Aug 07 07:51:01 PM PDT 24 Aug 07 07:55:31 PM PDT 24 3255865054 ps
T1165 /workspace/coverage/default/0.chip_sw_hmac_smoketest.3036528485 Aug 07 07:56:44 PM PDT 24 Aug 07 08:04:55 PM PDT 24 3122862592 ps
T1166 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.3987055713 Aug 07 08:22:10 PM PDT 24 Aug 07 08:28:53 PM PDT 24 3157541750 ps
T1167 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1227619947 Aug 07 08:15:48 PM PDT 24 Aug 07 08:27:14 PM PDT 24 4302177126 ps
T1168 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3044351923 Aug 07 08:06:49 PM PDT 24 Aug 07 08:18:39 PM PDT 24 4831378840 ps
T1169 /workspace/coverage/default/34.chip_sw_all_escalation_resets.929788888 Aug 07 08:24:58 PM PDT 24 Aug 07 08:37:26 PM PDT 24 4683988344 ps
T318 /workspace/coverage/default/1.chip_plic_all_irqs_0.1728635932 Aug 07 08:04:42 PM PDT 24 Aug 07 08:25:31 PM PDT 24 6217248976 ps
T138 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2727947445 Aug 07 08:16:30 PM PDT 24 Aug 07 08:25:22 PM PDT 24 5492133210 ps
T375 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.2484775688 Aug 07 08:09:26 PM PDT 24 Aug 07 11:46:41 PM PDT 24 64684118590 ps
T1170 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.768050467 Aug 07 08:02:24 PM PDT 24 Aug 07 08:24:22 PM PDT 24 6996564096 ps
T1171 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2924203761 Aug 07 08:05:35 PM PDT 24 Aug 07 08:39:00 PM PDT 24 9633760164 ps
T1172 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1163497224 Aug 07 08:22:36 PM PDT 24 Aug 07 08:27:51 PM PDT 24 7299222160 ps
T1173 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.1375637036 Aug 07 08:08:24 PM PDT 24 Aug 07 08:12:18 PM PDT 24 3187037192 ps
T1174 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.1967598460 Aug 07 08:24:54 PM PDT 24 Aug 07 09:27:16 PM PDT 24 14835660727 ps
T1175 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.187758738 Aug 07 08:21:55 PM PDT 24 Aug 07 08:31:31 PM PDT 24 4385158790 ps
T723 /workspace/coverage/default/84.chip_sw_all_escalation_resets.833390139 Aug 07 08:30:07 PM PDT 24 Aug 07 08:38:07 PM PDT 24 4705231392 ps
T777 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1444720240 Aug 07 08:31:03 PM PDT 24 Aug 07 08:39:01 PM PDT 24 3688597382 ps
T1176 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3783665152 Aug 07 07:52:53 PM PDT 24 Aug 07 08:07:48 PM PDT 24 10155309608 ps
T1177 /workspace/coverage/default/0.rom_e2e_self_hash.3960114632 Aug 07 07:59:14 PM PDT 24 Aug 07 09:47:53 PM PDT 24 25546913344 ps
T1178 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2733164273 Aug 07 07:53:06 PM PDT 24 Aug 07 08:37:20 PM PDT 24 29528000936 ps
T273 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.3778101343 Aug 07 07:59:28 PM PDT 24 Aug 07 08:12:23 PM PDT 24 4744615426 ps
T274 /workspace/coverage/default/2.rom_e2e_asm_init_dev.2046894936 Aug 07 08:22:31 PM PDT 24 Aug 07 09:17:07 PM PDT 24 15655621026 ps
T142 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3637914602 Aug 07 08:06:00 PM PDT 24 Aug 07 08:15:50 PM PDT 24 4786634528 ps
T241 /workspace/coverage/default/1.chip_sw_flash_init.3487617505 Aug 07 07:58:28 PM PDT 24 Aug 07 08:28:47 PM PDT 24 16544419260 ps
T122 /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.398204928 Aug 07 08:07:30 PM PDT 24 Aug 07 09:15:40 PM PDT 24 22766072117 ps
T71 /workspace/coverage/default/1.chip_tap_straps_rma.2450165662 Aug 07 08:07:13 PM PDT 24 Aug 07 08:22:09 PM PDT 24 8909646651 ps
T275 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2813916216 Aug 07 08:32:03 PM PDT 24 Aug 07 08:37:56 PM PDT 24 3259033920 ps
T276 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.4286069728 Aug 07 07:53:58 PM PDT 24 Aug 07 08:33:01 PM PDT 24 11086598682 ps
T277 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2353232033 Aug 07 08:21:19 PM PDT 24 Aug 07 08:33:59 PM PDT 24 4754729306 ps
T278 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3852544033 Aug 07 08:18:50 PM PDT 24 Aug 07 09:12:04 PM PDT 24 16916100733 ps
T1179 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.92288594 Aug 07 08:04:10 PM PDT 24 Aug 07 08:09:51 PM PDT 24 3241731188 ps
T260 /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.96408720 Aug 07 07:55:13 PM PDT 24 Aug 07 08:38:38 PM PDT 24 11711150122 ps
T345 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1638058765 Aug 07 08:18:11 PM PDT 24 Aug 07 08:32:50 PM PDT 24 4648340028 ps
T802 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2310038704 Aug 07 08:24:20 PM PDT 24 Aug 07 08:30:19 PM PDT 24 3550384554 ps
T1180 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.239755056 Aug 07 08:03:59 PM PDT 24 Aug 07 08:27:40 PM PDT 24 6623636305 ps
T1181 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.4283429889 Aug 07 08:01:01 PM PDT 24 Aug 07 09:11:51 PM PDT 24 16025800242 ps
T1182 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3108419256 Aug 07 08:01:30 PM PDT 24 Aug 07 09:12:23 PM PDT 24 14592884310 ps
T287 /workspace/coverage/default/44.chip_sw_all_escalation_resets.3721819382 Aug 07 08:26:51 PM PDT 24 Aug 07 08:37:55 PM PDT 24 5294546664 ps
T385 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.283093641 Aug 07 08:16:43 PM PDT 24 Aug 07 08:26:21 PM PDT 24 5181498960 ps
T747 /workspace/coverage/default/1.chip_sw_power_sleep_load.875866742 Aug 07 08:07:02 PM PDT 24 Aug 07 08:12:46 PM PDT 24 4471935716 ps
T1183 /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.1205662497 Aug 07 07:56:31 PM PDT 24 Aug 07 08:53:12 PM PDT 24 22657936399 ps
T72 /workspace/coverage/default/4.chip_tap_straps_rma.4032391546 Aug 07 08:21:07 PM PDT 24 Aug 07 08:24:19 PM PDT 24 2500493581 ps
T77 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.1399166720 Aug 07 07:52:01 PM PDT 24 Aug 07 09:58:42 PM PDT 24 31639919752 ps
T770 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1697230995 Aug 07 08:26:29 PM PDT 24 Aug 07 08:34:57 PM PDT 24 3613598550 ps
T1184 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2014271380 Aug 07 08:22:32 PM PDT 24 Aug 07 08:26:12 PM PDT 24 2483130580 ps
T62 /workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.1086776166 Aug 07 08:18:11 PM PDT 24 Aug 07 08:24:51 PM PDT 24 3568789020 ps
T41 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.328283485 Aug 07 08:01:28 PM PDT 24 Aug 07 08:08:43 PM PDT 24 6272786288 ps
T1185 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.1758396229 Aug 07 08:02:25 PM PDT 24 Aug 07 08:36:21 PM PDT 24 9484273300 ps
T797 /workspace/coverage/default/65.chip_sw_all_escalation_resets.913584378 Aug 07 08:30:36 PM PDT 24 Aug 07 08:43:07 PM PDT 24 4778807446 ps
T1186 /workspace/coverage/default/76.chip_sw_all_escalation_resets.1674913473 Aug 07 08:30:19 PM PDT 24 Aug 07 08:41:42 PM PDT 24 5474585890 ps
T1187 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.3250462089 Aug 07 07:54:03 PM PDT 24 Aug 07 07:59:05 PM PDT 24 3407850132 ps
T851 /workspace/coverage/default/13.chip_sw_all_escalation_resets.1712799597 Aug 07 08:23:01 PM PDT 24 Aug 07 08:34:00 PM PDT 24 5748156976 ps
T1188 /workspace/coverage/default/0.chip_sw_otbn_smoketest.2419445364 Aug 07 07:54:58 PM PDT 24 Aug 07 08:36:41 PM PDT 24 10050724658 ps
T1189 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.4259082286 Aug 07 08:13:37 PM PDT 24 Aug 07 08:18:52 PM PDT 24 3009563924 ps
T413 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.4080057013 Aug 07 08:15:36 PM PDT 24 Aug 07 08:23:41 PM PDT 24 9019373596 ps
T269 /workspace/coverage/default/18.chip_sw_all_escalation_resets.189948303 Aug 07 08:24:32 PM PDT 24 Aug 07 08:33:18 PM PDT 24 3978608184 ps
T1190 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.2395805085 Aug 07 08:10:36 PM PDT 24 Aug 07 08:15:44 PM PDT 24 3180140056 ps
T1191 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3794558852 Aug 07 08:00:09 PM PDT 24 Aug 07 09:01:30 PM PDT 24 11387738312 ps
T1192 /workspace/coverage/default/1.chip_tap_straps_dev.380948023 Aug 07 08:04:57 PM PDT 24 Aug 07 08:09:50 PM PDT 24 3674757612 ps
T1193 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3888452437 Aug 07 07:54:51 PM PDT 24 Aug 07 08:05:01 PM PDT 24 3790866294 ps
T1194 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2501546981 Aug 07 07:59:25 PM PDT 24 Aug 07 08:23:41 PM PDT 24 15041737174 ps
T1195 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1182778229 Aug 07 07:52:01 PM PDT 24 Aug 07 07:57:18 PM PDT 24 2806155968 ps
T1196 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3135882808 Aug 07 07:58:43 PM PDT 24 Aug 07 09:08:35 PM PDT 24 15010924732 ps
T1197 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.2016889998 Aug 07 08:21:21 PM PDT 24 Aug 07 08:34:29 PM PDT 24 4971387548 ps
T1198 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.4078127533 Aug 07 07:52:00 PM PDT 24 Aug 07 07:57:59 PM PDT 24 3075232803 ps
T1199 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1569629 Aug 07 07:55:31 PM PDT 24 Aug 07 08:30:53 PM PDT 24 25063445465 ps
T1200 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1721252951 Aug 07 07:58:45 PM PDT 24 Aug 07 09:10:11 PM PDT 24 15334555014 ps
T161 /workspace/coverage/default/2.chip_plic_all_irqs_10.3444051864 Aug 07 08:14:37 PM PDT 24 Aug 07 08:24:05 PM PDT 24 3950467580 ps
T1201 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3122441936 Aug 07 08:00:59 PM PDT 24 Aug 07 08:11:54 PM PDT 24 5401537944 ps
T242 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.2507100414 Aug 07 08:09:58 PM PDT 24 Aug 07 08:19:27 PM PDT 24 4268818666 ps
T1202 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.723713129 Aug 07 08:13:53 PM PDT 24 Aug 07 08:49:05 PM PDT 24 10315715412 ps
T1203 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.1378862610 Aug 07 08:00:59 PM PDT 24 Aug 07 08:10:47 PM PDT 24 3858215300 ps
T1204 /workspace/coverage/default/2.chip_sw_example_flash.1005577611 Aug 07 08:08:45 PM PDT 24 Aug 07 08:12:21 PM PDT 24 2373938440 ps
T1205 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1749070007 Aug 07 08:16:24 PM PDT 24 Aug 07 08:25:33 PM PDT 24 3563931956 ps
T1206 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3340508502 Aug 07 08:25:13 PM PDT 24 Aug 07 09:51:20 PM PDT 24 20631673340 ps
T348 /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.452378550 Aug 07 08:17:16 PM PDT 24 Aug 07 08:25:12 PM PDT 24 4068140376 ps
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