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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.03 95.50 93.78 95.28 94.53 97.53 99.55


Total test records in report: 2934
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T1207 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.639764635 Aug 07 08:13:34 PM PDT 24 Aug 07 08:19:34 PM PDT 24 3592100380 ps
T831 /workspace/coverage/default/58.chip_sw_all_escalation_resets.1532906298 Aug 07 08:29:58 PM PDT 24 Aug 07 08:39:42 PM PDT 24 5422627782 ps
T1208 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1603218030 Aug 07 08:22:19 PM PDT 24 Aug 07 09:09:07 PM PDT 24 13293394000 ps
T342 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.2966270241 Aug 07 08:10:09 PM PDT 24 Aug 07 08:24:50 PM PDT 24 5054958600 ps
T195 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1390369357 Aug 07 07:58:58 PM PDT 24 Aug 07 09:30:37 PM PDT 24 43627533854 ps
T779 /workspace/coverage/default/70.chip_sw_all_escalation_resets.3514036844 Aug 07 08:28:46 PM PDT 24 Aug 07 08:37:45 PM PDT 24 4946741862 ps
T1209 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3894897190 Aug 07 08:11:38 PM PDT 24 Aug 07 08:33:46 PM PDT 24 13276659961 ps
T95 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.729033506 Aug 07 08:28:42 PM PDT 24 Aug 07 08:35:28 PM PDT 24 3846539760 ps
T1210 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3034035373 Aug 07 08:10:28 PM PDT 24 Aug 07 08:16:07 PM PDT 24 4055138746 ps
T821 /workspace/coverage/default/62.chip_sw_all_escalation_resets.128540290 Aug 07 08:27:31 PM PDT 24 Aug 07 08:39:07 PM PDT 24 4541099186 ps
T1211 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.3858871799 Aug 07 08:14:07 PM PDT 24 Aug 07 08:48:54 PM PDT 24 9673364288 ps
T1212 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.153238369 Aug 07 08:11:59 PM PDT 24 Aug 07 08:21:50 PM PDT 24 7882544010 ps
T1213 /workspace/coverage/default/2.rom_keymgr_functest.1624480543 Aug 07 08:19:05 PM PDT 24 Aug 07 08:28:57 PM PDT 24 5439240940 ps
T1214 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1389598472 Aug 07 08:13:16 PM PDT 24 Aug 07 09:16:49 PM PDT 24 19132823505 ps
T63 /workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.2954563749 Aug 07 07:57:45 PM PDT 24 Aug 07 08:01:55 PM PDT 24 3596911941 ps
T815 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1656068353 Aug 07 08:20:48 PM PDT 24 Aug 07 08:27:48 PM PDT 24 3900043008 ps
T1215 /workspace/coverage/default/0.chip_sw_otbn_randomness.2181312960 Aug 07 07:52:36 PM PDT 24 Aug 07 08:08:13 PM PDT 24 6195743116 ps
T825 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.4028209609 Aug 07 08:21:50 PM PDT 24 Aug 07 08:31:56 PM PDT 24 3982830600 ps
T852 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.916204679 Aug 07 08:27:48 PM PDT 24 Aug 07 08:36:16 PM PDT 24 3681338444 ps
T205 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3580281196 Aug 07 08:10:15 PM PDT 24 Aug 07 08:20:09 PM PDT 24 5250939079 ps
T814 /workspace/coverage/default/87.chip_sw_all_escalation_resets.2955748237 Aug 07 08:30:10 PM PDT 24 Aug 07 08:42:37 PM PDT 24 6227738888 ps
T270 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2689466093 Aug 07 07:51:09 PM PDT 24 Aug 07 08:01:35 PM PDT 24 6905151752 ps
T774 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3720920042 Aug 07 08:28:47 PM PDT 24 Aug 07 08:36:15 PM PDT 24 3319296360 ps
T1216 /workspace/coverage/default/1.chip_sw_otbn_smoketest.2865206670 Aug 07 08:08:18 PM PDT 24 Aug 07 08:43:19 PM PDT 24 8238740408 ps
T1217 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1054724113 Aug 07 08:01:30 PM PDT 24 Aug 07 08:11:34 PM PDT 24 5067956064 ps
T1218 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1264719944 Aug 07 08:04:35 PM PDT 24 Aug 07 08:50:52 PM PDT 24 11368392330 ps
T836 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.4236366109 Aug 07 08:31:17 PM PDT 24 Aug 07 08:38:47 PM PDT 24 3544205802 ps
T177 /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.3701015559 Aug 07 07:55:00 PM PDT 24 Aug 07 08:04:41 PM PDT 24 4769733132 ps
T1219 /workspace/coverage/default/1.rom_e2e_smoke.3589627784 Aug 07 08:11:40 PM PDT 24 Aug 07 09:25:30 PM PDT 24 15132201292 ps
T1220 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.150471555 Aug 07 08:25:15 PM PDT 24 Aug 07 08:31:37 PM PDT 24 3491488480 ps
T1221 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1994488978 Aug 07 07:54:06 PM PDT 24 Aug 07 08:06:26 PM PDT 24 4863668464 ps
T1222 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.956680271 Aug 07 07:53:09 PM PDT 24 Aug 07 11:29:57 PM PDT 24 255819283148 ps
T1223 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.3171394412 Aug 07 07:56:41 PM PDT 24 Aug 07 11:19:11 PM PDT 24 65404934284 ps
T1224 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2849126400 Aug 07 07:55:13 PM PDT 24 Aug 07 08:05:25 PM PDT 24 3992812648 ps
T772 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.967690516 Aug 07 08:25:09 PM PDT 24 Aug 07 08:31:33 PM PDT 24 4441093368 ps
T206 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.1334240782 Aug 07 08:15:50 PM PDT 24 Aug 07 08:28:06 PM PDT 24 5728644662 ps
T1225 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.553912160 Aug 07 08:27:16 PM PDT 24 Aug 07 08:36:10 PM PDT 24 3638770140 ps
T166 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1441458485 Aug 07 08:10:14 PM PDT 24 Aug 07 08:14:01 PM PDT 24 2615119262 ps
T1226 /workspace/coverage/default/2.chip_tap_straps_rma.2802296260 Aug 07 08:17:07 PM PDT 24 Aug 07 08:25:58 PM PDT 24 5257761504 ps
T115 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.3654616691 Aug 07 08:06:17 PM PDT 24 Aug 07 08:16:01 PM PDT 24 4946221564 ps
T820 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2213049526 Aug 07 08:28:33 PM PDT 24 Aug 07 08:34:25 PM PDT 24 3291013792 ps
T1227 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3212742942 Aug 07 07:53:39 PM PDT 24 Aug 07 08:01:16 PM PDT 24 4497626068 ps
T1228 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.4112822189 Aug 07 08:18:59 PM PDT 24 Aug 07 08:28:40 PM PDT 24 3440669844 ps
T1229 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2528784914 Aug 07 08:10:45 PM PDT 24 Aug 07 08:15:03 PM PDT 24 3420579624 ps
T1230 /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2342116084 Aug 07 08:07:06 PM PDT 24 Aug 07 08:14:57 PM PDT 24 4852889240 ps
T1231 /workspace/coverage/default/1.rom_e2e_static_critical.3266574496 Aug 07 08:11:29 PM PDT 24 Aug 07 09:29:14 PM PDT 24 17023178476 ps
T349 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.1609957208 Aug 07 08:05:25 PM PDT 24 Aug 07 08:10:56 PM PDT 24 3557783088 ps
T1232 /workspace/coverage/default/1.chip_sw_hmac_enc.1811070214 Aug 07 08:03:45 PM PDT 24 Aug 07 08:08:51 PM PDT 24 2846716208 ps
T1233 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.466699597 Aug 07 08:22:33 PM PDT 24 Aug 07 08:36:22 PM PDT 24 4466461800 ps
T386 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.60262969 Aug 07 07:54:30 PM PDT 24 Aug 07 08:03:16 PM PDT 24 6674684360 ps
T1234 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3442013676 Aug 07 08:14:35 PM PDT 24 Aug 07 08:19:57 PM PDT 24 3814274331 ps
T351 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3667128182 Aug 07 07:55:26 PM PDT 24 Aug 07 08:05:16 PM PDT 24 4466859326 ps
T1235 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1874865971 Aug 07 08:01:40 PM PDT 24 Aug 07 09:12:59 PM PDT 24 19058888223 ps
T167 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1688430928 Aug 07 07:59:05 PM PDT 24 Aug 07 08:03:18 PM PDT 24 2899683735 ps
T748 /workspace/coverage/default/0.chip_sw_power_sleep_load.2205320946 Aug 07 07:54:44 PM PDT 24 Aug 07 08:00:04 PM PDT 24 4265081560 ps
T1236 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.757870195 Aug 07 08:21:47 PM PDT 24 Aug 07 09:28:59 PM PDT 24 16869191246 ps
T843 /workspace/coverage/default/12.chip_sw_all_escalation_resets.2467616547 Aug 07 08:23:44 PM PDT 24 Aug 07 08:36:45 PM PDT 24 5447695092 ps
T1237 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2363374892 Aug 07 08:11:33 PM PDT 24 Aug 07 08:19:57 PM PDT 24 7172846325 ps
T1238 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.985689517 Aug 07 07:59:30 PM PDT 24 Aug 07 08:04:53 PM PDT 24 3321768174 ps
T1239 /workspace/coverage/default/1.chip_sw_aes_idle.2011438466 Aug 07 08:02:25 PM PDT 24 Aug 07 08:06:49 PM PDT 24 2781306122 ps
T143 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.838245879 Aug 07 08:20:44 PM PDT 24 Aug 07 08:38:16 PM PDT 24 7743509250 ps
T1240 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.3581589575 Aug 07 07:58:33 PM PDT 24 Aug 07 09:46:56 PM PDT 24 23401467525 ps
T1241 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1530470916 Aug 07 07:58:58 PM PDT 24 Aug 07 08:05:06 PM PDT 24 3304290288 ps
T1242 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1931181512 Aug 07 07:51:54 PM PDT 24 Aug 07 08:09:49 PM PDT 24 8172099592 ps
T1243 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2997915695 Aug 07 07:57:43 PM PDT 24 Aug 07 07:59:26 PM PDT 24 2119228458 ps
T1244 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2226578996 Aug 07 08:21:42 PM PDT 24 Aug 07 08:34:53 PM PDT 24 4460665808 ps
T799 /workspace/coverage/default/0.chip_sw_all_escalation_resets.1278575790 Aug 07 07:54:06 PM PDT 24 Aug 07 08:03:17 PM PDT 24 5084724716 ps
T1245 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1832494212 Aug 07 07:54:27 PM PDT 24 Aug 07 08:03:18 PM PDT 24 7924772374 ps
T555 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1064791553 Aug 07 07:53:08 PM PDT 24 Aug 07 08:06:25 PM PDT 24 4943163334 ps
T1246 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2446385786 Aug 07 08:10:35 PM PDT 24 Aug 07 08:12:36 PM PDT 24 2664233604 ps
T805 /workspace/coverage/default/3.chip_sw_all_escalation_resets.2945737845 Aug 07 08:20:13 PM PDT 24 Aug 07 08:30:01 PM PDT 24 5364097496 ps
T826 /workspace/coverage/default/22.chip_sw_all_escalation_resets.3651625414 Aug 07 08:25:19 PM PDT 24 Aug 07 08:35:48 PM PDT 24 4918337050 ps
T795 /workspace/coverage/default/61.chip_sw_all_escalation_resets.178349750 Aug 07 08:28:26 PM PDT 24 Aug 07 08:38:09 PM PDT 24 5198178510 ps
T1247 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1916029281 Aug 07 07:56:56 PM PDT 24 Aug 07 08:08:14 PM PDT 24 4721225776 ps
T210 /workspace/coverage/default/0.chip_jtag_mem_access.1043727753 Aug 07 07:45:32 PM PDT 24 Aug 07 08:05:50 PM PDT 24 13591600560 ps
T1248 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.630233570 Aug 07 08:23:40 PM PDT 24 Aug 07 09:13:18 PM PDT 24 11926305203 ps
T1249 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.4032418500 Aug 07 08:06:10 PM PDT 24 Aug 07 08:21:52 PM PDT 24 7812749404 ps
T1250 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2054440244 Aug 07 07:59:25 PM PDT 24 Aug 07 08:54:58 PM PDT 24 11437187936 ps
T1251 /workspace/coverage/default/1.chip_sw_csrng_smoketest.1578468238 Aug 07 08:07:56 PM PDT 24 Aug 07 08:12:13 PM PDT 24 3301156170 ps
T1252 /workspace/coverage/default/4.chip_tap_straps_dev.1745535707 Aug 07 08:20:51 PM PDT 24 Aug 07 08:23:36 PM PDT 24 3054517878 ps
T1253 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3740848996 Aug 07 08:09:48 PM PDT 24 Aug 07 08:24:32 PM PDT 24 5493341576 ps
T144 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3775861132 Aug 07 07:54:16 PM PDT 24 Aug 07 08:02:26 PM PDT 24 5061211580 ps
T1254 /workspace/coverage/default/0.chip_tap_straps_dev.3191308829 Aug 07 07:53:32 PM PDT 24 Aug 07 07:56:18 PM PDT 24 3291901565 ps
T819 /workspace/coverage/default/11.chip_sw_all_escalation_resets.1764395846 Aug 07 08:23:18 PM PDT 24 Aug 07 08:36:41 PM PDT 24 5437283224 ps
T840 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1880573671 Aug 07 08:24:33 PM PDT 24 Aug 07 08:30:07 PM PDT 24 3609698848 ps
T1255 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3849453261 Aug 07 08:08:25 PM PDT 24 Aug 07 08:18:35 PM PDT 24 5394497984 ps
T1256 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1919737840 Aug 07 08:00:58 PM PDT 24 Aug 07 08:16:31 PM PDT 24 9272639049 ps
T430 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1156062696 Aug 07 08:17:38 PM PDT 24 Aug 07 08:23:31 PM PDT 24 7466467640 ps
T243 /workspace/coverage/default/0.chip_sw_flash_init.1479547611 Aug 07 07:50:40 PM PDT 24 Aug 07 08:31:09 PM PDT 24 21085056108 ps
T1257 /workspace/coverage/default/24.chip_sw_all_escalation_resets.2495618985 Aug 07 08:23:58 PM PDT 24 Aug 07 08:32:44 PM PDT 24 5261144556 ps
T1258 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.457116123 Aug 07 07:58:42 PM PDT 24 Aug 07 08:19:08 PM PDT 24 8529540430 ps
T1259 /workspace/coverage/default/93.chip_sw_all_escalation_resets.1638663196 Aug 07 08:31:50 PM PDT 24 Aug 07 08:41:02 PM PDT 24 5755307902 ps
T11 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.85584589 Aug 07 08:16:09 PM PDT 24 Aug 07 08:20:17 PM PDT 24 2888175738 ps
T295 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.965655490 Aug 07 07:57:50 PM PDT 24 Aug 07 08:03:45 PM PDT 24 3126070828 ps
T1260 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.37184215 Aug 07 08:11:09 PM PDT 24 Aug 07 08:25:37 PM PDT 24 4696457452 ps
T1261 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2316398293 Aug 07 08:14:33 PM PDT 24 Aug 07 08:27:04 PM PDT 24 7032611980 ps
T1262 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1230662804 Aug 07 07:58:47 PM PDT 24 Aug 07 08:58:42 PM PDT 24 14672615988 ps
T207 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.3087907641 Aug 07 07:58:30 PM PDT 24 Aug 07 08:12:48 PM PDT 24 7034927726 ps
T296 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2575629997 Aug 07 07:56:32 PM PDT 24 Aug 07 08:00:33 PM PDT 24 2209329340 ps
T792 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1213919496 Aug 07 08:22:48 PM PDT 24 Aug 07 08:29:36 PM PDT 24 3158188138 ps
T1263 /workspace/coverage/default/0.chip_sw_example_manufacturer.2520416650 Aug 07 07:50:59 PM PDT 24 Aug 07 07:53:48 PM PDT 24 3039568546 ps
T1264 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.2210531915 Aug 07 08:07:50 PM PDT 24 Aug 07 08:17:56 PM PDT 24 3977713288 ps
T757 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3430310164 Aug 07 08:13:08 PM PDT 24 Aug 07 08:28:08 PM PDT 24 5567555960 ps
T1265 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1770973092 Aug 07 07:52:59 PM PDT 24 Aug 07 08:12:53 PM PDT 24 7446349478 ps
T1266 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.1868788405 Aug 07 08:15:16 PM PDT 24 Aug 07 08:19:59 PM PDT 24 2976798040 ps
T1267 /workspace/coverage/default/2.chip_sival_flash_info_access.1637959265 Aug 07 08:10:44 PM PDT 24 Aug 07 08:17:25 PM PDT 24 3304357388 ps
T1268 /workspace/coverage/default/0.chip_sw_uart_smoketest.2411123446 Aug 07 07:56:48 PM PDT 24 Aug 07 08:01:22 PM PDT 24 2973936998 ps
T1269 /workspace/coverage/default/3.chip_sw_uart_tx_rx.3852463231 Aug 07 08:21:01 PM PDT 24 Aug 07 08:30:44 PM PDT 24 4114021350 ps
T1270 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1522183325 Aug 07 07:53:10 PM PDT 24 Aug 07 08:01:42 PM PDT 24 5082887584 ps
T1271 /workspace/coverage/default/92.chip_sw_all_escalation_resets.473173902 Aug 07 08:31:37 PM PDT 24 Aug 07 08:44:13 PM PDT 24 4978001786 ps
T1272 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.262024212 Aug 07 07:52:11 PM PDT 24 Aug 07 07:57:59 PM PDT 24 3438012940 ps
T759 /workspace/coverage/default/1.rom_raw_unlock.49591217 Aug 07 08:07:31 PM PDT 24 Aug 07 08:11:23 PM PDT 24 5712691440 ps
T169 /workspace/coverage/default/51.chip_sw_all_escalation_resets.2884666613 Aug 07 08:27:31 PM PDT 24 Aug 07 08:39:23 PM PDT 24 5923826024 ps
T1273 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2444849092 Aug 07 07:55:53 PM PDT 24 Aug 07 08:06:41 PM PDT 24 4059930800 ps
T1274 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.770196825 Aug 07 07:52:43 PM PDT 24 Aug 07 08:08:04 PM PDT 24 5810910064 ps
T1275 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1230205324 Aug 07 08:16:37 PM PDT 24 Aug 07 08:25:53 PM PDT 24 4559181528 ps
T1276 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.301596380 Aug 07 07:59:49 PM PDT 24 Aug 07 08:06:02 PM PDT 24 4215803516 ps
T39 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3759154865 Aug 07 08:11:14 PM PDT 24 Aug 07 08:15:40 PM PDT 24 3225771260 ps
T1277 /workspace/coverage/default/2.chip_sw_uart_smoketest.2003718697 Aug 07 08:19:31 PM PDT 24 Aug 07 08:25:25 PM PDT 24 3243803136 ps
T1278 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.474934787 Aug 07 08:12:57 PM PDT 24 Aug 07 09:08:54 PM PDT 24 16578179440 ps
T808 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2462654559 Aug 07 08:29:34 PM PDT 24 Aug 07 08:39:02 PM PDT 24 3896297456 ps
T1279 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1118047743 Aug 07 08:03:29 PM PDT 24 Aug 07 08:07:49 PM PDT 24 3473469600 ps
T1280 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2764940147 Aug 07 08:29:07 PM PDT 24 Aug 07 08:35:58 PM PDT 24 3829110830 ps
T1281 /workspace/coverage/default/1.chip_sw_otbn_randomness.662631165 Aug 07 08:01:04 PM PDT 24 Aug 07 08:14:41 PM PDT 24 6057457252 ps
T812 /workspace/coverage/default/68.chip_sw_all_escalation_resets.860607336 Aug 07 08:29:05 PM PDT 24 Aug 07 08:40:24 PM PDT 24 6768181028 ps
T1282 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.508383370 Aug 07 08:00:04 PM PDT 24 Aug 07 09:07:45 PM PDT 24 15822591850 ps
T118 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3739757376 Aug 07 07:54:42 PM PDT 24 Aug 07 08:22:30 PM PDT 24 23056048600 ps
T1283 /workspace/coverage/default/52.chip_sw_all_escalation_resets.1255629260 Aug 07 08:27:14 PM PDT 24 Aug 07 08:38:55 PM PDT 24 4973769956 ps
T1284 /workspace/coverage/default/42.chip_sw_all_escalation_resets.3073764429 Aug 07 08:28:29 PM PDT 24 Aug 07 08:39:18 PM PDT 24 4977467800 ps
T785 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2719849369 Aug 07 07:56:06 PM PDT 24 Aug 07 08:10:19 PM PDT 24 4978460220 ps
T1285 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.627820956 Aug 07 08:16:39 PM PDT 24 Aug 07 08:22:27 PM PDT 24 3301944606 ps
T1286 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1928146119 Aug 07 08:17:12 PM PDT 24 Aug 07 08:30:08 PM PDT 24 4608271937 ps
T211 /workspace/coverage/default/1.chip_jtag_mem_access.4205385848 Aug 07 07:58:34 PM PDT 24 Aug 07 08:25:57 PM PDT 24 13677465974 ps
T42 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1040754693 Aug 07 08:12:37 PM PDT 24 Aug 07 08:19:18 PM PDT 24 5371379400 ps
T1287 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.726010839 Aug 07 07:53:21 PM PDT 24 Aug 07 08:20:31 PM PDT 24 7513345720 ps
T165 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3905211962 Aug 07 07:52:58 PM PDT 24 Aug 07 07:55:58 PM PDT 24 2851976997 ps
T1288 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.2765765345 Aug 07 07:51:51 PM PDT 24 Aug 07 08:09:46 PM PDT 24 5479702080 ps
T431 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.475424039 Aug 07 07:57:11 PM PDT 24 Aug 07 08:36:25 PM PDT 24 24591153560 ps
T771 /workspace/coverage/default/33.chip_sw_all_escalation_resets.1833876305 Aug 07 08:25:06 PM PDT 24 Aug 07 08:34:50 PM PDT 24 4864817032 ps
T1289 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1590463797 Aug 07 08:03:36 PM PDT 24 Aug 07 08:26:53 PM PDT 24 7294194280 ps
T196 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.179233114 Aug 07 08:10:02 PM PDT 24 Aug 07 09:37:11 PM PDT 24 45338118216 ps
T208 /workspace/coverage/default/0.chip_sw_power_virus.127417203 Aug 07 07:59:56 PM PDT 24 Aug 07 08:26:11 PM PDT 24 5936462492 ps
T1290 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.238394252 Aug 07 08:13:49 PM PDT 24 Aug 07 10:13:35 PM PDT 24 28519891608 ps
T1291 /workspace/coverage/default/0.chip_sw_kmac_idle.2133746422 Aug 07 07:54:05 PM PDT 24 Aug 07 07:59:11 PM PDT 24 3261383636 ps
T1292 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.811388002 Aug 07 08:11:32 PM PDT 24 Aug 07 08:45:30 PM PDT 24 32063338624 ps
T806 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.692890986 Aug 07 08:24:00 PM PDT 24 Aug 07 08:31:07 PM PDT 24 4459644056 ps
T1293 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.940634844 Aug 07 08:11:17 PM PDT 24 Aug 07 08:13:04 PM PDT 24 2128279636 ps
T1294 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3994238363 Aug 07 07:54:07 PM PDT 24 Aug 07 09:12:44 PM PDT 24 25229736995 ps
T1295 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.822017406 Aug 07 08:06:19 PM PDT 24 Aug 07 08:13:53 PM PDT 24 4103163720 ps
T1296 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1182257501 Aug 07 08:10:23 PM PDT 24 Aug 07 09:46:04 PM PDT 24 49049798498 ps
T800 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3883901058 Aug 07 08:31:42 PM PDT 24 Aug 07 08:38:26 PM PDT 24 3474675864 ps
T1297 /workspace/coverage/default/0.rom_e2e_asm_init_prod.2315083302 Aug 07 07:57:03 PM PDT 24 Aug 07 09:08:03 PM PDT 24 15267925704 ps
T1298 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2404144235 Aug 07 08:07:06 PM PDT 24 Aug 07 08:14:59 PM PDT 24 4331703844 ps
T1299 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.439177489 Aug 07 08:20:42 PM PDT 24 Aug 07 08:24:54 PM PDT 24 2885414244 ps
T1300 /workspace/coverage/default/17.chip_sw_all_escalation_resets.4262012067 Aug 07 08:24:25 PM PDT 24 Aug 07 08:35:31 PM PDT 24 4559897120 ps
T319 /workspace/coverage/default/2.chip_plic_all_irqs_20.1847658734 Aug 07 08:16:10 PM PDT 24 Aug 07 08:30:27 PM PDT 24 5145183650 ps
T1301 /workspace/coverage/default/2.chip_sw_aes_masking_off.432692626 Aug 07 08:12:29 PM PDT 24 Aug 07 08:16:52 PM PDT 24 3155624310 ps
T1302 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.350215525 Aug 07 07:51:25 PM PDT 24 Aug 07 08:03:59 PM PDT 24 6346815730 ps
T1303 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.1582629403 Aug 07 08:19:02 PM PDT 24 Aug 07 08:23:15 PM PDT 24 2495241600 ps
T1304 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1694779413 Aug 07 08:21:54 PM PDT 24 Aug 07 08:29:36 PM PDT 24 4337209750 ps
T288 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2900349765 Aug 07 08:25:00 PM PDT 24 Aug 07 08:31:57 PM PDT 24 4171322520 ps
T209 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1649076971 Aug 07 07:52:08 PM PDT 24 Aug 07 08:02:06 PM PDT 24 4601998451 ps
T1305 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1925865687 Aug 07 08:02:25 PM PDT 24 Aug 07 09:19:35 PM PDT 24 15415930000 ps
T1306 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2861484214 Aug 07 07:57:26 PM PDT 24 Aug 07 08:13:07 PM PDT 24 5429816579 ps
T1307 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.788234351 Aug 07 07:53:15 PM PDT 24 Aug 07 07:58:40 PM PDT 24 2925869160 ps
T1308 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3972466144 Aug 07 07:51:02 PM PDT 24 Aug 07 08:01:04 PM PDT 24 4279129688 ps
T1309 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3660990820 Aug 07 08:00:37 PM PDT 24 Aug 07 08:08:24 PM PDT 24 8623597576 ps
T1310 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2637646446 Aug 07 08:17:57 PM PDT 24 Aug 07 08:26:07 PM PDT 24 6567699616 ps
T1311 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3762805488 Aug 07 07:58:40 PM PDT 24 Aug 07 09:06:35 PM PDT 24 14612527160 ps
T56 /workspace/coverage/default/2.chip_sw_alert_test.3456960860 Aug 07 08:11:52 PM PDT 24 Aug 07 08:15:34 PM PDT 24 2501637624 ps
T1312 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1529902522 Aug 07 08:03:22 PM PDT 24 Aug 07 08:20:55 PM PDT 24 8972939380 ps
T841 /workspace/coverage/default/85.chip_sw_all_escalation_resets.3064313654 Aug 07 08:31:02 PM PDT 24 Aug 07 08:44:25 PM PDT 24 5849472364 ps
T1313 /workspace/coverage/default/2.chip_sw_aes_idle.2551553481 Aug 07 08:13:43 PM PDT 24 Aug 07 08:18:44 PM PDT 24 2871922576 ps
T1314 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3222176545 Aug 07 08:11:50 PM PDT 24 Aug 07 09:18:15 PM PDT 24 14951682160 ps
T1315 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2798531961 Aug 07 08:05:11 PM PDT 24 Aug 07 08:16:14 PM PDT 24 3914933214 ps
T1316 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.1213259803 Aug 07 08:23:52 PM PDT 24 Aug 07 08:31:43 PM PDT 24 5951079025 ps
T1317 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.4056168624 Aug 07 07:56:22 PM PDT 24 Aug 07 08:18:37 PM PDT 24 10842823184 ps
T1318 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.3405302799 Aug 07 08:19:52 PM PDT 24 Aug 07 08:30:30 PM PDT 24 4672087720 ps
T1319 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.2164310811 Aug 07 07:51:05 PM PDT 24 Aug 07 07:59:02 PM PDT 24 4144493800 ps
T1320 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2831811521 Aug 07 08:17:40 PM PDT 24 Aug 07 08:37:23 PM PDT 24 7832514129 ps
T1321 /workspace/coverage/default/1.chip_sw_edn_auto_mode.1718467573 Aug 07 08:03:37 PM PDT 24 Aug 07 08:22:51 PM PDT 24 4495445624 ps
T1322 /workspace/coverage/default/0.rom_e2e_asm_init_dev.3327037096 Aug 07 07:59:23 PM PDT 24 Aug 07 09:04:14 PM PDT 24 15066384135 ps
T1323 /workspace/coverage/default/1.rom_e2e_asm_init_dev.22680819 Aug 07 08:10:47 PM PDT 24 Aug 07 09:19:09 PM PDT 24 15063687792 ps
T1324 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.2482634754 Aug 07 08:06:31 PM PDT 24 Aug 07 08:13:44 PM PDT 24 5292262924 ps
T1325 /workspace/coverage/default/1.chip_sw_hmac_multistream.2818971053 Aug 07 08:03:49 PM PDT 24 Aug 07 08:30:39 PM PDT 24 8031082036 ps
T302 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.709337047 Aug 07 08:15:24 PM PDT 24 Aug 07 08:33:15 PM PDT 24 9184616242 ps
T1326 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3458497692 Aug 07 08:03:43 PM PDT 24 Aug 07 08:09:21 PM PDT 24 3063289090 ps
T1327 /workspace/coverage/default/1.chip_sw_edn_sw_mode.2834569146 Aug 07 08:02:33 PM PDT 24 Aug 07 08:46:35 PM PDT 24 9948519810 ps
T1328 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.919970 Aug 07 08:06:56 PM PDT 24 Aug 07 08:55:02 PM PDT 24 14507623276 ps
T261 /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.356070658 Aug 07 07:54:20 PM PDT 24 Aug 07 08:29:15 PM PDT 24 11734925587 ps
T1329 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2218350898 Aug 07 08:10:03 PM PDT 24 Aug 07 08:21:03 PM PDT 24 4228482442 ps
T1330 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3332085595 Aug 07 08:16:03 PM PDT 24 Aug 07 08:25:48 PM PDT 24 4004649623 ps
T1331 /workspace/coverage/default/2.chip_sw_uart_tx_rx.2338341031 Aug 07 08:11:34 PM PDT 24 Aug 07 08:20:26 PM PDT 24 3882261276 ps
T1332 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.761325465 Aug 07 07:59:56 PM PDT 24 Aug 07 09:07:06 PM PDT 24 15485056960 ps
T1333 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3356949369 Aug 07 08:08:32 PM PDT 24 Aug 07 08:20:13 PM PDT 24 4363589116 ps
T373 /workspace/coverage/default/2.chip_sw_hmac_enc.3332856072 Aug 07 08:14:45 PM PDT 24 Aug 07 08:20:00 PM PDT 24 3254520966 ps
T1334 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.2735666922 Aug 07 07:52:39 PM PDT 24 Aug 07 07:56:38 PM PDT 24 2952356924 ps
T1335 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3653637095 Aug 07 07:54:13 PM PDT 24 Aug 07 08:49:46 PM PDT 24 20441627189 ps
T1336 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1196423050 Aug 07 08:03:37 PM PDT 24 Aug 07 11:42:43 PM PDT 24 254731981740 ps
T1337 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.3362380250 Aug 07 08:17:43 PM PDT 24 Aug 07 08:36:59 PM PDT 24 7260998014 ps
T1338 /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.4253192771 Aug 07 08:08:55 PM PDT 24 Aug 07 11:11:56 PM PDT 24 59174303581 ps
T297 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1072436728 Aug 07 08:06:34 PM PDT 24 Aug 07 08:09:52 PM PDT 24 2439457400 ps
T810 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2962875644 Aug 07 08:22:34 PM PDT 24 Aug 07 08:28:53 PM PDT 24 3526060736 ps
T1339 /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.77306471 Aug 07 08:22:21 PM PDT 24 Aug 07 10:02:02 PM PDT 24 26732370968 ps
T1340 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3077461194 Aug 07 07:57:21 PM PDT 24 Aug 07 09:28:09 PM PDT 24 22896675937 ps
T1341 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.1437183479 Aug 07 07:57:06 PM PDT 24 Aug 07 10:57:31 PM PDT 24 58335382458 ps
T1342 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1661785602 Aug 07 08:12:22 PM PDT 24 Aug 07 08:46:53 PM PDT 24 17814346370 ps
T1343 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1278936009 Aug 07 08:07:04 PM PDT 24 Aug 07 08:13:00 PM PDT 24 6316132584 ps
T96 /workspace/coverage/default/27.chip_sw_all_escalation_resets.2263248844 Aug 07 08:27:22 PM PDT 24 Aug 07 08:39:59 PM PDT 24 6276050760 ps
T1344 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.271647999 Aug 07 08:23:10 PM PDT 24 Aug 07 08:33:39 PM PDT 24 5586936196 ps
T1345 /workspace/coverage/default/2.rom_e2e_asm_init_prod.3518135115 Aug 07 08:24:47 PM PDT 24 Aug 07 09:33:59 PM PDT 24 15791161182 ps
T1346 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1720355242 Aug 07 07:58:38 PM PDT 24 Aug 07 08:59:26 PM PDT 24 14336738260 ps
T1347 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3303082066 Aug 07 08:12:14 PM PDT 24 Aug 07 08:23:44 PM PDT 24 4913005389 ps
T1348 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2023655806 Aug 07 08:01:44 PM PDT 24 Aug 07 08:28:05 PM PDT 24 8858163374 ps
T1349 /workspace/coverage/default/0.chip_sw_coremark.235336428 Aug 07 07:54:13 PM PDT 24 Aug 08 12:06:10 AM PDT 24 71800034400 ps
T1350 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2365561012 Aug 07 08:12:48 PM PDT 24 Aug 07 09:18:52 PM PDT 24 25320855425 ps
T1351 /workspace/coverage/default/1.chip_sw_example_flash.3562859434 Aug 07 07:54:49 PM PDT 24 Aug 07 07:58:26 PM PDT 24 2807975192 ps
T1352 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.11754432 Aug 07 07:58:49 PM PDT 24 Aug 07 08:02:55 PM PDT 24 3005668444 ps
T352 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1683152007 Aug 07 07:56:50 PM PDT 24 Aug 07 08:09:57 PM PDT 24 4552474439 ps
T1353 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1429753007 Aug 07 08:12:01 PM PDT 24 Aug 07 08:45:38 PM PDT 24 24640763144 ps
T1354 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2673293039 Aug 07 07:56:35 PM PDT 24 Aug 07 08:02:34 PM PDT 24 3249871640 ps
T798 /workspace/coverage/default/99.chip_sw_all_escalation_resets.2364363338 Aug 07 08:30:47 PM PDT 24 Aug 07 08:43:57 PM PDT 24 5753128980 ps
T1355 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.732429297 Aug 07 08:03:47 PM PDT 24 Aug 07 08:08:55 PM PDT 24 3328089933 ps
T1356 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.457463829 Aug 07 07:53:48 PM PDT 24 Aug 07 08:09:57 PM PDT 24 5850590920 ps
T326 /workspace/coverage/default/2.chip_plic_all_irqs_0.1671807186 Aug 07 08:15:39 PM PDT 24 Aug 07 08:38:58 PM PDT 24 5728234024 ps
T1357 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2712750296 Aug 07 08:00:15 PM PDT 24 Aug 07 08:05:28 PM PDT 24 2710879969 ps
T1358 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.926170934 Aug 07 08:26:03 PM PDT 24 Aug 07 08:34:03 PM PDT 24 4103316758 ps
T1359 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1029103751 Aug 07 08:15:19 PM PDT 24 Aug 07 08:25:37 PM PDT 24 3823046764 ps
T1360 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1050219402 Aug 07 08:18:10 PM PDT 24 Aug 07 08:25:30 PM PDT 24 4112027898 ps
T1361 /workspace/coverage/default/1.chip_tap_straps_prod.1763619345 Aug 07 08:06:17 PM PDT 24 Aug 07 08:08:22 PM PDT 24 2434763622 ps
T1362 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3326252013 Aug 07 07:59:25 PM PDT 24 Aug 07 09:12:50 PM PDT 24 15188114952 ps
T811 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2359809513 Aug 07 08:24:35 PM PDT 24 Aug 07 08:33:13 PM PDT 24 3730601400 ps
T1363 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1213721897 Aug 07 08:27:31 PM PDT 24 Aug 07 08:37:00 PM PDT 24 3949588018 ps
T1364 /workspace/coverage/default/1.chip_sw_aes_masking_off.3167826510 Aug 07 08:02:54 PM PDT 24 Aug 07 08:08:31 PM PDT 24 2720707076 ps
T832 /workspace/coverage/default/41.chip_sw_all_escalation_resets.3655618339 Aug 07 08:26:09 PM PDT 24 Aug 07 08:37:23 PM PDT 24 5436023616 ps
T1365 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1076338115 Aug 07 07:51:18 PM PDT 24 Aug 07 08:03:33 PM PDT 24 4365506954 ps
T1366 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1760526661 Aug 07 08:16:30 PM PDT 24 Aug 07 08:25:37 PM PDT 24 4300130082 ps
T1367 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1672632305 Aug 07 08:25:15 PM PDT 24 Aug 07 08:33:57 PM PDT 24 3673322216 ps
T1368 /workspace/coverage/default/47.chip_sw_all_escalation_resets.4096611188 Aug 07 08:27:02 PM PDT 24 Aug 07 08:38:35 PM PDT 24 5488677334 ps
T388 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1575451213 Aug 07 07:52:57 PM PDT 24 Aug 07 08:04:28 PM PDT 24 5753050312 ps
T848 /workspace/coverage/default/86.chip_sw_all_escalation_resets.1194494158 Aug 07 08:31:45 PM PDT 24 Aug 07 08:44:39 PM PDT 24 5853247012 ps
T232 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2288606133 Aug 07 08:06:13 PM PDT 24 Aug 07 08:54:44 PM PDT 24 11894084984 ps
T857 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2398930552 Aug 07 08:29:40 PM PDT 24 Aug 07 08:36:34 PM PDT 24 3661989048 ps
T1369 /workspace/coverage/default/30.chip_sw_all_escalation_resets.3282123268 Aug 07 08:26:29 PM PDT 24 Aug 07 08:40:56 PM PDT 24 6047675720 ps
T1370 /workspace/coverage/default/49.chip_sw_all_escalation_resets.1020611818 Aug 07 08:27:56 PM PDT 24 Aug 07 08:36:52 PM PDT 24 4831428412 ps
T838 /workspace/coverage/default/48.chip_sw_all_escalation_resets.3053065951 Aug 07 08:27:08 PM PDT 24 Aug 07 08:39:10 PM PDT 24 5022232530 ps
T1371 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2108012083 Aug 07 07:53:06 PM PDT 24 Aug 07 08:03:05 PM PDT 24 4954664908 ps
T1372 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.470319261 Aug 07 07:56:14 PM PDT 24 Aug 07 08:06:28 PM PDT 24 4967287596 ps
T346 /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2990385676 Aug 07 07:53:13 PM PDT 24 Aug 07 07:59:26 PM PDT 24 4260361916 ps
T343 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3436149891 Aug 07 07:57:05 PM PDT 24 Aug 07 08:07:31 PM PDT 24 4500367130 ps
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