Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.68	96.99	84.51			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.72	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T55,T59,T360

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T55,T59,T360
1	1	Covered	T55,T59,T360

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T55,T59,T360

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T55,T59,T360
1	1	Covered	T55,T59,T360

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T55,T59,T360
0	0	1	Covered	T55,T59,T360
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T55,T59,T360
0	0	1	Covered	T55,T59,T360
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153385102	99822	0	0
DstReqKnown_A	1876502	1649632	0	0
SrcAckBusyChk_A	153385102	254	0	0
SrcBusyKnown_A	153385102	152556632	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153385102	99822	0	0
T55	451755	375	0	0
T59	0	450	0	0
T147	0	2651	0	0
T148	0	713	0	0
T149	0	1080	0	0
T322	45678	0	0	0
T344	42844	0	0	0
T359	0	4937	0	0
T360	0	458	0	0
T386	0	385	0	0
T387	0	772	0	0
T388	0	308	0	0
T394	78841	0	0	0
T395	50623	0	0	0
T396	326836	0	0	0
T397	40784	0	0	0
T398	127173	0	0	0
T399	61297	0	0	0
T400	51047	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1876502	1649632	0	0
T1	293	120	0	0
T2	608	435	0	0
T3	5010	4836	0	0
T4	432	261	0	0
T5	705	531	0	0
T6	540	368	0	0
T16	420	247	0	0
T34	795	617	0	0
T95	4755	4583	0	0
T96	360	187	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153385102	254	0	0
T55	451755	1	0	0
T59	0	1	0	0
T147	0	6	0	0
T148	0	2	0	0
T149	0	3	0	0
T322	45678	0	0	0
T344	42844	0	0	0
T359	0	12	0	0
T360	0	1	0	0
T386	0	1	0	0
T387	0	2	0	0
T388	0	1	0	0
T394	78841	0	0	0
T395	50623	0	0	0
T396	326836	0	0	0
T397	40784	0	0	0
T398	127173	0	0	0
T399	61297	0	0	0
T400	51047	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153385102	152556632	0	0
T1	10234	9706	0	0
T2	43786	43303	0	0
T3	571526	571059	0	0
T4	23293	22873	0	0
T5	54483	54030	0	0
T6	35503	34939	0	0
T16	20716	20307	0	0
T34	44949	44037	0	0
T95	548528	547809	0	0
T96	23838	23017	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T55,T59,T360

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T55,T59,T360
1	1	Covered	T55,T59,T360

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T55,T59,T360

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T55,T59,T360
1	1	Covered	T55,T59,T360

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T55,T59,T360
0	0	1	Covered	T55,T59,T360
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T55,T59,T360
0	0	1	Covered	T55,T59,T360
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153385102	95459	0	0
DstReqKnown_A	1876502	1649632	0	0
SrcAckBusyChk_A	153385102	243	0	0
SrcBusyKnown_A	153385102	152556632	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153385102	95459	0	0
T55	451755	402	0	0
T59	0	396	0	0
T147	0	4880	0	0
T148	0	726	0	0
T149	0	1555	0	0
T322	45678	0	0	0
T344	42844	0	0	0
T359	0	2030	0	0
T360	0	431	0	0
T386	0	472	0	0
T387	0	764	0	0
T388	0	337	0	0
T394	78841	0	0	0
T395	50623	0	0	0
T396	326836	0	0	0
T397	40784	0	0	0
T398	127173	0	0	0
T399	61297	0	0	0
T400	51047	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1876502	1649632	0	0
T1	293	120	0	0
T2	608	435	0	0
T3	5010	4836	0	0
T4	432	261	0	0
T5	705	531	0	0
T6	540	368	0	0
T16	420	247	0	0
T34	795	617	0	0
T95	4755	4583	0	0
T96	360	187	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153385102	243	0	0
T55	451755	1	0	0
T59	0	1	0	0
T147	0	11	0	0
T148	0	2	0	0
T149	0	4	0	0
T322	45678	0	0	0
T344	42844	0	0	0
T359	0	5	0	0
T360	0	1	0	0
T386	0	1	0	0
T387	0	2	0	0
T388	0	1	0	0
T394	78841	0	0	0
T395	50623	0	0	0
T396	326836	0	0	0
T397	40784	0	0	0
T398	127173	0	0	0
T399	61297	0	0	0
T400	51047	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153385102	152556632	0	0
T1	10234	9706	0	0
T2	43786	43303	0	0
T3	571526	571059	0	0
T4	23293	22873	0	0
T5	54483	54030	0	0
T6	35503	34939	0	0
T16	20716	20307	0	0
T34	44949	44037	0	0
T95	548528	547809	0	0
T96	23838	23017	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T55,T59,T89

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T55,T59,T360
1	1	Covered	T55,T59,T360

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T55,T59,T360

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T55,T59,T360
1	1	Covered	T55,T59,T360

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T55,T59,T360
0	0	1	Covered	T55,T59,T360
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T55,T59,T360
0	0	1	Covered	T55,T59,T360
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153385102	95511	0	0
DstReqKnown_A	1876502	1649632	0	0
SrcAckBusyChk_A	153385102	243	0	0
SrcBusyKnown_A	153385102	152556632	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153385102	95511	0	0
T55	451755	378	0	0
T59	0	463	0	0
T147	0	1873	0	0
T148	0	685	0	0
T149	0	3900	0	0
T322	45678	0	0	0
T344	42844	0	0	0
T359	0	2045	0	0
T360	0	450	0	0
T386	0	413	0	0
T387	0	698	0	0
T388	0	335	0	0
T394	78841	0	0	0
T395	50623	0	0	0
T396	326836	0	0	0
T397	40784	0	0	0
T398	127173	0	0	0
T399	61297	0	0	0
T400	51047	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1876502	1649632	0	0
T1	293	120	0	0
T2	608	435	0	0
T3	5010	4836	0	0
T4	432	261	0	0
T5	705	531	0	0
T6	540	368	0	0
T16	420	247	0	0
T34	795	617	0	0
T95	4755	4583	0	0
T96	360	187	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153385102	243	0	0
T55	451755	1	0	0
T59	0	1	0	0
T147	0	4	0	0
T148	0	2	0	0
T149	0	9	0	0
T322	45678	0	0	0
T344	42844	0	0	0
T359	0	5	0	0
T360	0	1	0	0
T386	0	1	0	0
T387	0	2	0	0
T388	0	1	0	0
T394	78841	0	0	0
T395	50623	0	0	0
T396	326836	0	0	0
T397	40784	0	0	0
T398	127173	0	0	0
T399	61297	0	0	0
T400	51047	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153385102	152556632	0	0
T1	10234	9706	0	0
T2	43786	43303	0	0
T3	571526	571059	0	0
T4	23293	22873	0	0
T5	54483	54030	0	0
T6	35503	34939	0	0
T16	20716	20307	0	0
T34	44949	44037	0	0
T95	548528	547809	0	0
T96	23838	23017	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T55,T59,T360

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T55,T59,T360
1	1	Covered	T55,T59,T360

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T55,T59,T360

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T55,T59,T360
1	1	Covered	T55,T59,T360

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T55,T59,T360
0	0	1	Covered	T55,T59,T360
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T55,T59,T360
0	0	1	Covered	T55,T59,T360
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153385102	86829	0	0
DstReqKnown_A	1876502	1649632	0	0
SrcAckBusyChk_A	153385102	223	0	0
SrcBusyKnown_A	153385102	152556632	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153385102	86829	0	0
T55	451755	472	0	0
T59	0	463	0	0
T147	0	5313	0	0
T148	0	734	0	0
T149	0	482	0	0
T322	45678	0	0	0
T344	42844	0	0	0
T359	0	2914	0	0
T360	0	439	0	0
T386	0	432	0	0
T387	0	687	0	0
T388	0	318	0	0
T394	78841	0	0	0
T395	50623	0	0	0
T396	326836	0	0	0
T397	40784	0	0	0
T398	127173	0	0	0
T399	61297	0	0	0
T400	51047	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1876502	1649632	0	0
T1	293	120	0	0
T2	608	435	0	0
T3	5010	4836	0	0
T4	432	261	0	0
T5	705	531	0	0
T6	540	368	0	0
T16	420	247	0	0
T34	795	617	0	0
T95	4755	4583	0	0
T96	360	187	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153385102	223	0	0
T55	451755	1	0	0
T59	0	1	0	0
T147	0	12	0	0
T148	0	2	0	0
T149	0	1	0	0
T322	45678	0	0	0
T344	42844	0	0	0
T359	0	7	0	0
T360	0	1	0	0
T386	0	1	0	0
T387	0	2	0	0
T388	0	1	0	0
T394	78841	0	0	0
T395	50623	0	0	0
T396	326836	0	0	0
T397	40784	0	0	0
T398	127173	0	0	0
T399	61297	0	0	0
T400	51047	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153385102	152556632	0	0
T1	10234	9706	0	0
T2	43786	43303	0	0
T3	571526	571059	0	0
T4	23293	22873	0	0
T5	54483	54030	0	0
T6	35503	34939	0	0
T16	20716	20307	0	0
T34	44949	44037	0	0
T95	548528	547809	0	0
T96	23838	23017	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T55,T59,T360

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T55,T59,T360
1	1	Covered	T55,T59,T360

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T55,T59,T360

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T55,T59,T360
1	1	Covered	T55,T59,T360

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T55,T59,T360
0	0	1	Covered	T55,T59,T360
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T55,T59,T360
0	0	1	Covered	T55,T59,T360
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153385102	107013	0	0
DstReqKnown_A	1876502	1649632	0	0
SrcAckBusyChk_A	153385102	272	0	0
SrcBusyKnown_A	153385102	152556632	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153385102	107013	0	0
T55	451755	388	0	0
T59	0	364	0	0
T147	0	1323	0	0
T148	0	737	0	0
T149	0	1575	0	0
T322	45678	0	0	0
T344	42844	0	0	0
T359	0	2880	0	0
T360	0	389	0	0
T386	0	412	0	0
T387	0	782	0	0
T388	0	317	0	0
T394	78841	0	0	0
T395	50623	0	0	0
T396	326836	0	0	0
T397	40784	0	0	0
T398	127173	0	0	0
T399	61297	0	0	0
T400	51047	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1876502	1649632	0	0
T1	293	120	0	0
T2	608	435	0	0
T3	5010	4836	0	0
T4	432	261	0	0
T5	705	531	0	0
T6	540	368	0	0
T16	420	247	0	0
T34	795	617	0	0
T95	4755	4583	0	0
T96	360	187	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153385102	272	0	0
T55	451755	1	0	0
T59	0	1	0	0
T147	0	3	0	0
T148	0	2	0	0
T149	0	4	0	0
T322	45678	0	0	0
T344	42844	0	0	0
T359	0	7	0	0
T360	0	1	0	0
T386	0	1	0	0
T387	0	2	0	0
T388	0	1	0	0
T394	78841	0	0	0
T395	50623	0	0	0
T396	326836	0	0	0
T397	40784	0	0	0
T398	127173	0	0	0
T399	61297	0	0	0
T400	51047	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153385102	152556632	0	0
T1	10234	9706	0	0
T2	43786	43303	0	0
T3	571526	571059	0	0
T4	23293	22873	0	0
T5	54483	54030	0	0
T6	35503	34939	0	0
T16	20716	20307	0	0
T34	44949	44037	0	0
T95	548528	547809	0	0
T96	23838	23017	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T55,T59,T360

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T55,T59,T360
1	1	Covered	T55,T59,T360

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T55,T59,T360

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T55,T59,T360
1	1	Covered	T55,T59,T360

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T55,T59,T360
0	0	1	Covered	T55,T59,T360
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T55,T59,T360
0	0	1	Covered	T55,T59,T360
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153385102	92607	0	0
DstReqKnown_A	1876502	1649632	0	0
SrcAckBusyChk_A	153385102	237	0	0
SrcBusyKnown_A	153385102	152556632	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153385102	92607	0	0
T55	451755	448	0	0
T59	0	481	0	0
T147	0	3468	0	0
T148	0	722	0	0
T149	0	387	0	0
T322	45678	0	0	0
T344	42844	0	0	0
T359	0	4616	0	0
T360	0	475	0	0
T386	0	404	0	0
T387	0	807	0	0
T388	0	341	0	0
T394	78841	0	0	0
T395	50623	0	0	0
T396	326836	0	0	0
T397	40784	0	0	0
T398	127173	0	0	0
T399	61297	0	0	0
T400	51047	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1876502	1649632	0	0
T1	293	120	0	0
T2	608	435	0	0
T3	5010	4836	0	0
T4	432	261	0	0
T5	705	531	0	0
T6	540	368	0	0
T16	420	247	0	0
T34	795	617	0	0
T95	4755	4583	0	0
T96	360	187	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153385102	237	0	0
T55	451755	1	0	0
T59	0	1	0	0
T147	0	8	0	0
T148	0	2	0	0
T149	0	1	0	0
T322	45678	0	0	0
T344	42844	0	0	0
T359	0	11	0	0
T360	0	1	0	0
T386	0	1	0	0
T387	0	2	0	0
T388	0	1	0	0
T394	78841	0	0	0
T395	50623	0	0	0
T396	326836	0	0	0
T397	40784	0	0	0
T398	127173	0	0	0
T399	61297	0	0	0
T400	51047	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153385102	152556632	0	0
T1	10234	9706	0	0
T2	43786	43303	0	0
T3	571526	571059	0	0
T4	23293	22873	0	0
T5	54483	54030	0	0
T6	35503	34939	0	0
T16	20716	20307	0	0
T34	44949	44037	0	0
T95	548528	547809	0	0
T96	23838	23017	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T19,T17,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T17,T27
1	1	Covered	T19,T17,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T19,T17,T27
1	0	Covered	T19,T17,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T17,T27
1	1	Covered	T19,T17,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T19,T17,T27

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T19,T17,T27
0	0	1	Covered	T19,T17,T27
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T19,T17,T27
0	0	1	Covered	T19,T17,T27
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	153385102	118881	0	0
DstReqKnown_A	1876502	1649632	0	0
SrcAckBusyChk_A	153385102	269	0	0
SrcBusyKnown_A	153385102	152556632	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153385102	118881	0	0
T17	0	2128	0	0
T19	131552	1676	0	0
T27	0	1023	0	0
T53	41752	0	0	0
T55	0	403	0	0
T62	0	1416	0	0
T63	0	927	0	0
T65	0	1663	0	0
T106	34561	0	0	0
T107	24477	0	0	0
T108	58838	0	0	0
T109	0	787	0	0
T110	0	947	0	0
T111	22964	0	0	0
T112	28369	0	0	0
T113	44179	0	0	0
T114	181477	0	0	0
T115	15410	0	0	0
T385	0	670	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1876502	1649632	0	0
T1	293	120	0	0
T2	608	435	0	0
T3	5010	4836	0	0
T4	432	261	0	0
T5	705	531	0	0
T6	540	368	0	0
T16	420	247	0	0
T34	795	617	0	0
T95	4755	4583	0	0
T96	360	187	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153385102	269	0	0
T17	0	5	0	0
T19	131552	4	0	0
T27	0	2	0	0
T53	41752	0	0	0
T55	0	1	0	0
T62	0	4	0	0
T63	0	2	0	0
T65	0	5	0	0
T106	34561	0	0	0
T107	24477	0	0	0
T108	58838	0	0	0
T109	0	2	0	0
T110	0	2	0	0
T111	22964	0	0	0
T112	28369	0	0	0
T113	44179	0	0	0
T114	181477	0	0	0
T115	15410	0	0	0
T385	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153385102	152556632	0	0
T1	10234	9706	0	0
T2	43786	43303	0	0
T3	571526	571059	0	0
T4	23293	22873	0	0
T5	54483	54030	0	0
T6	35503	34939	0	0
T16	20716	20307	0	0
T34	44949	44037	0	0
T95	548528	547809	0	0
T96	23838	23017	0	0