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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.01 95.47 93.71 95.33 94.52 97.53 99.51


Total test records in report: 2938
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T328 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.868062553 Aug 11 08:03:36 PM PDT 24 Aug 11 08:18:36 PM PDT 24 4732969650 ps
T815 /workspace/coverage/default/58.chip_sw_all_escalation_resets.2470518950 Aug 11 08:22:38 PM PDT 24 Aug 11 08:31:13 PM PDT 24 5259309900 ps
T1002 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1862296198 Aug 11 08:18:13 PM PDT 24 Aug 11 09:24:25 PM PDT 24 16148749780 ps
T1003 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.169488635 Aug 11 08:16:10 PM PDT 24 Aug 11 08:24:33 PM PDT 24 6082668446 ps
T305 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3958001408 Aug 11 08:19:25 PM PDT 24 Aug 11 08:28:03 PM PDT 24 3825106240 ps
T823 /workspace/coverage/default/5.chip_sw_all_escalation_resets.835388947 Aug 11 08:14:52 PM PDT 24 Aug 11 08:23:17 PM PDT 24 5560107432 ps
T1004 /workspace/coverage/default/0.chip_sw_csrng_smoketest.441839591 Aug 11 07:49:57 PM PDT 24 Aug 11 07:54:08 PM PDT 24 3199732142 ps
T1005 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.2173125315 Aug 11 07:40:37 PM PDT 24 Aug 11 07:45:40 PM PDT 24 3095936392 ps
T1006 /workspace/coverage/default/0.chip_sw_hmac_oneshot.345366557 Aug 11 07:41:20 PM PDT 24 Aug 11 07:46:42 PM PDT 24 2675853048 ps
T156 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1950095738 Aug 11 07:38:06 PM PDT 24 Aug 11 07:40:34 PM PDT 24 3275233081 ps
T1007 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.1202538226 Aug 11 07:35:14 PM PDT 24 Aug 11 07:48:36 PM PDT 24 11820821965 ps
T1008 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.2930715555 Aug 11 08:16:29 PM PDT 24 Aug 11 08:26:10 PM PDT 24 7337777250 ps
T730 /workspace/coverage/default/0.chip_sw_edn_kat.2855751523 Aug 11 07:38:31 PM PDT 24 Aug 11 07:49:06 PM PDT 24 3031326420 ps
T1009 /workspace/coverage/default/2.rom_e2e_static_critical.1157112798 Aug 11 08:18:34 PM PDT 24 Aug 11 09:27:17 PM PDT 24 16585319800 ps
T58 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.140386692 Aug 11 08:10:12 PM PDT 24 Aug 11 08:33:45 PM PDT 24 22981539720 ps
T1010 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.762525199 Aug 11 08:05:44 PM PDT 24 Aug 11 08:36:32 PM PDT 24 16652668129 ps
T344 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.173919702 Aug 11 08:03:15 PM PDT 24 Aug 11 08:14:27 PM PDT 24 3573969584 ps
T1011 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2719140119 Aug 11 08:02:06 PM PDT 24 Aug 11 08:05:24 PM PDT 24 2927916992 ps
T787 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2364511188 Aug 11 08:23:30 PM PDT 24 Aug 11 08:29:38 PM PDT 24 3223599490 ps
T380 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.177895235 Aug 11 08:23:50 PM PDT 24 Aug 11 08:30:35 PM PDT 24 4287875756 ps
T792 /workspace/coverage/default/99.chip_sw_all_escalation_resets.601350091 Aug 11 08:25:18 PM PDT 24 Aug 11 08:32:37 PM PDT 24 5620114360 ps
T345 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1990600076 Aug 11 08:03:44 PM PDT 24 Aug 11 08:17:01 PM PDT 24 4265880659 ps
T220 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2642385760 Aug 11 07:34:54 PM PDT 24 Aug 11 09:16:02 PM PDT 24 47824083025 ps
T731 /workspace/coverage/default/1.chip_sw_edn_kat.3436731463 Aug 11 07:54:35 PM PDT 24 Aug 11 08:05:41 PM PDT 24 3690680648 ps
T1012 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.3446415092 Aug 11 08:18:35 PM PDT 24 Aug 11 08:28:22 PM PDT 24 6324967708 ps
T1013 /workspace/coverage/default/1.chip_tap_straps_prod.3580556622 Aug 11 07:57:44 PM PDT 24 Aug 11 08:21:07 PM PDT 24 13156505173 ps
T749 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.586803566 Aug 11 07:52:42 PM PDT 24 Aug 11 07:54:31 PM PDT 24 2379446220 ps
T1014 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.539042177 Aug 11 07:49:56 PM PDT 24 Aug 11 07:53:16 PM PDT 24 2576564044 ps
T186 /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2932213928 Aug 11 08:01:43 PM PDT 24 Aug 11 11:02:32 PM PDT 24 59540927186 ps
T1015 /workspace/coverage/default/0.chip_sw_uart_smoketest.1638411870 Aug 11 07:51:12 PM PDT 24 Aug 11 07:56:01 PM PDT 24 2947206244 ps
T1016 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.3021384414 Aug 11 07:34:03 PM PDT 24 Aug 11 10:54:57 PM PDT 24 64709289147 ps
T1017 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2784997893 Aug 11 07:53:04 PM PDT 24 Aug 11 08:57:45 PM PDT 24 41529905608 ps
T1018 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.3754925501 Aug 11 08:16:32 PM PDT 24 Aug 11 09:18:24 PM PDT 24 14429424232 ps
T196 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1783063105 Aug 11 07:50:12 PM PDT 24 Aug 11 08:12:17 PM PDT 24 8146091410 ps
T158 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.2668284229 Aug 11 07:53:38 PM PDT 24 Aug 11 08:07:03 PM PDT 24 8689666380 ps
T264 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2659830945 Aug 11 07:50:36 PM PDT 24 Aug 11 08:50:57 PM PDT 24 14305589912 ps
T330 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3110486534 Aug 11 08:13:27 PM PDT 24 Aug 11 08:24:48 PM PDT 24 4058003756 ps
T169 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3860141255 Aug 11 07:51:14 PM PDT 24 Aug 11 09:17:49 PM PDT 24 43709842676 ps
T1019 /workspace/coverage/default/1.chip_sw_edn_sw_mode.2080016958 Aug 11 07:55:23 PM PDT 24 Aug 11 08:16:16 PM PDT 24 6766677682 ps
T1020 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.428933610 Aug 11 08:05:34 PM PDT 24 Aug 11 09:15:21 PM PDT 24 14287845200 ps
T1021 /workspace/coverage/default/0.chip_sw_coremark.3425452100 Aug 11 07:39:44 PM PDT 24 Aug 11 11:48:51 PM PDT 24 72281946904 ps
T1022 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2198402629 Aug 11 07:36:18 PM PDT 24 Aug 11 07:46:54 PM PDT 24 7477907408 ps
T1023 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.1118135348 Aug 11 08:19:14 PM PDT 24 Aug 11 08:29:53 PM PDT 24 9376974407 ps
T306 /workspace/coverage/default/12.chip_sw_all_escalation_resets.310231964 Aug 11 08:16:46 PM PDT 24 Aug 11 08:31:07 PM PDT 24 6395573340 ps
T42 /workspace/coverage/default/0.chip_sw_power_virus.4259293972 Aug 11 07:48:32 PM PDT 24 Aug 11 08:13:13 PM PDT 24 6150761784 ps
T21 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2777026575 Aug 11 08:05:53 PM PDT 24 Aug 11 08:59:58 PM PDT 24 20822984032 ps
T24 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.3379429641 Aug 11 07:34:36 PM PDT 24 Aug 11 07:39:54 PM PDT 24 4262980036 ps
T1024 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.4062388561 Aug 11 08:17:00 PM PDT 24 Aug 11 08:21:53 PM PDT 24 2991426616 ps
T1025 /workspace/coverage/default/1.chip_sw_aes_idle.958506846 Aug 11 07:53:46 PM PDT 24 Aug 11 07:57:48 PM PDT 24 3060249676 ps
T1026 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1091564367 Aug 11 07:57:56 PM PDT 24 Aug 11 08:04:45 PM PDT 24 3001474224 ps
T793 /workspace/coverage/default/90.chip_sw_all_escalation_resets.2961784705 Aug 11 08:25:43 PM PDT 24 Aug 11 08:36:27 PM PDT 24 5951893746 ps
T302 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2454041211 Aug 11 07:39:38 PM PDT 24 Aug 11 08:05:33 PM PDT 24 6978543720 ps
T385 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1845920488 Aug 11 07:51:33 PM PDT 24 Aug 11 09:41:41 PM PDT 24 24636771770 ps
T360 /workspace/coverage/default/72.chip_sw_all_escalation_resets.3862120906 Aug 11 08:23:10 PM PDT 24 Aug 11 08:36:00 PM PDT 24 6767259028 ps
T1027 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.1890499361 Aug 11 07:51:18 PM PDT 24 Aug 11 08:13:37 PM PDT 24 7225522888 ps
T1028 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.3255782693 Aug 11 07:57:48 PM PDT 24 Aug 11 08:02:06 PM PDT 24 3002316456 ps
T854 /workspace/coverage/default/0.chip_sw_all_escalation_resets.921647208 Aug 11 07:34:24 PM PDT 24 Aug 11 07:42:50 PM PDT 24 5975602248 ps
T1029 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.2331660991 Aug 11 08:10:42 PM PDT 24 Aug 11 08:26:56 PM PDT 24 7723640253 ps
T1030 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2195634646 Aug 11 08:12:37 PM PDT 24 Aug 11 08:32:00 PM PDT 24 6149956128 ps
T733 /workspace/coverage/default/13.chip_sw_all_escalation_resets.2302223182 Aug 11 08:16:38 PM PDT 24 Aug 11 08:33:16 PM PDT 24 6343130136 ps
T820 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3881851921 Aug 11 08:20:18 PM PDT 24 Aug 11 08:28:11 PM PDT 24 4082155866 ps
T178 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.3488039014 Aug 11 08:03:28 PM PDT 24 Aug 11 08:16:34 PM PDT 24 6778990648 ps
T265 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2001922141 Aug 11 07:56:17 PM PDT 24 Aug 11 09:12:56 PM PDT 24 15463024387 ps
T266 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.1051020558 Aug 11 08:16:14 PM PDT 24 Aug 11 08:33:17 PM PDT 24 6278071232 ps
T817 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.1118374455 Aug 11 08:10:27 PM PDT 24 Aug 11 08:26:49 PM PDT 24 7730868804 ps
T327 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3171934516 Aug 11 08:14:13 PM PDT 24 Aug 11 08:25:47 PM PDT 24 4230836040 ps
T90 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1075263577 Aug 11 07:43:00 PM PDT 24 Aug 11 08:08:11 PM PDT 24 24565639288 ps
T313 /workspace/coverage/default/1.chip_plic_all_irqs_20.291310340 Aug 11 07:56:21 PM PDT 24 Aug 11 08:06:25 PM PDT 24 4750034776 ps
T1031 /workspace/coverage/default/0.chip_sw_aon_timer_irq.413105506 Aug 11 07:36:28 PM PDT 24 Aug 11 07:42:04 PM PDT 24 3752865180 ps
T54 /workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.2771469954 Aug 11 08:03:45 PM PDT 24 Aug 11 08:07:40 PM PDT 24 3122511192 ps
T1032 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.150269861 Aug 11 07:56:33 PM PDT 24 Aug 11 08:08:14 PM PDT 24 5572641618 ps
T399 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4162297396 Aug 11 07:57:45 PM PDT 24 Aug 11 08:21:17 PM PDT 24 23927787088 ps
T1033 /workspace/coverage/default/1.chip_sw_uart_smoketest.2331592272 Aug 11 08:02:15 PM PDT 24 Aug 11 08:06:32 PM PDT 24 3065004266 ps
T445 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.35773827 Aug 11 08:15:20 PM PDT 24 Aug 11 08:22:48 PM PDT 24 4035404600 ps
T776 /workspace/coverage/default/0.chip_sw_power_sleep_load.3421826406 Aug 11 07:45:04 PM PDT 24 Aug 11 07:54:41 PM PDT 24 11236105934 ps
T1034 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.2294731222 Aug 11 08:08:21 PM PDT 24 Aug 11 08:37:53 PM PDT 24 8348194844 ps
T841 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1309872814 Aug 11 08:23:54 PM PDT 24 Aug 11 08:31:01 PM PDT 24 3374503542 ps
T1035 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2529673160 Aug 11 08:01:14 PM PDT 24 Aug 11 09:18:31 PM PDT 24 25431088787 ps
T143 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.935505218 Aug 11 07:38:46 PM PDT 24 Aug 11 07:49:54 PM PDT 24 5878227024 ps
T852 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3895508021 Aug 11 08:22:25 PM PDT 24 Aug 11 08:29:55 PM PDT 24 3857075196 ps
T52 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.3938244918 Aug 11 08:03:07 PM PDT 24 Aug 11 08:08:45 PM PDT 24 4286032438 ps
T1036 /workspace/coverage/default/1.chip_sw_example_concurrency.1360217837 Aug 11 07:49:39 PM PDT 24 Aug 11 07:53:56 PM PDT 24 2927008144 ps
T357 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2089785764 Aug 11 08:02:04 PM PDT 24 Aug 11 08:11:29 PM PDT 24 4263267544 ps
T251 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.115520681 Aug 11 08:25:24 PM PDT 24 Aug 11 08:31:49 PM PDT 24 3215200472 ps
T856 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.965536084 Aug 11 08:16:16 PM PDT 24 Aug 11 08:21:54 PM PDT 24 4299072480 ps
T1037 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1338535385 Aug 11 07:53:10 PM PDT 24 Aug 11 09:09:31 PM PDT 24 19315990758 ps
T1038 /workspace/coverage/default/1.chip_sw_kmac_entropy.1391127071 Aug 11 07:51:05 PM PDT 24 Aug 11 07:55:56 PM PDT 24 2989496416 ps
T49 /workspace/coverage/default/2.chip_sw_alert_test.286067425 Aug 11 08:08:38 PM PDT 24 Aug 11 08:12:55 PM PDT 24 2714910900 ps
T848 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2574910298 Aug 11 08:22:58 PM PDT 24 Aug 11 08:27:50 PM PDT 24 3810030622 ps
T1039 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.503956116 Aug 11 08:05:50 PM PDT 24 Aug 11 08:12:47 PM PDT 24 4547721090 ps
T1040 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.1542512698 Aug 11 08:20:04 PM PDT 24 Aug 11 09:12:11 PM PDT 24 12826890144 ps
T81 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.576205540 Aug 11 07:55:59 PM PDT 24 Aug 11 08:01:21 PM PDT 24 3453765868 ps
T1041 /workspace/coverage/default/2.chip_sw_hmac_smoketest.2535393024 Aug 11 08:12:42 PM PDT 24 Aug 11 08:18:44 PM PDT 24 3881705874 ps
T1042 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3354749423 Aug 11 08:03:36 PM PDT 24 Aug 11 08:19:49 PM PDT 24 5499405178 ps
T325 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.2918849449 Aug 11 07:38:34 PM PDT 24 Aug 11 07:56:26 PM PDT 24 5784473780 ps
T164 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2140335287 Aug 11 07:39:24 PM PDT 24 Aug 11 07:49:48 PM PDT 24 7091639611 ps
T1043 /workspace/coverage/default/1.chip_sw_kmac_smoketest.2375151569 Aug 11 08:01:01 PM PDT 24 Aug 11 08:06:19 PM PDT 24 3126277710 ps
T1044 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.1409049599 Aug 11 08:07:21 PM PDT 24 Aug 11 08:10:30 PM PDT 24 2035177884 ps
T269 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.3956384705 Aug 11 08:14:58 PM PDT 24 Aug 11 08:26:32 PM PDT 24 5240443960 ps
T1045 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.1708699734 Aug 11 07:53:14 PM PDT 24 Aug 11 09:10:43 PM PDT 24 15358691880 ps
T157 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3629290329 Aug 11 07:39:12 PM PDT 24 Aug 11 07:42:46 PM PDT 24 3190241603 ps
T1046 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2285059427 Aug 11 07:52:43 PM PDT 24 Aug 11 09:04:47 PM PDT 24 14127536972 ps
T1047 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2999210855 Aug 11 08:16:55 PM PDT 24 Aug 11 09:22:14 PM PDT 24 14060951971 ps
T830 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1470675847 Aug 11 08:19:07 PM PDT 24 Aug 11 08:25:06 PM PDT 24 3100421340 ps
T819 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1016361812 Aug 11 08:20:05 PM PDT 24 Aug 11 08:25:19 PM PDT 24 4026973880 ps
T542 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3659856556 Aug 11 08:08:24 PM PDT 24 Aug 11 08:28:09 PM PDT 24 4847145136 ps
T179 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1824018350 Aug 11 07:34:48 PM PDT 24 Aug 11 07:41:56 PM PDT 24 4635345535 ps
T165 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3749793322 Aug 11 07:56:31 PM PDT 24 Aug 11 08:07:23 PM PDT 24 6704406107 ps
T1048 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.216933544 Aug 11 07:50:52 PM PDT 24 Aug 11 07:55:37 PM PDT 24 2694350099 ps
T1049 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1347378211 Aug 11 07:55:05 PM PDT 24 Aug 11 07:59:16 PM PDT 24 3195686955 ps
T9 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2836017430 Aug 11 08:02:23 PM PDT 24 Aug 11 08:07:38 PM PDT 24 2935935754 ps
T1050 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.4128234183 Aug 11 07:53:49 PM PDT 24 Aug 11 08:03:26 PM PDT 24 7059027200 ps
T1051 /workspace/coverage/default/2.rom_e2e_asm_init_rma.1376866019 Aug 11 08:17:04 PM PDT 24 Aug 11 09:22:43 PM PDT 24 14253227568 ps
T1052 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3016825693 Aug 11 08:05:03 PM PDT 24 Aug 11 08:33:43 PM PDT 24 12345610514 ps
T1053 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2074855020 Aug 11 08:15:17 PM PDT 24 Aug 11 08:30:26 PM PDT 24 10438855092 ps
T1054 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1179294061 Aug 11 08:10:29 PM PDT 24 Aug 11 08:18:27 PM PDT 24 5377507008 ps
T247 /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.2243017466 Aug 11 07:49:06 PM PDT 24 Aug 11 08:28:35 PM PDT 24 11216611883 ps
T82 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1235031932 Aug 11 07:37:12 PM PDT 24 Aug 11 07:41:24 PM PDT 24 3438317628 ps
T1055 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1316672933 Aug 11 07:58:43 PM PDT 24 Aug 11 08:06:30 PM PDT 24 4144644712 ps
T232 /workspace/coverage/default/47.chip_sw_all_escalation_resets.1511210258 Aug 11 08:21:46 PM PDT 24 Aug 11 08:35:24 PM PDT 24 6275914720 ps
T335 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1257475262 Aug 11 07:50:17 PM PDT 24 Aug 11 08:00:27 PM PDT 24 3786317144 ps
T861 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.4066378216 Aug 11 08:24:30 PM PDT 24 Aug 11 08:31:28 PM PDT 24 3136378752 ps
T1056 /workspace/coverage/default/2.chip_sival_flash_info_access.2090004469 Aug 11 08:02:27 PM PDT 24 Aug 11 08:07:00 PM PDT 24 2957032912 ps
T818 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1783211849 Aug 11 08:17:02 PM PDT 24 Aug 11 08:25:51 PM PDT 24 3656753490 ps
T1057 /workspace/coverage/default/1.chip_sw_otbn_smoketest.2507649845 Aug 11 08:05:35 PM PDT 24 Aug 11 08:28:31 PM PDT 24 6203347960 ps
T1058 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3638084575 Aug 11 08:11:20 PM PDT 24 Aug 11 08:30:35 PM PDT 24 7808045661 ps
T166 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2868650229 Aug 11 07:43:46 PM PDT 24 Aug 11 07:47:53 PM PDT 24 2938966690 ps
T40 /workspace/coverage/default/0.chip_sw_spi_device_tpm.1278312005 Aug 11 07:34:25 PM PDT 24 Aug 11 07:41:04 PM PDT 24 3754701913 ps
T221 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1280062762 Aug 11 08:08:58 PM PDT 24 Aug 11 09:36:42 PM PDT 24 45998919660 ps
T896 /workspace/coverage/default/27.chip_sw_all_escalation_resets.4053778822 Aug 11 08:21:00 PM PDT 24 Aug 11 08:31:21 PM PDT 24 5911519584 ps
T1059 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2824330017 Aug 11 08:14:27 PM PDT 24 Aug 11 08:21:06 PM PDT 24 7032327268 ps
T1060 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2542251706 Aug 11 07:45:13 PM PDT 24 Aug 11 07:51:08 PM PDT 24 3325542783 ps
T1061 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.726427073 Aug 11 07:37:15 PM PDT 24 Aug 11 07:47:58 PM PDT 24 4728765992 ps
T882 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1893469993 Aug 11 08:23:02 PM PDT 24 Aug 11 08:30:00 PM PDT 24 3862984514 ps
T1062 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2298155036 Aug 11 08:05:11 PM PDT 24 Aug 11 08:43:08 PM PDT 24 28815233340 ps
T361 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1513276822 Aug 11 07:34:40 PM PDT 24 Aug 11 07:44:39 PM PDT 24 6061958420 ps
T99 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1827259013 Aug 11 07:42:55 PM PDT 24 Aug 11 08:07:12 PM PDT 24 24601254950 ps
T753 /workspace/coverage/default/4.chip_sw_all_escalation_resets.863759558 Aug 11 08:16:45 PM PDT 24 Aug 11 08:27:07 PM PDT 24 5077216622 ps
T180 /workspace/coverage/default/1.chip_sw_power_virus.228115857 Aug 11 08:04:48 PM PDT 24 Aug 11 08:30:24 PM PDT 24 6075633364 ps
T1063 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.635985118 Aug 11 08:13:20 PM PDT 24 Aug 11 09:00:34 PM PDT 24 14014316872 ps
T1064 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3939641924 Aug 11 08:16:13 PM PDT 24 Aug 11 08:23:32 PM PDT 24 4320923060 ps
T1065 /workspace/coverage/default/1.rom_e2e_asm_init_dev.1516477231 Aug 11 08:04:25 PM PDT 24 Aug 11 09:08:30 PM PDT 24 15792082944 ps
T1066 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.1260928169 Aug 11 08:11:25 PM PDT 24 Aug 11 08:17:40 PM PDT 24 3882860810 ps
T1067 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3429158410 Aug 11 08:05:22 PM PDT 24 Aug 11 09:13:22 PM PDT 24 14721708711 ps
T394 /workspace/coverage/default/39.chip_sw_all_escalation_resets.2144539860 Aug 11 08:21:37 PM PDT 24 Aug 11 08:35:02 PM PDT 24 5130137746 ps
T868 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.741268646 Aug 11 08:31:34 PM PDT 24 Aug 11 08:39:41 PM PDT 24 4365072792 ps
T331 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1358717909 Aug 11 07:50:11 PM PDT 24 Aug 11 08:06:10 PM PDT 24 8520772595 ps
T1068 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.21184364 Aug 11 08:10:43 PM PDT 24 Aug 11 08:28:50 PM PDT 24 11888945944 ps
T148 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2650783300 Aug 11 07:52:04 PM PDT 24 Aug 11 07:55:03 PM PDT 24 2306858485 ps
T336 /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.3436829260 Aug 11 08:10:04 PM PDT 24 Aug 11 08:16:47 PM PDT 24 3543512120 ps
T1069 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3921260541 Aug 11 07:57:30 PM PDT 24 Aug 11 08:05:40 PM PDT 24 4080030314 ps
T1070 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1517045146 Aug 11 07:49:45 PM PDT 24 Aug 11 07:55:27 PM PDT 24 4934352560 ps
T1071 /workspace/coverage/default/0.chip_sw_otbn_randomness.1112680158 Aug 11 07:37:52 PM PDT 24 Aug 11 07:53:06 PM PDT 24 5946665776 ps
T1072 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3914581621 Aug 11 07:41:36 PM PDT 24 Aug 11 07:50:48 PM PDT 24 5319707914 ps
T1073 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1639385791 Aug 11 08:03:18 PM PDT 24 Aug 11 08:07:29 PM PDT 24 2804548808 ps
T1074 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1383086626 Aug 11 08:13:01 PM PDT 24 Aug 11 08:17:08 PM PDT 24 2423382384 ps
T348 /workspace/coverage/default/2.chip_sw_pattgen_ios.2666443353 Aug 11 08:03:02 PM PDT 24 Aug 11 08:08:05 PM PDT 24 3106701360 ps
T1075 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2638979320 Aug 11 08:12:54 PM PDT 24 Aug 11 09:14:25 PM PDT 24 22613091903 ps
T847 /workspace/coverage/default/70.chip_sw_all_escalation_resets.3814343077 Aug 11 08:23:46 PM PDT 24 Aug 11 08:34:11 PM PDT 24 3964075130 ps
T316 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1988748862 Aug 11 08:02:17 PM PDT 24 Aug 11 08:14:07 PM PDT 24 4735709112 ps
T1076 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.767197553 Aug 11 08:16:41 PM PDT 24 Aug 11 08:25:01 PM PDT 24 3954738632 ps
T1077 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3856510342 Aug 11 07:51:03 PM PDT 24 Aug 11 08:02:23 PM PDT 24 4114345288 ps
T233 /workspace/coverage/default/19.chip_sw_all_escalation_resets.3908402520 Aug 11 08:18:05 PM PDT 24 Aug 11 08:30:23 PM PDT 24 4788138920 ps
T804 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3837327593 Aug 11 08:27:22 PM PDT 24 Aug 11 08:34:32 PM PDT 24 3199473450 ps
T745 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2930801092 Aug 11 08:10:58 PM PDT 24 Aug 11 08:22:20 PM PDT 24 4438147956 ps
T365 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.966241475 Aug 11 07:54:53 PM PDT 24 Aug 11 07:59:14 PM PDT 24 2863986787 ps
T1078 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.679306246 Aug 11 07:41:16 PM PDT 24 Aug 11 07:44:51 PM PDT 24 3098242536 ps
T1079 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2753074036 Aug 11 08:08:35 PM PDT 24 Aug 11 08:14:14 PM PDT 24 4614570580 ps
T270 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.4196248157 Aug 11 07:50:53 PM PDT 24 Aug 11 08:01:43 PM PDT 24 5769885648 ps
T832 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3198592190 Aug 11 08:16:04 PM PDT 24 Aug 11 08:23:31 PM PDT 24 4106432880 ps
T1080 /workspace/coverage/default/1.chip_sw_otbn_randomness.3305785991 Aug 11 07:55:21 PM PDT 24 Aug 11 08:09:53 PM PDT 24 6121467804 ps
T167 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.4091289479 Aug 11 08:13:00 PM PDT 24 Aug 11 08:17:37 PM PDT 24 3003987081 ps
T141 /workspace/coverage/default/0.chip_plic_all_irqs_10.1834984370 Aug 11 07:44:09 PM PDT 24 Aug 11 07:53:36 PM PDT 24 3796396856 ps
T1081 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3129306656 Aug 11 08:07:52 PM PDT 24 Aug 11 09:08:31 PM PDT 24 15407275095 ps
T189 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3584672523 Aug 11 07:36:24 PM PDT 24 Aug 11 07:43:12 PM PDT 24 3206610613 ps
T1082 /workspace/coverage/default/2.chip_sw_aon_timer_irq.2670454666 Aug 11 08:07:15 PM PDT 24 Aug 11 08:13:55 PM PDT 24 4120774680 ps
T1083 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3631253948 Aug 11 08:08:09 PM PDT 24 Aug 11 08:26:41 PM PDT 24 7505524232 ps
T1084 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2478449202 Aug 11 08:08:55 PM PDT 24 Aug 11 08:24:16 PM PDT 24 9221848902 ps
T50 /workspace/coverage/default/0.chip_sw_alert_test.4106852054 Aug 11 07:38:48 PM PDT 24 Aug 11 07:43:46 PM PDT 24 3065649098 ps
T839 /workspace/coverage/default/51.chip_sw_all_escalation_resets.2051649024 Aug 11 08:22:08 PM PDT 24 Aug 11 08:33:39 PM PDT 24 4655458000 ps
T1085 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.4114845081 Aug 11 07:35:28 PM PDT 24 Aug 11 07:45:48 PM PDT 24 3811530008 ps
T877 /workspace/coverage/default/32.chip_sw_all_escalation_resets.2821608100 Aug 11 08:19:49 PM PDT 24 Aug 11 08:29:22 PM PDT 24 5898586840 ps
T1086 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1597213439 Aug 11 07:55:43 PM PDT 24 Aug 11 07:59:18 PM PDT 24 3435965404 ps
T1087 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.1632164295 Aug 11 07:37:16 PM PDT 24 Aug 11 07:47:26 PM PDT 24 4926610724 ps
T1088 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2317260211 Aug 11 07:53:41 PM PDT 24 Aug 11 08:58:47 PM PDT 24 14503664072 ps
T340 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1296099364 Aug 11 08:00:11 PM PDT 24 Aug 11 08:11:10 PM PDT 24 4667074013 ps
T1089 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.2555596202 Aug 11 07:53:38 PM PDT 24 Aug 11 08:01:26 PM PDT 24 4290706440 ps
T842 /workspace/coverage/default/95.chip_sw_all_escalation_resets.406823494 Aug 11 08:27:57 PM PDT 24 Aug 11 08:35:58 PM PDT 24 4388228948 ps
T849 /workspace/coverage/default/8.chip_sw_all_escalation_resets.3246294264 Aug 11 08:15:54 PM PDT 24 Aug 11 08:22:39 PM PDT 24 4889856576 ps
T314 /workspace/coverage/default/2.chip_plic_all_irqs_20.1847850585 Aug 11 08:08:58 PM PDT 24 Aug 11 08:20:39 PM PDT 24 4559461560 ps
T1090 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.739379639 Aug 11 07:51:51 PM PDT 24 Aug 11 08:02:44 PM PDT 24 4545330052 ps
T123 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3473786518 Aug 11 07:56:32 PM PDT 24 Aug 11 08:12:45 PM PDT 24 10153300374 ps
T1091 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1253188459 Aug 11 07:34:23 PM PDT 24 Aug 11 07:55:05 PM PDT 24 7714920652 ps
T1092 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3035727127 Aug 11 08:07:09 PM PDT 24 Aug 11 08:42:14 PM PDT 24 10119041488 ps
T1093 /workspace/coverage/default/0.chip_sw_kmac_idle.1700771719 Aug 11 07:39:58 PM PDT 24 Aug 11 07:44:06 PM PDT 24 2202034240 ps
T412 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2704072944 Aug 11 08:09:41 PM PDT 24 Aug 11 08:18:04 PM PDT 24 6857535708 ps
T1094 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.80228912 Aug 11 07:57:10 PM PDT 24 Aug 11 09:18:57 PM PDT 24 20197623520 ps
T862 /workspace/coverage/default/84.chip_sw_all_escalation_resets.3382112558 Aug 11 08:25:14 PM PDT 24 Aug 11 08:38:27 PM PDT 24 5275953340 ps
T366 /workspace/coverage/default/1.chip_sw_hmac_enc.909276231 Aug 11 07:55:55 PM PDT 24 Aug 11 08:00:25 PM PDT 24 3154443158 ps
T22 /workspace/coverage/default/0.chip_sw_usbdev_stream.4132899101 Aug 11 07:34:49 PM PDT 24 Aug 11 09:05:46 PM PDT 24 18829281588 ps
T131 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3417992967 Aug 11 07:35:58 PM PDT 24 Aug 11 07:43:14 PM PDT 24 8395785488 ps
T193 /workspace/coverage/default/0.chip_sw_gpio_smoketest.3354679587 Aug 11 07:49:06 PM PDT 24 Aug 11 07:52:38 PM PDT 24 2300729662 ps
T1095 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1468804889 Aug 11 07:35:29 PM PDT 24 Aug 11 07:52:01 PM PDT 24 7628005132 ps
T289 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2307022824 Aug 11 07:43:51 PM PDT 24 Aug 11 07:48:37 PM PDT 24 3086911635 ps
T215 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.219891527 Aug 11 08:08:48 PM PDT 24 Aug 11 09:14:20 PM PDT 24 17050490550 ps
T25 /workspace/coverage/default/1.chip_sw_gpio.279451375 Aug 11 07:53:21 PM PDT 24 Aug 11 08:02:22 PM PDT 24 3945589518 ps
T168 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3512951381 Aug 11 08:03:10 PM PDT 24 Aug 11 09:32:24 PM PDT 24 44589709038 ps
T1096 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3874056516 Aug 11 07:55:17 PM PDT 24 Aug 11 08:15:42 PM PDT 24 6408935007 ps
T332 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2764929049 Aug 11 07:51:41 PM PDT 24 Aug 11 08:02:40 PM PDT 24 4272074530 ps
T1097 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1132014612 Aug 11 07:51:15 PM PDT 24 Aug 11 08:44:18 PM PDT 24 11364573496 ps
T241 /workspace/coverage/default/2.chip_sw_plic_sw_irq.3120104008 Aug 11 08:09:59 PM PDT 24 Aug 11 08:14:54 PM PDT 24 2657246984 ps
T1098 /workspace/coverage/default/2.chip_sw_uart_smoketest.915670305 Aug 11 08:14:54 PM PDT 24 Aug 11 08:18:48 PM PDT 24 2646371010 ps
T756 /workspace/coverage/default/0.chip_sw_power_idle_load.2631375061 Aug 11 07:44:41 PM PDT 24 Aug 11 07:53:53 PM PDT 24 4712659464 ps
T320 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2394436185 Aug 11 07:34:45 PM PDT 24 Aug 11 07:46:20 PM PDT 24 4748203410 ps
T1099 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1186471694 Aug 11 08:15:44 PM PDT 24 Aug 11 08:58:37 PM PDT 24 13352173495 ps
T1100 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.895997721 Aug 11 07:58:47 PM PDT 24 Aug 11 08:18:41 PM PDT 24 7526843526 ps
T1101 /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3575039838 Aug 11 08:04:30 PM PDT 24 Aug 12 12:03:15 AM PDT 24 78892272415 ps
T1102 /workspace/coverage/default/2.chip_sw_aes_entropy.501347876 Aug 11 08:08:08 PM PDT 24 Aug 11 08:12:44 PM PDT 24 2989133880 ps
T857 /workspace/coverage/default/60.chip_sw_all_escalation_resets.1552390322 Aug 11 08:23:27 PM PDT 24 Aug 11 08:32:22 PM PDT 24 4902492888 ps
T1103 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2859806244 Aug 11 08:08:15 PM PDT 24 Aug 11 08:39:46 PM PDT 24 7582236408 ps
T190 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.4224355641 Aug 11 07:38:21 PM PDT 24 Aug 11 08:12:33 PM PDT 24 23722087224 ps
T1104 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3533560967 Aug 11 08:02:32 PM PDT 24 Aug 11 08:12:00 PM PDT 24 4213083026 ps
T236 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.24921180 Aug 11 08:23:05 PM PDT 24 Aug 11 08:28:54 PM PDT 24 3920473390 ps
T281 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3210956802 Aug 11 07:57:45 PM PDT 24 Aug 11 08:02:05 PM PDT 24 3309111704 ps
T282 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.4064309453 Aug 11 08:15:01 PM PDT 24 Aug 11 08:23:58 PM PDT 24 4714615528 ps
T283 /workspace/coverage/default/2.rom_e2e_self_hash.2453261191 Aug 11 08:17:41 PM PDT 24 Aug 11 09:49:48 PM PDT 24 26420089456 ps
T284 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.3516106672 Aug 11 07:52:59 PM PDT 24 Aug 11 07:59:29 PM PDT 24 6540004266 ps
T285 /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.437905411 Aug 11 08:14:57 PM PDT 24 Aug 11 08:35:27 PM PDT 24 10130444232 ps
T286 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3633705204 Aug 11 08:15:50 PM PDT 24 Aug 11 08:30:50 PM PDT 24 9882650808 ps
T287 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2330509367 Aug 11 08:23:44 PM PDT 24 Aug 11 08:30:19 PM PDT 24 4415965660 ps
T288 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1314745257 Aug 11 08:11:51 PM PDT 24 Aug 11 08:16:10 PM PDT 24 3353366009 ps
T222 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1103148300 Aug 11 07:34:38 PM PDT 24 Aug 11 09:11:56 PM PDT 24 49608870898 ps
T248 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1313777816 Aug 11 08:10:08 PM PDT 24 Aug 11 08:17:34 PM PDT 24 5277162168 ps
T1105 /workspace/coverage/default/0.chip_sw_edn_auto_mode.1636255573 Aug 11 07:39:14 PM PDT 24 Aug 11 07:54:27 PM PDT 24 4251108340 ps
T319 /workspace/coverage/default/0.chip_plic_all_irqs_20.2116303805 Aug 11 07:40:40 PM PDT 24 Aug 11 07:51:52 PM PDT 24 3963627064 ps
T352 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.4193192205 Aug 11 07:56:19 PM PDT 24 Aug 11 08:00:13 PM PDT 24 3105329544 ps
T395 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.2937722242 Aug 11 07:56:29 PM PDT 24 Aug 11 08:04:44 PM PDT 24 8620349325 ps
T883 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2679602639 Aug 11 08:14:55 PM PDT 24 Aug 11 08:22:08 PM PDT 24 3384890920 ps
T850 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.350684244 Aug 11 07:54:13 PM PDT 24 Aug 11 08:00:52 PM PDT 24 3669607830 ps
T878 /workspace/coverage/default/42.chip_sw_all_escalation_resets.2429644814 Aug 11 08:21:31 PM PDT 24 Aug 11 08:35:11 PM PDT 24 5600402984 ps
T864 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3222523766 Aug 11 08:23:42 PM PDT 24 Aug 11 08:30:51 PM PDT 24 3430267634 ps
T181 /workspace/coverage/default/2.chip_sw_power_virus.977977292 Aug 11 08:17:26 PM PDT 24 Aug 11 08:43:14 PM PDT 24 5879368584 ps
T836 /workspace/coverage/default/85.chip_sw_all_escalation_resets.3722320553 Aug 11 08:33:35 PM PDT 24 Aug 11 08:45:01 PM PDT 24 6340657828 ps
T801 /workspace/coverage/default/69.chip_sw_all_escalation_resets.983870268 Aug 11 08:24:35 PM PDT 24 Aug 11 08:34:03 PM PDT 24 4438939104 ps
T894 /workspace/coverage/default/46.chip_sw_all_escalation_resets.384769550 Aug 11 08:20:50 PM PDT 24 Aug 11 08:29:28 PM PDT 24 5890511368 ps
T358 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2445156941 Aug 11 07:50:51 PM PDT 24 Aug 11 08:05:47 PM PDT 24 5616474576 ps
T1106 /workspace/coverage/default/0.chip_sw_edn_sw_mode.3093588988 Aug 11 07:38:09 PM PDT 24 Aug 11 08:03:09 PM PDT 24 7478728962 ps
T1107 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.3133844369 Aug 11 07:36:04 PM PDT 24 Aug 11 08:22:48 PM PDT 24 28466836185 ps
T1108 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.507511199 Aug 11 07:50:50 PM PDT 24 Aug 11 11:01:06 PM PDT 24 64817705032 ps
T1109 /workspace/coverage/default/0.rom_e2e_self_hash.1447025606 Aug 11 07:55:32 PM PDT 24 Aug 11 09:41:59 PM PDT 24 27367224000 ps
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