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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.01 95.47 93.71 95.33 94.52 97.53 99.51


Total test records in report: 2938
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T1259 /workspace/coverage/default/2.rom_volatile_raw_unlock.3350312585 Aug 11 08:14:36 PM PDT 24 Aug 11 08:16:31 PM PDT 24 1769124394 ps
T1260 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2484260639 Aug 11 08:04:05 PM PDT 24 Aug 11 08:07:13 PM PDT 24 2448327876 ps
T1261 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1164962036 Aug 11 07:36:09 PM PDT 24 Aug 11 07:43:40 PM PDT 24 5159856555 ps
T184 /workspace/coverage/default/1.chip_jtag_mem_access.1902969970 Aug 11 07:50:35 PM PDT 24 Aug 11 08:12:23 PM PDT 24 14072708468 ps
T1262 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3959993722 Aug 11 08:10:20 PM PDT 24 Aug 11 08:20:22 PM PDT 24 5677872822 ps
T1263 /workspace/coverage/default/1.rom_e2e_asm_init_prod.2072683908 Aug 11 08:08:07 PM PDT 24 Aug 11 09:17:35 PM PDT 24 15934483504 ps
T1264 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2400345367 Aug 11 07:35:58 PM PDT 24 Aug 11 07:43:58 PM PDT 24 6874669400 ps
T1265 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1351505777 Aug 11 07:40:04 PM PDT 24 Aug 11 07:47:23 PM PDT 24 4576208676 ps
T1266 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.4045309368 Aug 11 07:55:32 PM PDT 24 Aug 11 08:22:45 PM PDT 24 6885838992 ps
T291 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.443813612 Aug 11 08:10:47 PM PDT 24 Aug 11 08:15:17 PM PDT 24 3329117780 ps
T1267 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1236414165 Aug 11 07:34:07 PM PDT 24 Aug 11 07:52:18 PM PDT 24 6399739044 ps
T1268 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3555697807 Aug 11 07:55:07 PM PDT 24 Aug 11 11:26:23 PM PDT 24 255972936620 ps
T1269 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1703996656 Aug 11 08:20:20 PM PDT 24 Aug 11 08:27:21 PM PDT 24 3353667040 ps
T322 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2906978466 Aug 11 08:04:06 PM PDT 24 Aug 11 08:33:53 PM PDT 24 10507793416 ps
T317 /workspace/coverage/default/1.chip_plic_all_irqs_0.2562905223 Aug 11 07:57:58 PM PDT 24 Aug 11 08:19:31 PM PDT 24 6451660492 ps
T773 /workspace/coverage/default/2.chip_sw_power_sleep_load.1642828789 Aug 11 08:13:13 PM PDT 24 Aug 11 08:21:48 PM PDT 24 4304857312 ps
T1270 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3143045870 Aug 11 07:33:46 PM PDT 24 Aug 11 07:42:28 PM PDT 24 4413292778 ps
T1271 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2679088423 Aug 11 07:53:26 PM PDT 24 Aug 11 08:06:50 PM PDT 24 7844600788 ps
T1272 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3468316404 Aug 11 08:25:04 PM PDT 24 Aug 11 08:31:20 PM PDT 24 3946132406 ps
T1273 /workspace/coverage/default/2.rom_e2e_shutdown_output.3656308630 Aug 11 08:18:28 PM PDT 24 Aug 11 09:11:56 PM PDT 24 22724297936 ps
T1274 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2859463103 Aug 11 07:34:59 PM PDT 24 Aug 11 07:47:10 PM PDT 24 9880127476 ps
T853 /workspace/coverage/default/52.chip_sw_all_escalation_resets.201431848 Aug 11 08:23:10 PM PDT 24 Aug 11 08:34:29 PM PDT 24 5596804304 ps
T1275 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.2082209312 Aug 11 07:56:22 PM PDT 24 Aug 11 08:05:58 PM PDT 24 4756396080 ps
T1276 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.4080354018 Aug 11 07:42:48 PM PDT 24 Aug 11 08:32:39 PM PDT 24 12611151250 ps
T1277 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2857247910 Aug 11 08:21:54 PM PDT 24 Aug 11 08:30:05 PM PDT 24 3721914204 ps
T1278 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2987561867 Aug 11 08:03:45 PM PDT 24 Aug 11 08:14:08 PM PDT 24 4505857856 ps
T1279 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.4110708460 Aug 11 08:16:45 PM PDT 24 Aug 11 09:00:59 PM PDT 24 13798223260 ps
T1280 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3454929368 Aug 11 08:07:01 PM PDT 24 Aug 11 08:26:16 PM PDT 24 11030313484 ps
T1281 /workspace/coverage/default/2.chip_tap_straps_testunlock0.1872032588 Aug 11 08:12:14 PM PDT 24 Aug 11 08:20:55 PM PDT 24 5329411728 ps
T1282 /workspace/coverage/default/1.chip_tap_straps_dev.948109821 Aug 11 07:57:54 PM PDT 24 Aug 11 08:15:36 PM PDT 24 9916293757 ps
T1283 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1431079058 Aug 11 08:09:19 PM PDT 24 Aug 11 08:18:12 PM PDT 24 9961192442 ps
T1284 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3682328570 Aug 11 07:56:33 PM PDT 24 Aug 11 08:37:54 PM PDT 24 12116095516 ps
T746 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.434257547 Aug 11 07:42:47 PM PDT 24 Aug 11 07:50:45 PM PDT 24 4758862042 ps
T783 /workspace/coverage/default/0.rom_raw_unlock.3632125498 Aug 11 07:51:17 PM PDT 24 Aug 11 07:55:16 PM PDT 24 6037254531 ps
T1285 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.663968504 Aug 11 07:55:57 PM PDT 24 Aug 11 08:00:27 PM PDT 24 2625715270 ps
T1286 /workspace/coverage/default/2.chip_tap_straps_rma.2364290680 Aug 11 08:10:23 PM PDT 24 Aug 11 08:14:50 PM PDT 24 3870492318 ps
T1287 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.2443167671 Aug 11 08:16:13 PM PDT 24 Aug 11 08:29:04 PM PDT 24 4428392856 ps
T437 /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.783587597 Aug 11 07:49:17 PM PDT 24 Aug 11 08:50:41 PM PDT 24 24769826809 ps
T1288 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.3444813174 Aug 11 08:03:53 PM PDT 24 Aug 11 08:32:44 PM PDT 24 7420508544 ps
T1289 /workspace/coverage/default/93.chip_sw_all_escalation_resets.1425856539 Aug 11 08:25:14 PM PDT 24 Aug 11 08:37:19 PM PDT 24 5264706760 ps
T1290 /workspace/coverage/default/34.chip_sw_all_escalation_resets.2980665114 Aug 11 08:25:05 PM PDT 24 Aug 11 08:35:31 PM PDT 24 5536583656 ps
T1291 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.249373117 Aug 11 07:40:51 PM PDT 24 Aug 11 08:05:15 PM PDT 24 17422305355 ps
T1292 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.3963477387 Aug 11 07:53:21 PM PDT 24 Aug 11 08:00:14 PM PDT 24 3711076940 ps
T1293 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.4045883077 Aug 11 07:36:21 PM PDT 24 Aug 11 07:39:45 PM PDT 24 2699604232 ps
T1294 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1680223733 Aug 11 07:54:09 PM PDT 24 Aug 11 08:00:45 PM PDT 24 4859924138 ps
T1295 /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.966334494 Aug 11 07:38:57 PM PDT 24 Aug 11 08:03:49 PM PDT 24 8090090552 ps
T546 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.4167602943 Aug 11 07:58:11 PM PDT 24 Aug 11 08:06:52 PM PDT 24 4191217320 ps
T1296 /workspace/coverage/default/1.chip_sw_power_idle_load.750288239 Aug 11 08:03:43 PM PDT 24 Aug 11 08:13:52 PM PDT 24 4483683284 ps
T1297 /workspace/coverage/default/76.chip_sw_all_escalation_resets.763806001 Aug 11 08:24:01 PM PDT 24 Aug 11 08:34:09 PM PDT 24 4706220274 ps
T1298 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1725388161 Aug 11 07:36:50 PM PDT 24 Aug 11 07:55:01 PM PDT 24 8964166120 ps
T1299 /workspace/coverage/default/1.chip_sw_aes_entropy.116039542 Aug 11 07:56:38 PM PDT 24 Aug 11 08:00:36 PM PDT 24 2916457570 ps
T1300 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.2854692028 Aug 11 08:06:24 PM PDT 24 Aug 11 08:24:32 PM PDT 24 5270043332 ps
T1301 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3665667091 Aug 11 07:39:15 PM PDT 24 Aug 11 07:41:26 PM PDT 24 3272636959 ps
T1302 /workspace/coverage/default/1.chip_sw_aes_masking_off.3577798107 Aug 11 07:54:38 PM PDT 24 Aug 11 08:00:09 PM PDT 24 3222569666 ps
T398 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.281633153 Aug 11 08:11:27 PM PDT 24 Aug 11 08:19:45 PM PDT 24 4199001128 ps
T547 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3508590974 Aug 11 08:10:07 PM PDT 24 Aug 11 08:19:57 PM PDT 24 4709657558 ps
T1303 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1700183371 Aug 11 07:55:44 PM PDT 24 Aug 11 09:38:40 PM PDT 24 18620875190 ps
T1304 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.682752829 Aug 11 07:42:53 PM PDT 24 Aug 11 07:53:59 PM PDT 24 5241322876 ps
T890 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2958037387 Aug 11 08:18:43 PM PDT 24 Aug 11 08:24:40 PM PDT 24 4199571810 ps
T1305 /workspace/coverage/default/2.chip_sw_aes_enc.1885539513 Aug 11 08:07:03 PM PDT 24 Aug 11 08:11:44 PM PDT 24 2761803442 ps
T321 /workspace/coverage/default/2.chip_plic_all_irqs_0.3189075814 Aug 11 08:10:25 PM PDT 24 Aug 11 08:28:58 PM PDT 24 6666510700 ps
T1306 /workspace/coverage/default/3.chip_tap_straps_dev.2102119702 Aug 11 08:14:50 PM PDT 24 Aug 11 08:40:08 PM PDT 24 11194601306 ps
T133 /workspace/coverage/default/2.chip_jtag_csr_rw.2567866230 Aug 11 08:03:32 PM PDT 24 Aug 11 08:09:25 PM PDT 24 4047761022 ps
T1307 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3473032966 Aug 11 07:34:57 PM PDT 24 Aug 11 07:49:57 PM PDT 24 6449734666 ps
T1308 /workspace/coverage/default/0.chip_sw_flash_crash_alert.2813577924 Aug 11 07:45:39 PM PDT 24 Aug 11 07:57:17 PM PDT 24 6301171422 ps
T182 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.4013610565 Aug 11 08:02:47 PM PDT 24 Aug 11 08:12:06 PM PDT 24 4144182281 ps
T1309 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1436272106 Aug 11 07:52:15 PM PDT 24 Aug 11 09:07:08 PM PDT 24 15623648280 ps
T1310 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2109940544 Aug 11 07:51:02 PM PDT 24 Aug 11 08:04:53 PM PDT 24 5579916473 ps
T1311 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3386364963 Aug 11 08:09:40 PM PDT 24 Aug 11 08:21:45 PM PDT 24 4537221108 ps
T1312 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2112064576 Aug 11 07:36:08 PM PDT 24 Aug 11 07:48:22 PM PDT 24 5975655952 ps
T1313 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.4225435431 Aug 11 08:11:24 PM PDT 24 Aug 11 08:22:08 PM PDT 24 4628182900 ps
T1314 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1603320019 Aug 11 07:39:21 PM PDT 24 Aug 11 08:26:35 PM PDT 24 12753281254 ps
T1315 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.747843820 Aug 11 08:18:10 PM PDT 24 Aug 11 08:45:31 PM PDT 24 7642692916 ps
T1316 /workspace/coverage/default/73.chip_sw_all_escalation_resets.1875899181 Aug 11 08:29:19 PM PDT 24 Aug 11 08:39:26 PM PDT 24 4614093304 ps
T1317 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3264695854 Aug 11 08:01:24 PM PDT 24 Aug 11 08:05:23 PM PDT 24 2870430200 ps
T1318 /workspace/coverage/default/2.chip_tap_straps_prod.2097712365 Aug 11 08:10:27 PM PDT 24 Aug 11 08:30:34 PM PDT 24 11389480469 ps
T1319 /workspace/coverage/default/1.chip_sw_aes_smoketest.3379860082 Aug 11 08:01:28 PM PDT 24 Aug 11 08:07:33 PM PDT 24 3479860790 ps
T1320 /workspace/coverage/default/1.chip_sw_csrng_kat_test.704465313 Aug 11 07:55:37 PM PDT 24 Aug 11 07:59:55 PM PDT 24 2216846760 ps
T893 /workspace/coverage/default/31.chip_sw_all_escalation_resets.3762617235 Aug 11 08:24:42 PM PDT 24 Aug 11 08:38:22 PM PDT 24 5847283690 ps
T1321 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2921061886 Aug 11 07:52:27 PM PDT 24 Aug 11 08:53:23 PM PDT 24 14755583002 ps
T1322 /workspace/coverage/default/22.chip_sw_all_escalation_resets.1910052415 Aug 11 08:18:46 PM PDT 24 Aug 11 08:31:51 PM PDT 24 4791999968 ps
T1323 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2032924975 Aug 11 07:49:34 PM PDT 24 Aug 11 07:57:32 PM PDT 24 3453477190 ps
T764 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3993081631 Aug 11 08:05:21 PM PDT 24 Aug 11 08:08:29 PM PDT 24 2871834232 ps
T1324 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.41147049 Aug 11 07:51:13 PM PDT 24 Aug 11 09:09:32 PM PDT 24 15799342572 ps
T1325 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3509346748 Aug 11 08:03:09 PM PDT 24 Aug 11 08:13:20 PM PDT 24 4658769380 ps
T334 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.4280349990 Aug 11 07:35:02 PM PDT 24 Aug 11 07:45:31 PM PDT 24 4492117160 ps
T1326 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1973047341 Aug 11 07:53:09 PM PDT 24 Aug 11 08:03:36 PM PDT 24 19044196814 ps
T1327 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3383544186 Aug 11 07:51:51 PM PDT 24 Aug 11 09:37:54 PM PDT 24 23344783560 ps
T1328 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.298858505 Aug 11 08:14:09 PM PDT 24 Aug 11 08:26:42 PM PDT 24 4027009579 ps
T808 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.41412385 Aug 11 07:37:40 PM PDT 24 Aug 11 07:42:49 PM PDT 24 3533593808 ps
T413 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1051481829 Aug 11 08:11:21 PM PDT 24 Aug 11 08:34:50 PM PDT 24 20184235110 ps
T1329 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3783147862 Aug 11 07:34:39 PM PDT 24 Aug 11 07:52:29 PM PDT 24 5692854401 ps
T1330 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3790077243 Aug 11 07:42:44 PM PDT 24 Aug 11 07:58:22 PM PDT 24 9939806634 ps
T1331 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3652495990 Aug 11 07:37:52 PM PDT 24 Aug 11 07:45:43 PM PDT 24 4678069746 ps
T1332 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.950796318 Aug 11 07:33:43 PM PDT 24 Aug 11 11:30:35 PM PDT 24 79020674472 ps
T843 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3479958719 Aug 11 08:25:09 PM PDT 24 Aug 11 08:32:17 PM PDT 24 3840957300 ps
T834 /workspace/coverage/default/92.chip_sw_all_escalation_resets.3955013866 Aug 11 08:25:34 PM PDT 24 Aug 11 08:36:22 PM PDT 24 5335523856 ps
T1333 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1560627007 Aug 11 07:38:06 PM PDT 24 Aug 11 07:55:18 PM PDT 24 5798777044 ps
T1334 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.3270468196 Aug 11 07:53:37 PM PDT 24 Aug 11 08:00:33 PM PDT 24 5170727352 ps
T1335 /workspace/coverage/default/0.chip_sw_hmac_multistream.29455101 Aug 11 07:38:22 PM PDT 24 Aug 11 08:04:29 PM PDT 24 7630883944 ps
T226 /workspace/coverage/default/0.chip_sw_flash_init.2874497439 Aug 11 07:34:12 PM PDT 24 Aug 11 08:06:51 PM PDT 24 22184584014 ps
T1336 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3378531328 Aug 11 07:39:53 PM PDT 24 Aug 11 08:14:47 PM PDT 24 8192696060 ps
T255 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.661958817 Aug 11 07:38:55 PM PDT 24 Aug 11 07:48:34 PM PDT 24 5625238174 ps
T1337 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.947978329 Aug 11 08:08:01 PM PDT 24 Aug 11 08:31:19 PM PDT 24 8328739192 ps
T1338 /workspace/coverage/default/0.chip_sw_kmac_app_rom.3223937886 Aug 11 07:39:47 PM PDT 24 Aug 11 07:44:36 PM PDT 24 3249758006 ps
T859 /workspace/coverage/default/86.chip_sw_all_escalation_resets.1355713808 Aug 11 08:25:49 PM PDT 24 Aug 11 08:36:59 PM PDT 24 4691540020 ps
T1339 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1463868910 Aug 11 07:39:51 PM PDT 24 Aug 11 07:43:02 PM PDT 24 2860296436 ps
T872 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1828903141 Aug 11 08:17:19 PM PDT 24 Aug 11 08:23:18 PM PDT 24 3414152702 ps
T338 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3001484973 Aug 11 07:57:50 PM PDT 24 Aug 11 08:03:48 PM PDT 24 2898438896 ps
T1340 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.785980201 Aug 11 07:41:16 PM PDT 24 Aug 11 07:44:54 PM PDT 24 3029020864 ps
T747 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.4215769535 Aug 11 07:57:44 PM PDT 24 Aug 11 08:06:22 PM PDT 24 4342025198 ps
T1341 /workspace/coverage/default/2.chip_sw_example_flash.2925021412 Aug 11 08:04:54 PM PDT 24 Aug 11 08:08:54 PM PDT 24 2532877048 ps
T1342 /workspace/coverage/default/0.rom_e2e_shutdown_output.1961862465 Aug 11 07:50:34 PM PDT 24 Aug 11 08:59:53 PM PDT 24 27432097197 ps
T1343 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.3654778067 Aug 11 07:45:21 PM PDT 24 Aug 11 07:49:49 PM PDT 24 3511457305 ps
T1344 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1834272377 Aug 11 07:52:15 PM PDT 24 Aug 11 08:38:26 PM PDT 24 28303301016 ps
T1345 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3576185664 Aug 11 08:11:53 PM PDT 24 Aug 11 08:15:15 PM PDT 24 2358704892 ps
T1346 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.4187011192 Aug 11 08:18:03 PM PDT 24 Aug 11 08:30:07 PM PDT 24 4587378600 ps
T1347 /workspace/coverage/default/4.chip_tap_straps_rma.1187131631 Aug 11 08:14:58 PM PDT 24 Aug 11 08:18:56 PM PDT 24 3447099912 ps
T1348 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3509825105 Aug 11 07:38:42 PM PDT 24 Aug 11 07:53:47 PM PDT 24 5470774708 ps
T1349 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.883024651 Aug 11 07:52:42 PM PDT 24 Aug 11 08:02:49 PM PDT 24 5071891874 ps
T1350 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2093808849 Aug 11 08:01:31 PM PDT 24 Aug 11 08:07:21 PM PDT 24 5065107324 ps
T1351 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3757572123 Aug 11 07:45:05 PM PDT 24 Aug 11 09:26:19 PM PDT 24 26752699320 ps
T886 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2153042430 Aug 11 08:20:49 PM PDT 24 Aug 11 08:28:51 PM PDT 24 3690005010 ps
T825 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1107526846 Aug 11 08:23:41 PM PDT 24 Aug 11 08:32:01 PM PDT 24 4222846550 ps
T1352 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2346640820 Aug 11 08:15:34 PM PDT 24 Aug 11 08:28:13 PM PDT 24 7861158701 ps
T1353 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.161704915 Aug 11 07:54:37 PM PDT 24 Aug 11 08:16:22 PM PDT 24 7559226196 ps
T152 /workspace/coverage/default/3.chip_sw_all_escalation_resets.3860245778 Aug 11 08:13:19 PM PDT 24 Aug 11 08:23:21 PM PDT 24 5704526810 ps
T1354 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.696022210 Aug 11 07:56:20 PM PDT 24 Aug 11 08:04:55 PM PDT 24 3567100542 ps
T1355 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.111194686 Aug 11 07:37:15 PM PDT 24 Aug 11 07:46:59 PM PDT 24 5179249585 ps
T809 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3787325172 Aug 11 08:22:30 PM PDT 24 Aug 11 08:29:44 PM PDT 24 3235906082 ps
T545 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.655673102 Aug 11 08:09:33 PM PDT 24 Aug 11 08:20:55 PM PDT 24 4469906071 ps
T1356 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2323294470 Aug 11 07:34:34 PM PDT 24 Aug 11 08:01:01 PM PDT 24 8535183808 ps
T38 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.783197593 Aug 11 07:36:31 PM PDT 24 Aug 11 07:43:30 PM PDT 24 5844206680 ps
T1357 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1389678712 Aug 11 08:11:21 PM PDT 24 Aug 11 08:20:56 PM PDT 24 4204178040 ps
T1358 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.567903222 Aug 11 07:38:16 PM PDT 24 Aug 11 11:22:31 PM PDT 24 255201351992 ps
T1359 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1329854347 Aug 11 08:16:46 PM PDT 24 Aug 11 08:45:08 PM PDT 24 9405642964 ps
T307 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3227918680 Aug 11 08:16:29 PM PDT 24 Aug 11 08:25:50 PM PDT 24 3816388844 ps
T1360 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1424714569 Aug 11 08:01:20 PM PDT 24 Aug 11 08:09:41 PM PDT 24 4454202656 ps
T154 /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.992692082 Aug 11 07:56:47 PM PDT 24 Aug 11 08:02:19 PM PDT 24 5205325252 ps
T1361 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.1000270171 Aug 11 07:40:13 PM PDT 24 Aug 11 07:57:12 PM PDT 24 8690378454 ps
T1362 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3928331192 Aug 11 07:53:20 PM PDT 24 Aug 11 08:18:28 PM PDT 24 14773051320 ps
T1363 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.1763921498 Aug 11 07:52:26 PM PDT 24 Aug 11 07:56:14 PM PDT 24 2868373784 ps
T887 /workspace/coverage/default/10.chip_sw_all_escalation_resets.1203980268 Aug 11 08:17:54 PM PDT 24 Aug 11 08:30:37 PM PDT 24 5600262896 ps
T125 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1285343524 Aug 11 07:39:28 PM PDT 24 Aug 11 07:47:33 PM PDT 24 4743881770 ps
T1364 /workspace/coverage/default/0.chip_sw_uart_tx_rx.3664811005 Aug 11 07:37:33 PM PDT 24 Aug 11 07:48:31 PM PDT 24 3987391840 ps
T870 /workspace/coverage/default/82.chip_sw_all_escalation_resets.4121805506 Aug 11 08:24:27 PM PDT 24 Aug 11 08:32:44 PM PDT 24 5544347388 ps
T1365 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.2494650403 Aug 11 07:52:21 PM PDT 24 Aug 11 07:59:10 PM PDT 24 3360897560 ps
T300 /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2571804100 Aug 11 07:57:31 PM PDT 24 Aug 11 08:08:49 PM PDT 24 4318584792 ps
T1366 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.4014501291 Aug 11 08:07:48 PM PDT 24 Aug 11 08:11:53 PM PDT 24 3180712060 ps
T876 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1649907163 Aug 11 08:21:30 PM PDT 24 Aug 11 08:28:57 PM PDT 24 4579042560 ps
T98 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.2428568183 Aug 11 08:04:17 PM PDT 24 Aug 11 08:09:29 PM PDT 24 2963262204 ps
T347 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.3988930452 Aug 11 08:03:02 PM PDT 24 Aug 11 08:14:30 PM PDT 24 5096184184 ps
T418 /workspace/coverage/default/40.chip_sw_all_escalation_resets.251078757 Aug 11 08:21:44 PM PDT 24 Aug 11 08:32:58 PM PDT 24 5749875000 ps
T419 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.805536769 Aug 11 07:52:03 PM PDT 24 Aug 11 08:00:10 PM PDT 24 8856876916 ps
T420 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1011107345 Aug 11 07:38:29 PM PDT 24 Aug 11 08:40:26 PM PDT 24 21042111602 ps
T421 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.4268036639 Aug 11 08:01:20 PM PDT 24 Aug 11 08:09:46 PM PDT 24 6341739152 ps
T422 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2458249700 Aug 11 08:08:47 PM PDT 24 Aug 11 11:32:52 PM PDT 24 255201954604 ps
T423 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2864213413 Aug 11 08:25:48 PM PDT 24 Aug 11 08:32:14 PM PDT 24 3991758264 ps
T424 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.208721783 Aug 11 08:04:17 PM PDT 24 Aug 11 08:08:03 PM PDT 24 2980402860 ps
T425 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.2021019651 Aug 11 07:51:33 PM PDT 24 Aug 11 09:25:57 PM PDT 24 49588382549 ps
T1367 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.626561315 Aug 11 07:36:15 PM PDT 24 Aug 11 08:21:39 PM PDT 24 20702511468 ps
T1368 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2852241021 Aug 11 07:52:16 PM PDT 24 Aug 11 08:43:46 PM PDT 24 11122884310 ps
T55 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.22260587 Aug 11 07:50:02 PM PDT 24 Aug 11 07:53:45 PM PDT 24 2483250508 ps
T216 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.3871500312 Aug 11 07:55:45 PM PDT 24 Aug 11 09:08:41 PM PDT 24 13832122456 ps
T402 /workspace/coverage/default/38.chip_sw_all_escalation_resets.4265387514 Aug 11 08:22:08 PM PDT 24 Aug 11 08:33:03 PM PDT 24 5451784768 ps
T403 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.38713373 Aug 11 07:51:25 PM PDT 24 Aug 11 09:45:10 PM PDT 24 23063120108 ps
T404 /workspace/coverage/default/2.rom_e2e_asm_init_dev.3846846740 Aug 11 08:18:02 PM PDT 24 Aug 11 09:32:00 PM PDT 24 14748052361 ps
T35 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.3678391766 Aug 11 07:33:47 PM PDT 24 Aug 11 07:37:09 PM PDT 24 3250369736 ps
T405 /workspace/coverage/default/53.chip_sw_all_escalation_resets.2878131151 Aug 11 08:23:22 PM PDT 24 Aug 11 08:35:40 PM PDT 24 4584027710 ps
T406 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.1742707424 Aug 11 08:16:18 PM PDT 24 Aug 11 08:31:14 PM PDT 24 9340800308 ps
T407 /workspace/coverage/default/94.chip_sw_all_escalation_resets.2767596366 Aug 11 08:25:21 PM PDT 24 Aug 11 08:34:13 PM PDT 24 5621669492 ps
T408 /workspace/coverage/default/67.chip_sw_all_escalation_resets.3849233139 Aug 11 08:23:27 PM PDT 24 Aug 11 08:36:01 PM PDT 24 5879875848 ps
T1369 /workspace/coverage/default/2.chip_sw_example_manufacturer.3847089082 Aug 11 08:05:01 PM PDT 24 Aug 11 08:08:07 PM PDT 24 2721753568 ps
T68 /workspace/coverage/default/0.chip_sw_usbdev_pullup.3465823661 Aug 11 07:33:30 PM PDT 24 Aug 11 07:36:53 PM PDT 24 2248773616 ps
T1370 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3730689586 Aug 11 07:37:56 PM PDT 24 Aug 11 08:53:15 PM PDT 24 17884275980 ps
T544 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2306281655 Aug 11 07:55:25 PM PDT 24 Aug 11 08:09:21 PM PDT 24 5669982774 ps
T881 /workspace/coverage/default/33.chip_sw_all_escalation_resets.3765279927 Aug 11 08:25:01 PM PDT 24 Aug 11 08:39:10 PM PDT 24 5634331168 ps
T1371 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.582999564 Aug 11 07:51:31 PM PDT 24 Aug 11 09:34:31 PM PDT 24 51653838314 ps
T1372 /workspace/coverage/default/0.rom_e2e_static_critical.2371400508 Aug 11 07:51:19 PM PDT 24 Aug 11 09:08:27 PM PDT 24 17420924240 ps
T414 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.50220855 Aug 11 07:43:32 PM PDT 24 Aug 11 07:49:11 PM PDT 24 7035967588 ps
T1373 /workspace/coverage/default/2.chip_sw_gpio_smoketest.1870127415 Aug 11 08:15:09 PM PDT 24 Aug 11 08:20:54 PM PDT 24 2805563837 ps
T1374 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.626144011 Aug 11 08:09:38 PM PDT 24 Aug 11 08:33:04 PM PDT 24 8251058094 ps
T800 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1994633693 Aug 11 08:15:01 PM PDT 24 Aug 11 08:23:02 PM PDT 24 3812087212 ps
T774 /workspace/coverage/default/1.chip_sw_power_sleep_load.532481452 Aug 11 07:59:14 PM PDT 24 Aug 11 08:08:06 PM PDT 24 4938565444 ps
T1375 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2413172147 Aug 11 07:36:56 PM PDT 24 Aug 11 07:44:19 PM PDT 24 5254654138 ps
T1376 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1011392811 Aug 11 07:44:41 PM PDT 24 Aug 11 07:54:56 PM PDT 24 5166368068 ps
T846 /workspace/coverage/default/37.chip_sw_all_escalation_resets.2061718864 Aug 11 08:21:35 PM PDT 24 Aug 11 08:35:55 PM PDT 24 5862401660 ps
T1377 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2953752559 Aug 11 07:36:31 PM PDT 24 Aug 11 08:26:45 PM PDT 24 35644830201 ps
T1378 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1403760928 Aug 11 08:00:30 PM PDT 24 Aug 11 08:04:05 PM PDT 24 3042179832 ps
T97 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.56628956 Aug 11 07:57:26 PM PDT 24 Aug 11 08:03:20 PM PDT 24 3883354792 ps
T1379 /workspace/coverage/default/1.chip_sw_kmac_app_rom.2800670846 Aug 11 07:58:33 PM PDT 24 Aug 11 08:03:17 PM PDT 24 3514018920 ps
T1380 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1060217037 Aug 11 07:51:28 PM PDT 24 Aug 11 08:48:25 PM PDT 24 11487476836 ps
T1381 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.718424435 Aug 11 07:57:45 PM PDT 24 Aug 11 08:28:43 PM PDT 24 10319867776 ps
T1382 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3922529796 Aug 11 07:54:19 PM PDT 24 Aug 11 08:06:35 PM PDT 24 5799867298 ps
T1383 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.902968436 Aug 11 08:08:48 PM PDT 24 Aug 11 08:13:04 PM PDT 24 2859233256 ps
T1384 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.732735346 Aug 11 07:57:01 PM PDT 24 Aug 11 08:03:45 PM PDT 24 3281479232 ps
T346 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.2236573892 Aug 11 07:50:57 PM PDT 24 Aug 11 08:05:07 PM PDT 24 5323253816 ps
T69 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.4186994532 Aug 11 07:37:45 PM PDT 24 Aug 11 07:47:42 PM PDT 24 4311277018 ps
T1385 /workspace/coverage/default/0.chip_sw_usbdev_vbus.249003715 Aug 11 07:36:21 PM PDT 24 Aug 11 07:41:30 PM PDT 24 3463138080 ps
T1386 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.1998575228 Aug 11 08:16:06 PM PDT 24 Aug 11 09:04:46 PM PDT 24 11157309344 ps
T1387 /workspace/coverage/default/0.chip_tap_straps_testunlock0.1653141217 Aug 11 07:42:30 PM PDT 24 Aug 11 07:49:31 PM PDT 24 4579493429 ps
T1388 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.629212083 Aug 11 08:10:53 PM PDT 24 Aug 11 08:21:11 PM PDT 24 4200692292 ps
T831 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1381417298 Aug 11 08:25:12 PM PDT 24 Aug 11 08:31:17 PM PDT 24 3408309808 ps
T1389 /workspace/coverage/default/2.chip_sw_all_escalation_resets.1081715182 Aug 11 08:02:42 PM PDT 24 Aug 11 08:13:42 PM PDT 24 4875055736 ps
T1390 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.427827873 Aug 11 08:06:48 PM PDT 24 Aug 11 08:18:34 PM PDT 24 19718452122 ps
T1391 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.794612243 Aug 11 08:01:44 PM PDT 24 Aug 11 08:13:15 PM PDT 24 3595720776 ps
T1392 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3269173734 Aug 11 07:52:29 PM PDT 24 Aug 11 08:01:41 PM PDT 24 4165845218 ps
T369 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3504686823 Aug 11 07:58:50 PM PDT 24 Aug 11 08:05:16 PM PDT 24 6357453080 ps
T1393 /workspace/coverage/default/2.chip_sw_aes_idle.1381014428 Aug 11 08:06:49 PM PDT 24 Aug 11 08:11:18 PM PDT 24 3085784640 ps
T827 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1530104545 Aug 11 08:17:18 PM PDT 24 Aug 11 08:25:49 PM PDT 24 3728348208 ps
T1394 /workspace/coverage/default/14.chip_sw_all_escalation_resets.2257247476 Aug 11 08:16:52 PM PDT 24 Aug 11 08:29:50 PM PDT 24 5975928444 ps
T1395 /workspace/coverage/default/0.chip_sw_csrng_kat_test.980846306 Aug 11 07:38:49 PM PDT 24 Aug 11 07:42:56 PM PDT 24 3304491136 ps
T1396 /workspace/coverage/default/4.chip_sw_uart_tx_rx.3810151737 Aug 11 08:13:53 PM PDT 24 Aug 11 08:24:59 PM PDT 24 4657434220 ps
T326 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.3383068989 Aug 11 07:57:39 PM PDT 24 Aug 11 08:31:42 PM PDT 24 7684874180 ps
T1397 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3813770012 Aug 11 08:09:07 PM PDT 24 Aug 11 08:19:58 PM PDT 24 5338018040 ps
T1398 /workspace/coverage/default/89.chip_sw_all_escalation_resets.1234709699 Aug 11 08:35:40 PM PDT 24 Aug 11 08:43:46 PM PDT 24 4996719300 ps
T1399 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.923776965 Aug 11 07:42:34 PM PDT 24 Aug 11 07:47:28 PM PDT 24 4233540370 ps
T256 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2192872100 Aug 11 08:05:26 PM PDT 24 Aug 11 08:19:44 PM PDT 24 7321344732 ps
T1400 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.4218360033 Aug 11 07:43:44 PM PDT 24 Aug 11 07:47:50 PM PDT 24 2965375532 ps
T1401 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2360720185 Aug 11 07:39:56 PM PDT 24 Aug 11 07:54:41 PM PDT 24 7657569924 ps
T1402 /workspace/coverage/default/21.chip_sw_all_escalation_resets.2226038845 Aug 11 08:19:44 PM PDT 24 Aug 11 08:30:04 PM PDT 24 4419976880 ps
T1403 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3058178897 Aug 11 08:06:51 PM PDT 24 Aug 11 09:05:03 PM PDT 24 18912050426 ps
T1404 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1061919017 Aug 11 08:09:07 PM PDT 24 Aug 11 08:36:13 PM PDT 24 8137959126 ps
T1405 /workspace/coverage/default/50.chip_sw_all_escalation_resets.2528743574 Aug 11 08:22:16 PM PDT 24 Aug 11 08:36:44 PM PDT 24 6503347312 ps
T1406 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1310058724 Aug 11 07:56:57 PM PDT 24 Aug 11 08:06:40 PM PDT 24 8904674866 ps
T885 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1827439471 Aug 11 08:19:23 PM PDT 24 Aug 11 08:25:21 PM PDT 24 4007460700 ps
T1407 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3231764985 Aug 11 07:38:31 PM PDT 24 Aug 11 08:52:51 PM PDT 24 19254956807 ps
T1408 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.448253409 Aug 11 07:52:30 PM PDT 24 Aug 11 09:08:59 PM PDT 24 15481123520 ps
T805 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.450621870 Aug 11 08:27:25 PM PDT 24 Aug 11 08:33:38 PM PDT 24 3727507428 ps
T1409 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.3016964794 Aug 11 08:19:07 PM PDT 24 Aug 11 08:59:23 PM PDT 24 12488774492 ps
T1410 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.2278477918 Aug 11 08:13:54 PM PDT 24 Aug 11 08:17:35 PM PDT 24 2502058504 ps
T860 /workspace/coverage/default/63.chip_sw_all_escalation_resets.3703907016 Aug 11 08:23:01 PM PDT 24 Aug 11 08:32:07 PM PDT 24 4713688800 ps
T1411 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.343674133 Aug 11 08:24:44 PM PDT 24 Aug 11 08:33:15 PM PDT 24 3959897800 ps
T1412 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.731297978 Aug 11 07:58:24 PM PDT 24 Aug 11 08:10:05 PM PDT 24 4994169080 ps
T126 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1103445252 Aug 11 08:17:29 PM PDT 24 Aug 11 08:32:10 PM PDT 24 6303745304 ps
T438 /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.1955794401 Aug 11 07:49:18 PM PDT 24 Aug 11 08:25:17 PM PDT 24 25115424802 ps
T784 /workspace/coverage/default/2.rom_raw_unlock.3630401060 Aug 11 08:13:41 PM PDT 24 Aug 11 08:17:29 PM PDT 24 5722529403 ps
T1413 /workspace/coverage/default/1.chip_tap_straps_testunlock0.356329439 Aug 11 07:57:03 PM PDT 24 Aug 11 08:11:03 PM PDT 24 7885738880 ps
T1414 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1589605674 Aug 11 07:42:44 PM PDT 24 Aug 11 07:50:36 PM PDT 24 5004466280 ps
T1415 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1164769865 Aug 11 07:39:54 PM PDT 24 Aug 11 07:43:29 PM PDT 24 3070655926 ps
T1416 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1094902458 Aug 11 08:17:06 PM PDT 24 Aug 11 08:28:54 PM PDT 24 4336259768 ps
T1417 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3773508351 Aug 11 08:10:23 PM PDT 24 Aug 11 08:29:59 PM PDT 24 6922833720 ps
T323 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2738720352 Aug 11 07:38:49 PM PDT 24 Aug 11 08:09:47 PM PDT 24 12030533890 ps
T27 /workspace/coverage/default/0.chip_sw_gpio.2822752477 Aug 11 07:34:02 PM PDT 24 Aug 11 07:40:37 PM PDT 24 3842851802 ps
T1418 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.903761087 Aug 11 08:04:25 PM PDT 24 Aug 11 08:06:20 PM PDT 24 1692130078 ps
T1419 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.4069746457 Aug 11 08:06:19 PM PDT 24 Aug 11 08:12:44 PM PDT 24 4162554958 ps
T897 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2838033529 Aug 11 08:21:48 PM PDT 24 Aug 11 08:28:39 PM PDT 24 3320090706 ps
T1420 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.989079195 Aug 11 08:04:46 PM PDT 24 Aug 11 08:12:19 PM PDT 24 5341508136 ps
T1421 /workspace/coverage/default/1.rom_e2e_asm_init_rma.588964139 Aug 11 08:05:16 PM PDT 24 Aug 11 09:12:45 PM PDT 24 14756345735 ps
T267 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.3187084124 Aug 11 08:14:16 PM PDT 24 Aug 11 08:23:29 PM PDT 24 4806600948 ps
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